1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /**************************************************************************** 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Driver for the IFX spi modem. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2009, 2010 Intel Corp 7*4882a593Smuzhiyun * Jim Stanley <jim.stanley@intel.com> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun *****************************************************************************/ 10*4882a593Smuzhiyun #ifndef _IFX6X60_H 11*4882a593Smuzhiyun #define _IFX6X60_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct gpio_desc; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define DRVNAME "ifx6x60" 16*4882a593Smuzhiyun #define TTYNAME "ttyIFX" 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define IFX_SPI_MAX_MINORS 1 19*4882a593Smuzhiyun #define IFX_SPI_TRANSFER_SIZE 2048 20*4882a593Smuzhiyun #define IFX_SPI_FIFO_SIZE 4096 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define IFX_SPI_HEADER_OVERHEAD 4 23*4882a593Smuzhiyun #define IFX_RESET_TIMEOUT msecs_to_jiffies(50) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* device flags bitfield definitions */ 26*4882a593Smuzhiyun #define IFX_SPI_STATE_PRESENT 0 27*4882a593Smuzhiyun #define IFX_SPI_STATE_IO_IN_PROGRESS 1 28*4882a593Smuzhiyun #define IFX_SPI_STATE_IO_READY 2 29*4882a593Smuzhiyun #define IFX_SPI_STATE_TIMER_PENDING 3 30*4882a593Smuzhiyun #define IFX_SPI_STATE_IO_AVAILABLE 4 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* flow control bitfields */ 33*4882a593Smuzhiyun #define IFX_SPI_DCD 0 34*4882a593Smuzhiyun #define IFX_SPI_CTS 1 35*4882a593Smuzhiyun #define IFX_SPI_DSR 2 36*4882a593Smuzhiyun #define IFX_SPI_RI 3 37*4882a593Smuzhiyun #define IFX_SPI_DTR 4 38*4882a593Smuzhiyun #define IFX_SPI_RTS 5 39*4882a593Smuzhiyun #define IFX_SPI_TX_FC 6 40*4882a593Smuzhiyun #define IFX_SPI_RX_FC 7 41*4882a593Smuzhiyun #define IFX_SPI_UPDATE 8 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define IFX_SPI_PAYLOAD_SIZE (IFX_SPI_TRANSFER_SIZE - \ 44*4882a593Smuzhiyun IFX_SPI_HEADER_OVERHEAD) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define IFX_SPI_IRQ_TYPE DETECT_EDGE_RISING 47*4882a593Smuzhiyun #define IFX_SPI_GPIO_TARGET 0 48*4882a593Smuzhiyun #define IFX_SPI_GPIO0 0x105 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define IFX_SPI_STATUS_TIMEOUT (2000*HZ) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* values for bits in power status byte */ 53*4882a593Smuzhiyun #define IFX_SPI_POWER_DATA_PENDING 1 54*4882a593Smuzhiyun #define IFX_SPI_POWER_SRDY 2 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun struct ifx_spi_device { 57*4882a593Smuzhiyun /* Our SPI device */ 58*4882a593Smuzhiyun struct spi_device *spi_dev; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* Port specific data */ 61*4882a593Smuzhiyun struct kfifo tx_fifo; 62*4882a593Smuzhiyun spinlock_t fifo_lock; 63*4882a593Smuzhiyun unsigned long signal_state; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* TTY Layer logic */ 66*4882a593Smuzhiyun struct tty_port tty_port; 67*4882a593Smuzhiyun struct device *tty_dev; 68*4882a593Smuzhiyun int minor; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* Low level I/O work */ 71*4882a593Smuzhiyun struct tasklet_struct io_work_tasklet; 72*4882a593Smuzhiyun unsigned long flags; 73*4882a593Smuzhiyun dma_addr_t rx_dma; 74*4882a593Smuzhiyun dma_addr_t tx_dma; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun int modem; /* Modem type */ 77*4882a593Smuzhiyun int use_dma; /* provide dma-able addrs in SPI msg */ 78*4882a593Smuzhiyun long max_hz; /* max SPI frequency */ 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun spinlock_t write_lock; 81*4882a593Smuzhiyun int write_pending; 82*4882a593Smuzhiyun spinlock_t power_lock; 83*4882a593Smuzhiyun unsigned char power_status; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun unsigned char *rx_buffer; 86*4882a593Smuzhiyun unsigned char *tx_buffer; 87*4882a593Smuzhiyun dma_addr_t rx_bus; 88*4882a593Smuzhiyun dma_addr_t tx_bus; 89*4882a593Smuzhiyun unsigned char spi_more; 90*4882a593Smuzhiyun unsigned char spi_slave_cts; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun struct timer_list spi_timer; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun struct spi_message spi_msg; 95*4882a593Smuzhiyun struct spi_transfer spi_xfer; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun struct { 98*4882a593Smuzhiyun /* gpio lines */ 99*4882a593Smuzhiyun struct gpio_desc *srdy; /* slave-ready gpio */ 100*4882a593Smuzhiyun struct gpio_desc *mrdy; /* master-ready gpio */ 101*4882a593Smuzhiyun struct gpio_desc *reset; /* modem-reset gpio */ 102*4882a593Smuzhiyun struct gpio_desc *po; /* modem-on gpio */ 103*4882a593Smuzhiyun struct gpio_desc *reset_out; /* modem-in-reset gpio */ 104*4882a593Smuzhiyun struct gpio_desc *pmu_reset; /* PMU reset gpio */ 105*4882a593Smuzhiyun /* state/stats */ 106*4882a593Smuzhiyun int unack_srdy_int_nb; 107*4882a593Smuzhiyun } gpio; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* modem reset */ 110*4882a593Smuzhiyun unsigned long mdm_reset_state; 111*4882a593Smuzhiyun #define MR_START 0 112*4882a593Smuzhiyun #define MR_INPROGRESS 1 113*4882a593Smuzhiyun #define MR_COMPLETE 2 114*4882a593Smuzhiyun wait_queue_head_t mdm_reset_wait; 115*4882a593Smuzhiyun void (*swap_buf)(unsigned char *buf, int len, void *end); 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #endif /* _IFX6X60_H */ 119