1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * dz.c: Serial port driver for DECstations equipped
4*4882a593Smuzhiyun * with the DZ chipset.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 1998 Olivier A. D. Lebaillif
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Email: olivier.lebaillif@ifrsys.com
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Copyright (C) 2004, 2006, 2007 Maciej W. Rozycki
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * [31-AUG-98] triemer
13*4882a593Smuzhiyun * Changed IRQ to use Harald's dec internals interrupts.h
14*4882a593Smuzhiyun * removed base_addr code - moving address assignment to setup.c
15*4882a593Smuzhiyun * Changed name of dz_init to rs_init to be consistent with tc code
16*4882a593Smuzhiyun * [13-NOV-98] triemer fixed code to receive characters
17*4882a593Smuzhiyun * after patches by harald to irq code.
18*4882a593Smuzhiyun * [09-JAN-99] triemer minor fix for schedule - due to removal of timeout
19*4882a593Smuzhiyun * field from "current" - somewhere between 2.1.121 and 2.1.131
20*4882a593Smuzhiyun Qua Jun 27 15:02:26 BRT 2001
21*4882a593Smuzhiyun * [27-JUN-2001] Arnaldo Carvalho de Melo <acme@conectiva.com.br> - cleanups
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * Parts (C) 1999 David Airlie, airlied@linux.ie
24*4882a593Smuzhiyun * [07-SEP-99] Bugfixes
25*4882a593Smuzhiyun *
26*4882a593Smuzhiyun * [06-Jan-2002] Russell King <rmk@arm.linux.org.uk>
27*4882a593Smuzhiyun * Converted to new serial core
28*4882a593Smuzhiyun */
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #undef DEBUG_DZ
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #include <linux/bitops.h>
33*4882a593Smuzhiyun #include <linux/compiler.h>
34*4882a593Smuzhiyun #include <linux/console.h>
35*4882a593Smuzhiyun #include <linux/delay.h>
36*4882a593Smuzhiyun #include <linux/errno.h>
37*4882a593Smuzhiyun #include <linux/init.h>
38*4882a593Smuzhiyun #include <linux/interrupt.h>
39*4882a593Smuzhiyun #include <linux/ioport.h>
40*4882a593Smuzhiyun #include <linux/kernel.h>
41*4882a593Smuzhiyun #include <linux/major.h>
42*4882a593Smuzhiyun #include <linux/module.h>
43*4882a593Smuzhiyun #include <linux/serial.h>
44*4882a593Smuzhiyun #include <linux/serial_core.h>
45*4882a593Smuzhiyun #include <linux/sysrq.h>
46*4882a593Smuzhiyun #include <linux/tty.h>
47*4882a593Smuzhiyun #include <linux/tty_flip.h>
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #include <linux/atomic.h>
50*4882a593Smuzhiyun #include <asm/bootinfo.h>
51*4882a593Smuzhiyun #include <asm/io.h>
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #include <asm/dec/interrupts.h>
54*4882a593Smuzhiyun #include <asm/dec/kn01.h>
55*4882a593Smuzhiyun #include <asm/dec/kn02.h>
56*4882a593Smuzhiyun #include <asm/dec/machtype.h>
57*4882a593Smuzhiyun #include <asm/dec/prom.h>
58*4882a593Smuzhiyun #include <asm/dec/system.h>
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #include "dz.h"
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun MODULE_DESCRIPTION("DECstation DZ serial driver");
64*4882a593Smuzhiyun MODULE_LICENSE("GPL");
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun static char dz_name[] __initdata = "DECstation DZ serial driver version ";
68*4882a593Smuzhiyun static char dz_version[] __initdata = "1.04";
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun struct dz_port {
71*4882a593Smuzhiyun struct dz_mux *mux;
72*4882a593Smuzhiyun struct uart_port port;
73*4882a593Smuzhiyun unsigned int cflag;
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun struct dz_mux {
77*4882a593Smuzhiyun struct dz_port dport[DZ_NB_PORT];
78*4882a593Smuzhiyun atomic_t map_guard;
79*4882a593Smuzhiyun atomic_t irq_guard;
80*4882a593Smuzhiyun int initialised;
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun static struct dz_mux dz_mux;
84*4882a593Smuzhiyun
to_dport(struct uart_port * uport)85*4882a593Smuzhiyun static inline struct dz_port *to_dport(struct uart_port *uport)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun return container_of(uport, struct dz_port, port);
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /*
91*4882a593Smuzhiyun * ------------------------------------------------------------
92*4882a593Smuzhiyun * dz_in () and dz_out ()
93*4882a593Smuzhiyun *
94*4882a593Smuzhiyun * These routines are used to access the registers of the DZ
95*4882a593Smuzhiyun * chip, hiding relocation differences between implementation.
96*4882a593Smuzhiyun * ------------------------------------------------------------
97*4882a593Smuzhiyun */
98*4882a593Smuzhiyun
dz_in(struct dz_port * dport,unsigned offset)99*4882a593Smuzhiyun static u16 dz_in(struct dz_port *dport, unsigned offset)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun void __iomem *addr = dport->port.membase + offset;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun return readw(addr);
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
dz_out(struct dz_port * dport,unsigned offset,u16 value)106*4882a593Smuzhiyun static void dz_out(struct dz_port *dport, unsigned offset, u16 value)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun void __iomem *addr = dport->port.membase + offset;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun writew(value, addr);
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /*
114*4882a593Smuzhiyun * ------------------------------------------------------------
115*4882a593Smuzhiyun * rs_stop () and rs_start ()
116*4882a593Smuzhiyun *
117*4882a593Smuzhiyun * These routines are called before setting or resetting
118*4882a593Smuzhiyun * tty->stopped. They enable or disable transmitter interrupts,
119*4882a593Smuzhiyun * as necessary.
120*4882a593Smuzhiyun * ------------------------------------------------------------
121*4882a593Smuzhiyun */
122*4882a593Smuzhiyun
dz_stop_tx(struct uart_port * uport)123*4882a593Smuzhiyun static void dz_stop_tx(struct uart_port *uport)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun struct dz_port *dport = to_dport(uport);
126*4882a593Smuzhiyun u16 tmp, mask = 1 << dport->port.line;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun tmp = dz_in(dport, DZ_TCR); /* read the TX flag */
129*4882a593Smuzhiyun tmp &= ~mask; /* clear the TX flag */
130*4882a593Smuzhiyun dz_out(dport, DZ_TCR, tmp);
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
dz_start_tx(struct uart_port * uport)133*4882a593Smuzhiyun static void dz_start_tx(struct uart_port *uport)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun struct dz_port *dport = to_dport(uport);
136*4882a593Smuzhiyun u16 tmp, mask = 1 << dport->port.line;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun tmp = dz_in(dport, DZ_TCR); /* read the TX flag */
139*4882a593Smuzhiyun tmp |= mask; /* set the TX flag */
140*4882a593Smuzhiyun dz_out(dport, DZ_TCR, tmp);
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun
dz_stop_rx(struct uart_port * uport)143*4882a593Smuzhiyun static void dz_stop_rx(struct uart_port *uport)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun struct dz_port *dport = to_dport(uport);
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun dport->cflag &= ~DZ_RXENAB;
148*4882a593Smuzhiyun dz_out(dport, DZ_LPR, dport->cflag);
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun /*
152*4882a593Smuzhiyun * ------------------------------------------------------------
153*4882a593Smuzhiyun *
154*4882a593Smuzhiyun * Here start the interrupt handling routines. All of the following
155*4882a593Smuzhiyun * subroutines are declared as inline and are folded into
156*4882a593Smuzhiyun * dz_interrupt. They were separated out for readability's sake.
157*4882a593Smuzhiyun *
158*4882a593Smuzhiyun * Note: dz_interrupt() is a "fast" interrupt, which means that it
159*4882a593Smuzhiyun * runs with interrupts turned off. People who may want to modify
160*4882a593Smuzhiyun * dz_interrupt() should try to keep the interrupt handler as fast as
161*4882a593Smuzhiyun * possible. After you are done making modifications, it is not a bad
162*4882a593Smuzhiyun * idea to do:
163*4882a593Smuzhiyun *
164*4882a593Smuzhiyun * make drivers/serial/dz.s
165*4882a593Smuzhiyun *
166*4882a593Smuzhiyun * and look at the resulting assemble code in dz.s.
167*4882a593Smuzhiyun *
168*4882a593Smuzhiyun * ------------------------------------------------------------
169*4882a593Smuzhiyun */
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun /*
172*4882a593Smuzhiyun * ------------------------------------------------------------
173*4882a593Smuzhiyun * receive_char ()
174*4882a593Smuzhiyun *
175*4882a593Smuzhiyun * This routine deals with inputs from any lines.
176*4882a593Smuzhiyun * ------------------------------------------------------------
177*4882a593Smuzhiyun */
dz_receive_chars(struct dz_mux * mux)178*4882a593Smuzhiyun static inline void dz_receive_chars(struct dz_mux *mux)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun struct uart_port *uport;
181*4882a593Smuzhiyun struct dz_port *dport = &mux->dport[0];
182*4882a593Smuzhiyun struct uart_icount *icount;
183*4882a593Smuzhiyun int lines_rx[DZ_NB_PORT] = { [0 ... DZ_NB_PORT - 1] = 0 };
184*4882a593Smuzhiyun unsigned char ch, flag;
185*4882a593Smuzhiyun u16 status;
186*4882a593Smuzhiyun int i;
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun while ((status = dz_in(dport, DZ_RBUF)) & DZ_DVAL) {
189*4882a593Smuzhiyun dport = &mux->dport[LINE(status)];
190*4882a593Smuzhiyun uport = &dport->port;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun ch = UCHAR(status); /* grab the char */
193*4882a593Smuzhiyun flag = TTY_NORMAL;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun icount = &uport->icount;
196*4882a593Smuzhiyun icount->rx++;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun if (unlikely(status & (DZ_OERR | DZ_FERR | DZ_PERR))) {
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun /*
201*4882a593Smuzhiyun * There is no separate BREAK status bit, so treat
202*4882a593Smuzhiyun * null characters with framing errors as BREAKs;
203*4882a593Smuzhiyun * normally, otherwise. For this move the Framing
204*4882a593Smuzhiyun * Error bit to a simulated BREAK bit.
205*4882a593Smuzhiyun */
206*4882a593Smuzhiyun if (!ch) {
207*4882a593Smuzhiyun status |= (status & DZ_FERR) >>
208*4882a593Smuzhiyun (ffs(DZ_FERR) - ffs(DZ_BREAK));
209*4882a593Smuzhiyun status &= ~DZ_FERR;
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun /* Handle SysRq/SAK & keep track of the statistics. */
213*4882a593Smuzhiyun if (status & DZ_BREAK) {
214*4882a593Smuzhiyun icount->brk++;
215*4882a593Smuzhiyun if (uart_handle_break(uport))
216*4882a593Smuzhiyun continue;
217*4882a593Smuzhiyun } else if (status & DZ_FERR)
218*4882a593Smuzhiyun icount->frame++;
219*4882a593Smuzhiyun else if (status & DZ_PERR)
220*4882a593Smuzhiyun icount->parity++;
221*4882a593Smuzhiyun if (status & DZ_OERR)
222*4882a593Smuzhiyun icount->overrun++;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun status &= uport->read_status_mask;
225*4882a593Smuzhiyun if (status & DZ_BREAK)
226*4882a593Smuzhiyun flag = TTY_BREAK;
227*4882a593Smuzhiyun else if (status & DZ_FERR)
228*4882a593Smuzhiyun flag = TTY_FRAME;
229*4882a593Smuzhiyun else if (status & DZ_PERR)
230*4882a593Smuzhiyun flag = TTY_PARITY;
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun if (uart_handle_sysrq_char(uport, ch))
235*4882a593Smuzhiyun continue;
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun uart_insert_char(uport, status, DZ_OERR, ch, flag);
238*4882a593Smuzhiyun lines_rx[LINE(status)] = 1;
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun for (i = 0; i < DZ_NB_PORT; i++)
241*4882a593Smuzhiyun if (lines_rx[i])
242*4882a593Smuzhiyun tty_flip_buffer_push(&mux->dport[i].port.state->port);
243*4882a593Smuzhiyun }
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun /*
246*4882a593Smuzhiyun * ------------------------------------------------------------
247*4882a593Smuzhiyun * transmit_char ()
248*4882a593Smuzhiyun *
249*4882a593Smuzhiyun * This routine deals with outputs to any lines.
250*4882a593Smuzhiyun * ------------------------------------------------------------
251*4882a593Smuzhiyun */
dz_transmit_chars(struct dz_mux * mux)252*4882a593Smuzhiyun static inline void dz_transmit_chars(struct dz_mux *mux)
253*4882a593Smuzhiyun {
254*4882a593Smuzhiyun struct dz_port *dport = &mux->dport[0];
255*4882a593Smuzhiyun struct circ_buf *xmit;
256*4882a593Smuzhiyun unsigned char tmp;
257*4882a593Smuzhiyun u16 status;
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun status = dz_in(dport, DZ_CSR);
260*4882a593Smuzhiyun dport = &mux->dport[LINE(status)];
261*4882a593Smuzhiyun xmit = &dport->port.state->xmit;
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun if (dport->port.x_char) { /* XON/XOFF chars */
264*4882a593Smuzhiyun dz_out(dport, DZ_TDR, dport->port.x_char);
265*4882a593Smuzhiyun dport->port.icount.tx++;
266*4882a593Smuzhiyun dport->port.x_char = 0;
267*4882a593Smuzhiyun return;
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun /* If nothing to do or stopped or hardware stopped. */
270*4882a593Smuzhiyun if (uart_circ_empty(xmit) || uart_tx_stopped(&dport->port)) {
271*4882a593Smuzhiyun spin_lock(&dport->port.lock);
272*4882a593Smuzhiyun dz_stop_tx(&dport->port);
273*4882a593Smuzhiyun spin_unlock(&dport->port.lock);
274*4882a593Smuzhiyun return;
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun /*
278*4882a593Smuzhiyun * If something to do... (remember the dz has no output fifo,
279*4882a593Smuzhiyun * so we go one char at a time) :-<
280*4882a593Smuzhiyun */
281*4882a593Smuzhiyun tmp = xmit->buf[xmit->tail];
282*4882a593Smuzhiyun xmit->tail = (xmit->tail + 1) & (DZ_XMIT_SIZE - 1);
283*4882a593Smuzhiyun dz_out(dport, DZ_TDR, tmp);
284*4882a593Smuzhiyun dport->port.icount.tx++;
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun if (uart_circ_chars_pending(xmit) < DZ_WAKEUP_CHARS)
287*4882a593Smuzhiyun uart_write_wakeup(&dport->port);
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun /* Are we are done. */
290*4882a593Smuzhiyun if (uart_circ_empty(xmit)) {
291*4882a593Smuzhiyun spin_lock(&dport->port.lock);
292*4882a593Smuzhiyun dz_stop_tx(&dport->port);
293*4882a593Smuzhiyun spin_unlock(&dport->port.lock);
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun /*
298*4882a593Smuzhiyun * ------------------------------------------------------------
299*4882a593Smuzhiyun * check_modem_status()
300*4882a593Smuzhiyun *
301*4882a593Smuzhiyun * DS 3100 & 5100: Only valid for the MODEM line, duh!
302*4882a593Smuzhiyun * DS 5000/200: Valid for the MODEM and PRINTER line.
303*4882a593Smuzhiyun * ------------------------------------------------------------
304*4882a593Smuzhiyun */
check_modem_status(struct dz_port * dport)305*4882a593Smuzhiyun static inline void check_modem_status(struct dz_port *dport)
306*4882a593Smuzhiyun {
307*4882a593Smuzhiyun /*
308*4882a593Smuzhiyun * FIXME:
309*4882a593Smuzhiyun * 1. No status change interrupt; use a timer.
310*4882a593Smuzhiyun * 2. Handle the 3100/5000 as appropriate. --macro
311*4882a593Smuzhiyun */
312*4882a593Smuzhiyun u16 status;
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun /* If not the modem line just return. */
315*4882a593Smuzhiyun if (dport->port.line != DZ_MODEM)
316*4882a593Smuzhiyun return;
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun status = dz_in(dport, DZ_MSR);
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun /* it's easy, since DSR2 is the only bit in the register */
321*4882a593Smuzhiyun if (status)
322*4882a593Smuzhiyun dport->port.icount.dsr++;
323*4882a593Smuzhiyun }
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun /*
326*4882a593Smuzhiyun * ------------------------------------------------------------
327*4882a593Smuzhiyun * dz_interrupt ()
328*4882a593Smuzhiyun *
329*4882a593Smuzhiyun * this is the main interrupt routine for the DZ chip.
330*4882a593Smuzhiyun * It deals with the multiple ports.
331*4882a593Smuzhiyun * ------------------------------------------------------------
332*4882a593Smuzhiyun */
dz_interrupt(int irq,void * dev_id)333*4882a593Smuzhiyun static irqreturn_t dz_interrupt(int irq, void *dev_id)
334*4882a593Smuzhiyun {
335*4882a593Smuzhiyun struct dz_mux *mux = dev_id;
336*4882a593Smuzhiyun struct dz_port *dport = &mux->dport[0];
337*4882a593Smuzhiyun u16 status;
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun /* get the reason why we just got an irq */
340*4882a593Smuzhiyun status = dz_in(dport, DZ_CSR);
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun if ((status & (DZ_RDONE | DZ_RIE)) == (DZ_RDONE | DZ_RIE))
343*4882a593Smuzhiyun dz_receive_chars(mux);
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun if ((status & (DZ_TRDY | DZ_TIE)) == (DZ_TRDY | DZ_TIE))
346*4882a593Smuzhiyun dz_transmit_chars(mux);
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun return IRQ_HANDLED;
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun /*
352*4882a593Smuzhiyun * -------------------------------------------------------------------
353*4882a593Smuzhiyun * Here ends the DZ interrupt routines.
354*4882a593Smuzhiyun * -------------------------------------------------------------------
355*4882a593Smuzhiyun */
356*4882a593Smuzhiyun
dz_get_mctrl(struct uart_port * uport)357*4882a593Smuzhiyun static unsigned int dz_get_mctrl(struct uart_port *uport)
358*4882a593Smuzhiyun {
359*4882a593Smuzhiyun /*
360*4882a593Smuzhiyun * FIXME: Handle the 3100/5000 as appropriate. --macro
361*4882a593Smuzhiyun */
362*4882a593Smuzhiyun struct dz_port *dport = to_dport(uport);
363*4882a593Smuzhiyun unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun if (dport->port.line == DZ_MODEM) {
366*4882a593Smuzhiyun if (dz_in(dport, DZ_MSR) & DZ_MODEM_DSR)
367*4882a593Smuzhiyun mctrl &= ~TIOCM_DSR;
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun return mctrl;
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun
dz_set_mctrl(struct uart_port * uport,unsigned int mctrl)373*4882a593Smuzhiyun static void dz_set_mctrl(struct uart_port *uport, unsigned int mctrl)
374*4882a593Smuzhiyun {
375*4882a593Smuzhiyun /*
376*4882a593Smuzhiyun * FIXME: Handle the 3100/5000 as appropriate. --macro
377*4882a593Smuzhiyun */
378*4882a593Smuzhiyun struct dz_port *dport = to_dport(uport);
379*4882a593Smuzhiyun u16 tmp;
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun if (dport->port.line == DZ_MODEM) {
382*4882a593Smuzhiyun tmp = dz_in(dport, DZ_TCR);
383*4882a593Smuzhiyun if (mctrl & TIOCM_DTR)
384*4882a593Smuzhiyun tmp &= ~DZ_MODEM_DTR;
385*4882a593Smuzhiyun else
386*4882a593Smuzhiyun tmp |= DZ_MODEM_DTR;
387*4882a593Smuzhiyun dz_out(dport, DZ_TCR, tmp);
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun }
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun /*
392*4882a593Smuzhiyun * -------------------------------------------------------------------
393*4882a593Smuzhiyun * startup ()
394*4882a593Smuzhiyun *
395*4882a593Smuzhiyun * various initialization tasks
396*4882a593Smuzhiyun * -------------------------------------------------------------------
397*4882a593Smuzhiyun */
dz_startup(struct uart_port * uport)398*4882a593Smuzhiyun static int dz_startup(struct uart_port *uport)
399*4882a593Smuzhiyun {
400*4882a593Smuzhiyun struct dz_port *dport = to_dport(uport);
401*4882a593Smuzhiyun struct dz_mux *mux = dport->mux;
402*4882a593Smuzhiyun unsigned long flags;
403*4882a593Smuzhiyun int irq_guard;
404*4882a593Smuzhiyun int ret;
405*4882a593Smuzhiyun u16 tmp;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun irq_guard = atomic_add_return(1, &mux->irq_guard);
408*4882a593Smuzhiyun if (irq_guard != 1)
409*4882a593Smuzhiyun return 0;
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun ret = request_irq(dport->port.irq, dz_interrupt,
412*4882a593Smuzhiyun IRQF_SHARED, "dz", mux);
413*4882a593Smuzhiyun if (ret) {
414*4882a593Smuzhiyun atomic_add(-1, &mux->irq_guard);
415*4882a593Smuzhiyun printk(KERN_ERR "dz: Cannot get IRQ %d!\n", dport->port.irq);
416*4882a593Smuzhiyun return ret;
417*4882a593Smuzhiyun }
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun spin_lock_irqsave(&dport->port.lock, flags);
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun /* Enable interrupts. */
422*4882a593Smuzhiyun tmp = dz_in(dport, DZ_CSR);
423*4882a593Smuzhiyun tmp |= DZ_RIE | DZ_TIE;
424*4882a593Smuzhiyun dz_out(dport, DZ_CSR, tmp);
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun spin_unlock_irqrestore(&dport->port.lock, flags);
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun return 0;
429*4882a593Smuzhiyun }
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun /*
432*4882a593Smuzhiyun * -------------------------------------------------------------------
433*4882a593Smuzhiyun * shutdown ()
434*4882a593Smuzhiyun *
435*4882a593Smuzhiyun * This routine will shutdown a serial port; interrupts are disabled, and
436*4882a593Smuzhiyun * DTR is dropped if the hangup on close termio flag is on.
437*4882a593Smuzhiyun * -------------------------------------------------------------------
438*4882a593Smuzhiyun */
dz_shutdown(struct uart_port * uport)439*4882a593Smuzhiyun static void dz_shutdown(struct uart_port *uport)
440*4882a593Smuzhiyun {
441*4882a593Smuzhiyun struct dz_port *dport = to_dport(uport);
442*4882a593Smuzhiyun struct dz_mux *mux = dport->mux;
443*4882a593Smuzhiyun unsigned long flags;
444*4882a593Smuzhiyun int irq_guard;
445*4882a593Smuzhiyun u16 tmp;
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun spin_lock_irqsave(&dport->port.lock, flags);
448*4882a593Smuzhiyun dz_stop_tx(&dport->port);
449*4882a593Smuzhiyun spin_unlock_irqrestore(&dport->port.lock, flags);
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun irq_guard = atomic_add_return(-1, &mux->irq_guard);
452*4882a593Smuzhiyun if (!irq_guard) {
453*4882a593Smuzhiyun /* Disable interrupts. */
454*4882a593Smuzhiyun tmp = dz_in(dport, DZ_CSR);
455*4882a593Smuzhiyun tmp &= ~(DZ_RIE | DZ_TIE);
456*4882a593Smuzhiyun dz_out(dport, DZ_CSR, tmp);
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun free_irq(dport->port.irq, mux);
459*4882a593Smuzhiyun }
460*4882a593Smuzhiyun }
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun /*
463*4882a593Smuzhiyun * -------------------------------------------------------------------
464*4882a593Smuzhiyun * dz_tx_empty() -- get the transmitter empty status
465*4882a593Smuzhiyun *
466*4882a593Smuzhiyun * Purpose: Let user call ioctl() to get info when the UART physically
467*4882a593Smuzhiyun * is emptied. On bus types like RS485, the transmitter must
468*4882a593Smuzhiyun * release the bus after transmitting. This must be done when
469*4882a593Smuzhiyun * the transmit shift register is empty, not be done when the
470*4882a593Smuzhiyun * transmit holding register is empty. This functionality
471*4882a593Smuzhiyun * allows an RS485 driver to be written in user space.
472*4882a593Smuzhiyun * -------------------------------------------------------------------
473*4882a593Smuzhiyun */
dz_tx_empty(struct uart_port * uport)474*4882a593Smuzhiyun static unsigned int dz_tx_empty(struct uart_port *uport)
475*4882a593Smuzhiyun {
476*4882a593Smuzhiyun struct dz_port *dport = to_dport(uport);
477*4882a593Smuzhiyun unsigned short tmp, mask = 1 << dport->port.line;
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun tmp = dz_in(dport, DZ_TCR);
480*4882a593Smuzhiyun tmp &= mask;
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun return tmp ? 0 : TIOCSER_TEMT;
483*4882a593Smuzhiyun }
484*4882a593Smuzhiyun
dz_break_ctl(struct uart_port * uport,int break_state)485*4882a593Smuzhiyun static void dz_break_ctl(struct uart_port *uport, int break_state)
486*4882a593Smuzhiyun {
487*4882a593Smuzhiyun /*
488*4882a593Smuzhiyun * FIXME: Can't access BREAK bits in TDR easily;
489*4882a593Smuzhiyun * reuse the code for polled TX. --macro
490*4882a593Smuzhiyun */
491*4882a593Smuzhiyun struct dz_port *dport = to_dport(uport);
492*4882a593Smuzhiyun unsigned long flags;
493*4882a593Smuzhiyun unsigned short tmp, mask = 1 << dport->port.line;
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun spin_lock_irqsave(&uport->lock, flags);
496*4882a593Smuzhiyun tmp = dz_in(dport, DZ_TCR);
497*4882a593Smuzhiyun if (break_state)
498*4882a593Smuzhiyun tmp |= mask;
499*4882a593Smuzhiyun else
500*4882a593Smuzhiyun tmp &= ~mask;
501*4882a593Smuzhiyun dz_out(dport, DZ_TCR, tmp);
502*4882a593Smuzhiyun spin_unlock_irqrestore(&uport->lock, flags);
503*4882a593Smuzhiyun }
504*4882a593Smuzhiyun
dz_encode_baud_rate(unsigned int baud)505*4882a593Smuzhiyun static int dz_encode_baud_rate(unsigned int baud)
506*4882a593Smuzhiyun {
507*4882a593Smuzhiyun switch (baud) {
508*4882a593Smuzhiyun case 50:
509*4882a593Smuzhiyun return DZ_B50;
510*4882a593Smuzhiyun case 75:
511*4882a593Smuzhiyun return DZ_B75;
512*4882a593Smuzhiyun case 110:
513*4882a593Smuzhiyun return DZ_B110;
514*4882a593Smuzhiyun case 134:
515*4882a593Smuzhiyun return DZ_B134;
516*4882a593Smuzhiyun case 150:
517*4882a593Smuzhiyun return DZ_B150;
518*4882a593Smuzhiyun case 300:
519*4882a593Smuzhiyun return DZ_B300;
520*4882a593Smuzhiyun case 600:
521*4882a593Smuzhiyun return DZ_B600;
522*4882a593Smuzhiyun case 1200:
523*4882a593Smuzhiyun return DZ_B1200;
524*4882a593Smuzhiyun case 1800:
525*4882a593Smuzhiyun return DZ_B1800;
526*4882a593Smuzhiyun case 2000:
527*4882a593Smuzhiyun return DZ_B2000;
528*4882a593Smuzhiyun case 2400:
529*4882a593Smuzhiyun return DZ_B2400;
530*4882a593Smuzhiyun case 3600:
531*4882a593Smuzhiyun return DZ_B3600;
532*4882a593Smuzhiyun case 4800:
533*4882a593Smuzhiyun return DZ_B4800;
534*4882a593Smuzhiyun case 7200:
535*4882a593Smuzhiyun return DZ_B7200;
536*4882a593Smuzhiyun case 9600:
537*4882a593Smuzhiyun return DZ_B9600;
538*4882a593Smuzhiyun default:
539*4882a593Smuzhiyun return -1;
540*4882a593Smuzhiyun }
541*4882a593Smuzhiyun }
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun
dz_reset(struct dz_port * dport)544*4882a593Smuzhiyun static void dz_reset(struct dz_port *dport)
545*4882a593Smuzhiyun {
546*4882a593Smuzhiyun struct dz_mux *mux = dport->mux;
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun if (mux->initialised)
549*4882a593Smuzhiyun return;
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun dz_out(dport, DZ_CSR, DZ_CLR);
552*4882a593Smuzhiyun while (dz_in(dport, DZ_CSR) & DZ_CLR);
553*4882a593Smuzhiyun iob();
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun /* Enable scanning. */
556*4882a593Smuzhiyun dz_out(dport, DZ_CSR, DZ_MSE);
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun mux->initialised = 1;
559*4882a593Smuzhiyun }
560*4882a593Smuzhiyun
dz_set_termios(struct uart_port * uport,struct ktermios * termios,struct ktermios * old_termios)561*4882a593Smuzhiyun static void dz_set_termios(struct uart_port *uport, struct ktermios *termios,
562*4882a593Smuzhiyun struct ktermios *old_termios)
563*4882a593Smuzhiyun {
564*4882a593Smuzhiyun struct dz_port *dport = to_dport(uport);
565*4882a593Smuzhiyun unsigned long flags;
566*4882a593Smuzhiyun unsigned int cflag, baud;
567*4882a593Smuzhiyun int bflag;
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun cflag = dport->port.line;
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun switch (termios->c_cflag & CSIZE) {
572*4882a593Smuzhiyun case CS5:
573*4882a593Smuzhiyun cflag |= DZ_CS5;
574*4882a593Smuzhiyun break;
575*4882a593Smuzhiyun case CS6:
576*4882a593Smuzhiyun cflag |= DZ_CS6;
577*4882a593Smuzhiyun break;
578*4882a593Smuzhiyun case CS7:
579*4882a593Smuzhiyun cflag |= DZ_CS7;
580*4882a593Smuzhiyun break;
581*4882a593Smuzhiyun case CS8:
582*4882a593Smuzhiyun default:
583*4882a593Smuzhiyun cflag |= DZ_CS8;
584*4882a593Smuzhiyun }
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun if (termios->c_cflag & CSTOPB)
587*4882a593Smuzhiyun cflag |= DZ_CSTOPB;
588*4882a593Smuzhiyun if (termios->c_cflag & PARENB)
589*4882a593Smuzhiyun cflag |= DZ_PARENB;
590*4882a593Smuzhiyun if (termios->c_cflag & PARODD)
591*4882a593Smuzhiyun cflag |= DZ_PARODD;
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun baud = uart_get_baud_rate(uport, termios, old_termios, 50, 9600);
594*4882a593Smuzhiyun bflag = dz_encode_baud_rate(baud);
595*4882a593Smuzhiyun if (bflag < 0) { /* Try to keep unchanged. */
596*4882a593Smuzhiyun baud = uart_get_baud_rate(uport, old_termios, NULL, 50, 9600);
597*4882a593Smuzhiyun bflag = dz_encode_baud_rate(baud);
598*4882a593Smuzhiyun if (bflag < 0) { /* Resort to 9600. */
599*4882a593Smuzhiyun baud = 9600;
600*4882a593Smuzhiyun bflag = DZ_B9600;
601*4882a593Smuzhiyun }
602*4882a593Smuzhiyun tty_termios_encode_baud_rate(termios, baud, baud);
603*4882a593Smuzhiyun }
604*4882a593Smuzhiyun cflag |= bflag;
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun if (termios->c_cflag & CREAD)
607*4882a593Smuzhiyun cflag |= DZ_RXENAB;
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun spin_lock_irqsave(&dport->port.lock, flags);
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun uart_update_timeout(uport, termios->c_cflag, baud);
612*4882a593Smuzhiyun
613*4882a593Smuzhiyun dz_out(dport, DZ_LPR, cflag);
614*4882a593Smuzhiyun dport->cflag = cflag;
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun /* setup accept flag */
617*4882a593Smuzhiyun dport->port.read_status_mask = DZ_OERR;
618*4882a593Smuzhiyun if (termios->c_iflag & INPCK)
619*4882a593Smuzhiyun dport->port.read_status_mask |= DZ_FERR | DZ_PERR;
620*4882a593Smuzhiyun if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
621*4882a593Smuzhiyun dport->port.read_status_mask |= DZ_BREAK;
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun /* characters to ignore */
624*4882a593Smuzhiyun uport->ignore_status_mask = 0;
625*4882a593Smuzhiyun if ((termios->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
626*4882a593Smuzhiyun dport->port.ignore_status_mask |= DZ_OERR;
627*4882a593Smuzhiyun if (termios->c_iflag & IGNPAR)
628*4882a593Smuzhiyun dport->port.ignore_status_mask |= DZ_FERR | DZ_PERR;
629*4882a593Smuzhiyun if (termios->c_iflag & IGNBRK)
630*4882a593Smuzhiyun dport->port.ignore_status_mask |= DZ_BREAK;
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun spin_unlock_irqrestore(&dport->port.lock, flags);
633*4882a593Smuzhiyun }
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun /*
636*4882a593Smuzhiyun * Hack alert!
637*4882a593Smuzhiyun * Required solely so that the initial PROM-based console
638*4882a593Smuzhiyun * works undisturbed in parallel with this one.
639*4882a593Smuzhiyun */
dz_pm(struct uart_port * uport,unsigned int state,unsigned int oldstate)640*4882a593Smuzhiyun static void dz_pm(struct uart_port *uport, unsigned int state,
641*4882a593Smuzhiyun unsigned int oldstate)
642*4882a593Smuzhiyun {
643*4882a593Smuzhiyun struct dz_port *dport = to_dport(uport);
644*4882a593Smuzhiyun unsigned long flags;
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun spin_lock_irqsave(&dport->port.lock, flags);
647*4882a593Smuzhiyun if (state < 3)
648*4882a593Smuzhiyun dz_start_tx(&dport->port);
649*4882a593Smuzhiyun else
650*4882a593Smuzhiyun dz_stop_tx(&dport->port);
651*4882a593Smuzhiyun spin_unlock_irqrestore(&dport->port.lock, flags);
652*4882a593Smuzhiyun }
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun
dz_type(struct uart_port * uport)655*4882a593Smuzhiyun static const char *dz_type(struct uart_port *uport)
656*4882a593Smuzhiyun {
657*4882a593Smuzhiyun return "DZ";
658*4882a593Smuzhiyun }
659*4882a593Smuzhiyun
dz_release_port(struct uart_port * uport)660*4882a593Smuzhiyun static void dz_release_port(struct uart_port *uport)
661*4882a593Smuzhiyun {
662*4882a593Smuzhiyun struct dz_mux *mux = to_dport(uport)->mux;
663*4882a593Smuzhiyun int map_guard;
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun iounmap(uport->membase);
666*4882a593Smuzhiyun uport->membase = NULL;
667*4882a593Smuzhiyun
668*4882a593Smuzhiyun map_guard = atomic_add_return(-1, &mux->map_guard);
669*4882a593Smuzhiyun if (!map_guard)
670*4882a593Smuzhiyun release_mem_region(uport->mapbase, dec_kn_slot_size);
671*4882a593Smuzhiyun }
672*4882a593Smuzhiyun
dz_map_port(struct uart_port * uport)673*4882a593Smuzhiyun static int dz_map_port(struct uart_port *uport)
674*4882a593Smuzhiyun {
675*4882a593Smuzhiyun if (!uport->membase)
676*4882a593Smuzhiyun uport->membase = ioremap(uport->mapbase,
677*4882a593Smuzhiyun dec_kn_slot_size);
678*4882a593Smuzhiyun if (!uport->membase) {
679*4882a593Smuzhiyun printk(KERN_ERR "dz: Cannot map MMIO\n");
680*4882a593Smuzhiyun return -ENOMEM;
681*4882a593Smuzhiyun }
682*4882a593Smuzhiyun return 0;
683*4882a593Smuzhiyun }
684*4882a593Smuzhiyun
dz_request_port(struct uart_port * uport)685*4882a593Smuzhiyun static int dz_request_port(struct uart_port *uport)
686*4882a593Smuzhiyun {
687*4882a593Smuzhiyun struct dz_mux *mux = to_dport(uport)->mux;
688*4882a593Smuzhiyun int map_guard;
689*4882a593Smuzhiyun int ret;
690*4882a593Smuzhiyun
691*4882a593Smuzhiyun map_guard = atomic_add_return(1, &mux->map_guard);
692*4882a593Smuzhiyun if (map_guard == 1) {
693*4882a593Smuzhiyun if (!request_mem_region(uport->mapbase, dec_kn_slot_size,
694*4882a593Smuzhiyun "dz")) {
695*4882a593Smuzhiyun atomic_add(-1, &mux->map_guard);
696*4882a593Smuzhiyun printk(KERN_ERR
697*4882a593Smuzhiyun "dz: Unable to reserve MMIO resource\n");
698*4882a593Smuzhiyun return -EBUSY;
699*4882a593Smuzhiyun }
700*4882a593Smuzhiyun }
701*4882a593Smuzhiyun ret = dz_map_port(uport);
702*4882a593Smuzhiyun if (ret) {
703*4882a593Smuzhiyun map_guard = atomic_add_return(-1, &mux->map_guard);
704*4882a593Smuzhiyun if (!map_guard)
705*4882a593Smuzhiyun release_mem_region(uport->mapbase, dec_kn_slot_size);
706*4882a593Smuzhiyun return ret;
707*4882a593Smuzhiyun }
708*4882a593Smuzhiyun return 0;
709*4882a593Smuzhiyun }
710*4882a593Smuzhiyun
dz_config_port(struct uart_port * uport,int flags)711*4882a593Smuzhiyun static void dz_config_port(struct uart_port *uport, int flags)
712*4882a593Smuzhiyun {
713*4882a593Smuzhiyun struct dz_port *dport = to_dport(uport);
714*4882a593Smuzhiyun
715*4882a593Smuzhiyun if (flags & UART_CONFIG_TYPE) {
716*4882a593Smuzhiyun if (dz_request_port(uport))
717*4882a593Smuzhiyun return;
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun uport->type = PORT_DZ;
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun dz_reset(dport);
722*4882a593Smuzhiyun }
723*4882a593Smuzhiyun }
724*4882a593Smuzhiyun
725*4882a593Smuzhiyun /*
726*4882a593Smuzhiyun * Verify the new serial_struct (for TIOCSSERIAL).
727*4882a593Smuzhiyun */
dz_verify_port(struct uart_port * uport,struct serial_struct * ser)728*4882a593Smuzhiyun static int dz_verify_port(struct uart_port *uport, struct serial_struct *ser)
729*4882a593Smuzhiyun {
730*4882a593Smuzhiyun int ret = 0;
731*4882a593Smuzhiyun
732*4882a593Smuzhiyun if (ser->type != PORT_UNKNOWN && ser->type != PORT_DZ)
733*4882a593Smuzhiyun ret = -EINVAL;
734*4882a593Smuzhiyun if (ser->irq != uport->irq)
735*4882a593Smuzhiyun ret = -EINVAL;
736*4882a593Smuzhiyun return ret;
737*4882a593Smuzhiyun }
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun static const struct uart_ops dz_ops = {
740*4882a593Smuzhiyun .tx_empty = dz_tx_empty,
741*4882a593Smuzhiyun .get_mctrl = dz_get_mctrl,
742*4882a593Smuzhiyun .set_mctrl = dz_set_mctrl,
743*4882a593Smuzhiyun .stop_tx = dz_stop_tx,
744*4882a593Smuzhiyun .start_tx = dz_start_tx,
745*4882a593Smuzhiyun .stop_rx = dz_stop_rx,
746*4882a593Smuzhiyun .break_ctl = dz_break_ctl,
747*4882a593Smuzhiyun .startup = dz_startup,
748*4882a593Smuzhiyun .shutdown = dz_shutdown,
749*4882a593Smuzhiyun .set_termios = dz_set_termios,
750*4882a593Smuzhiyun .pm = dz_pm,
751*4882a593Smuzhiyun .type = dz_type,
752*4882a593Smuzhiyun .release_port = dz_release_port,
753*4882a593Smuzhiyun .request_port = dz_request_port,
754*4882a593Smuzhiyun .config_port = dz_config_port,
755*4882a593Smuzhiyun .verify_port = dz_verify_port,
756*4882a593Smuzhiyun };
757*4882a593Smuzhiyun
dz_init_ports(void)758*4882a593Smuzhiyun static void __init dz_init_ports(void)
759*4882a593Smuzhiyun {
760*4882a593Smuzhiyun static int first = 1;
761*4882a593Smuzhiyun unsigned long base;
762*4882a593Smuzhiyun int line;
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun if (!first)
765*4882a593Smuzhiyun return;
766*4882a593Smuzhiyun first = 0;
767*4882a593Smuzhiyun
768*4882a593Smuzhiyun if (mips_machtype == MACH_DS23100 || mips_machtype == MACH_DS5100)
769*4882a593Smuzhiyun base = dec_kn_slot_base + KN01_DZ11;
770*4882a593Smuzhiyun else
771*4882a593Smuzhiyun base = dec_kn_slot_base + KN02_DZ11;
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun for (line = 0; line < DZ_NB_PORT; line++) {
774*4882a593Smuzhiyun struct dz_port *dport = &dz_mux.dport[line];
775*4882a593Smuzhiyun struct uart_port *uport = &dport->port;
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun dport->mux = &dz_mux;
778*4882a593Smuzhiyun
779*4882a593Smuzhiyun uport->irq = dec_interrupt[DEC_IRQ_DZ11];
780*4882a593Smuzhiyun uport->fifosize = 1;
781*4882a593Smuzhiyun uport->iotype = UPIO_MEM;
782*4882a593Smuzhiyun uport->flags = UPF_BOOT_AUTOCONF;
783*4882a593Smuzhiyun uport->ops = &dz_ops;
784*4882a593Smuzhiyun uport->line = line;
785*4882a593Smuzhiyun uport->mapbase = base;
786*4882a593Smuzhiyun uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_DZ_CONSOLE);
787*4882a593Smuzhiyun }
788*4882a593Smuzhiyun }
789*4882a593Smuzhiyun
790*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_DZ_CONSOLE
791*4882a593Smuzhiyun /*
792*4882a593Smuzhiyun * -------------------------------------------------------------------
793*4882a593Smuzhiyun * dz_console_putchar() -- transmit a character
794*4882a593Smuzhiyun *
795*4882a593Smuzhiyun * Polled transmission. This is tricky. We need to mask transmit
796*4882a593Smuzhiyun * interrupts so that they do not interfere, enable the transmitter
797*4882a593Smuzhiyun * for the line requested and then wait till the transmit scanner
798*4882a593Smuzhiyun * requests data for this line. But it may request data for another
799*4882a593Smuzhiyun * line first, in which case we have to disable its transmitter and
800*4882a593Smuzhiyun * repeat waiting till our line pops up. Only then the character may
801*4882a593Smuzhiyun * be transmitted. Finally, the state of the transmitter mask is
802*4882a593Smuzhiyun * restored. Welcome to the world of PDP-11!
803*4882a593Smuzhiyun * -------------------------------------------------------------------
804*4882a593Smuzhiyun */
dz_console_putchar(struct uart_port * uport,int ch)805*4882a593Smuzhiyun static void dz_console_putchar(struct uart_port *uport, int ch)
806*4882a593Smuzhiyun {
807*4882a593Smuzhiyun struct dz_port *dport = to_dport(uport);
808*4882a593Smuzhiyun unsigned long flags;
809*4882a593Smuzhiyun unsigned short csr, tcr, trdy, mask;
810*4882a593Smuzhiyun int loops = 10000;
811*4882a593Smuzhiyun
812*4882a593Smuzhiyun spin_lock_irqsave(&dport->port.lock, flags);
813*4882a593Smuzhiyun csr = dz_in(dport, DZ_CSR);
814*4882a593Smuzhiyun dz_out(dport, DZ_CSR, csr & ~DZ_TIE);
815*4882a593Smuzhiyun tcr = dz_in(dport, DZ_TCR);
816*4882a593Smuzhiyun tcr |= 1 << dport->port.line;
817*4882a593Smuzhiyun mask = tcr;
818*4882a593Smuzhiyun dz_out(dport, DZ_TCR, mask);
819*4882a593Smuzhiyun iob();
820*4882a593Smuzhiyun spin_unlock_irqrestore(&dport->port.lock, flags);
821*4882a593Smuzhiyun
822*4882a593Smuzhiyun do {
823*4882a593Smuzhiyun trdy = dz_in(dport, DZ_CSR);
824*4882a593Smuzhiyun if (!(trdy & DZ_TRDY))
825*4882a593Smuzhiyun continue;
826*4882a593Smuzhiyun trdy = (trdy & DZ_TLINE) >> 8;
827*4882a593Smuzhiyun if (trdy == dport->port.line)
828*4882a593Smuzhiyun break;
829*4882a593Smuzhiyun mask &= ~(1 << trdy);
830*4882a593Smuzhiyun dz_out(dport, DZ_TCR, mask);
831*4882a593Smuzhiyun iob();
832*4882a593Smuzhiyun udelay(2);
833*4882a593Smuzhiyun } while (--loops);
834*4882a593Smuzhiyun
835*4882a593Smuzhiyun if (loops) /* Cannot send otherwise. */
836*4882a593Smuzhiyun dz_out(dport, DZ_TDR, ch);
837*4882a593Smuzhiyun
838*4882a593Smuzhiyun dz_out(dport, DZ_TCR, tcr);
839*4882a593Smuzhiyun dz_out(dport, DZ_CSR, csr);
840*4882a593Smuzhiyun }
841*4882a593Smuzhiyun
842*4882a593Smuzhiyun /*
843*4882a593Smuzhiyun * -------------------------------------------------------------------
844*4882a593Smuzhiyun * dz_console_print ()
845*4882a593Smuzhiyun *
846*4882a593Smuzhiyun * dz_console_print is registered for printk.
847*4882a593Smuzhiyun * The console must be locked when we get here.
848*4882a593Smuzhiyun * -------------------------------------------------------------------
849*4882a593Smuzhiyun */
dz_console_print(struct console * co,const char * str,unsigned int count)850*4882a593Smuzhiyun static void dz_console_print(struct console *co,
851*4882a593Smuzhiyun const char *str,
852*4882a593Smuzhiyun unsigned int count)
853*4882a593Smuzhiyun {
854*4882a593Smuzhiyun struct dz_port *dport = &dz_mux.dport[co->index];
855*4882a593Smuzhiyun #ifdef DEBUG_DZ
856*4882a593Smuzhiyun prom_printf((char *) str);
857*4882a593Smuzhiyun #endif
858*4882a593Smuzhiyun uart_console_write(&dport->port, str, count, dz_console_putchar);
859*4882a593Smuzhiyun }
860*4882a593Smuzhiyun
dz_console_setup(struct console * co,char * options)861*4882a593Smuzhiyun static int __init dz_console_setup(struct console *co, char *options)
862*4882a593Smuzhiyun {
863*4882a593Smuzhiyun struct dz_port *dport = &dz_mux.dport[co->index];
864*4882a593Smuzhiyun struct uart_port *uport = &dport->port;
865*4882a593Smuzhiyun int baud = 9600;
866*4882a593Smuzhiyun int bits = 8;
867*4882a593Smuzhiyun int parity = 'n';
868*4882a593Smuzhiyun int flow = 'n';
869*4882a593Smuzhiyun int ret;
870*4882a593Smuzhiyun
871*4882a593Smuzhiyun ret = dz_map_port(uport);
872*4882a593Smuzhiyun if (ret)
873*4882a593Smuzhiyun return ret;
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun spin_lock_init(&dport->port.lock); /* For dz_pm(). */
876*4882a593Smuzhiyun
877*4882a593Smuzhiyun dz_reset(dport);
878*4882a593Smuzhiyun dz_pm(uport, 0, -1);
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun if (options)
881*4882a593Smuzhiyun uart_parse_options(options, &baud, &parity, &bits, &flow);
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun return uart_set_options(&dport->port, co, baud, parity, bits, flow);
884*4882a593Smuzhiyun }
885*4882a593Smuzhiyun
886*4882a593Smuzhiyun static struct uart_driver dz_reg;
887*4882a593Smuzhiyun static struct console dz_console = {
888*4882a593Smuzhiyun .name = "ttyS",
889*4882a593Smuzhiyun .write = dz_console_print,
890*4882a593Smuzhiyun .device = uart_console_device,
891*4882a593Smuzhiyun .setup = dz_console_setup,
892*4882a593Smuzhiyun .flags = CON_PRINTBUFFER,
893*4882a593Smuzhiyun .index = -1,
894*4882a593Smuzhiyun .data = &dz_reg,
895*4882a593Smuzhiyun };
896*4882a593Smuzhiyun
dz_serial_console_init(void)897*4882a593Smuzhiyun static int __init dz_serial_console_init(void)
898*4882a593Smuzhiyun {
899*4882a593Smuzhiyun if (!IOASIC) {
900*4882a593Smuzhiyun dz_init_ports();
901*4882a593Smuzhiyun register_console(&dz_console);
902*4882a593Smuzhiyun return 0;
903*4882a593Smuzhiyun } else
904*4882a593Smuzhiyun return -ENXIO;
905*4882a593Smuzhiyun }
906*4882a593Smuzhiyun
907*4882a593Smuzhiyun console_initcall(dz_serial_console_init);
908*4882a593Smuzhiyun
909*4882a593Smuzhiyun #define SERIAL_DZ_CONSOLE &dz_console
910*4882a593Smuzhiyun #else
911*4882a593Smuzhiyun #define SERIAL_DZ_CONSOLE NULL
912*4882a593Smuzhiyun #endif /* CONFIG_SERIAL_DZ_CONSOLE */
913*4882a593Smuzhiyun
914*4882a593Smuzhiyun static struct uart_driver dz_reg = {
915*4882a593Smuzhiyun .owner = THIS_MODULE,
916*4882a593Smuzhiyun .driver_name = "serial",
917*4882a593Smuzhiyun .dev_name = "ttyS",
918*4882a593Smuzhiyun .major = TTY_MAJOR,
919*4882a593Smuzhiyun .minor = 64,
920*4882a593Smuzhiyun .nr = DZ_NB_PORT,
921*4882a593Smuzhiyun .cons = SERIAL_DZ_CONSOLE,
922*4882a593Smuzhiyun };
923*4882a593Smuzhiyun
dz_init(void)924*4882a593Smuzhiyun static int __init dz_init(void)
925*4882a593Smuzhiyun {
926*4882a593Smuzhiyun int ret, i;
927*4882a593Smuzhiyun
928*4882a593Smuzhiyun if (IOASIC)
929*4882a593Smuzhiyun return -ENXIO;
930*4882a593Smuzhiyun
931*4882a593Smuzhiyun printk("%s%s\n", dz_name, dz_version);
932*4882a593Smuzhiyun
933*4882a593Smuzhiyun dz_init_ports();
934*4882a593Smuzhiyun
935*4882a593Smuzhiyun ret = uart_register_driver(&dz_reg);
936*4882a593Smuzhiyun if (ret)
937*4882a593Smuzhiyun return ret;
938*4882a593Smuzhiyun
939*4882a593Smuzhiyun for (i = 0; i < DZ_NB_PORT; i++)
940*4882a593Smuzhiyun uart_add_one_port(&dz_reg, &dz_mux.dport[i].port);
941*4882a593Smuzhiyun
942*4882a593Smuzhiyun return 0;
943*4882a593Smuzhiyun }
944*4882a593Smuzhiyun
945*4882a593Smuzhiyun module_init(dz_init);
946