1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __GRLIB_APBUART_H__ 3*4882a593Smuzhiyun #define __GRLIB_APBUART_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <asm/io.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define UART_NR 8 8*4882a593Smuzhiyun static int grlib_apbuart_port_nr; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun struct grlib_apbuart_regs_map { 11*4882a593Smuzhiyun u32 data; 12*4882a593Smuzhiyun u32 status; 13*4882a593Smuzhiyun u32 ctrl; 14*4882a593Smuzhiyun u32 scaler; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun struct amba_prom_registers { 18*4882a593Smuzhiyun unsigned int phys_addr; 19*4882a593Smuzhiyun unsigned int reg_size; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* 23*4882a593Smuzhiyun * The following defines the bits in the APBUART Status Registers. 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun #define UART_STATUS_DR 0x00000001 /* Data Ready */ 26*4882a593Smuzhiyun #define UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */ 27*4882a593Smuzhiyun #define UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */ 28*4882a593Smuzhiyun #define UART_STATUS_BR 0x00000008 /* Break Error */ 29*4882a593Smuzhiyun #define UART_STATUS_OE 0x00000010 /* RX Overrun Error */ 30*4882a593Smuzhiyun #define UART_STATUS_PE 0x00000020 /* RX Parity Error */ 31*4882a593Smuzhiyun #define UART_STATUS_FE 0x00000040 /* RX Framing Error */ 32*4882a593Smuzhiyun #define UART_STATUS_ERR 0x00000078 /* Error Mask */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* 35*4882a593Smuzhiyun * The following defines the bits in the APBUART Ctrl Registers. 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun #define UART_CTRL_RE 0x00000001 /* Receiver enable */ 38*4882a593Smuzhiyun #define UART_CTRL_TE 0x00000002 /* Transmitter enable */ 39*4882a593Smuzhiyun #define UART_CTRL_RI 0x00000004 /* Receiver interrupt enable */ 40*4882a593Smuzhiyun #define UART_CTRL_TI 0x00000008 /* Transmitter irq */ 41*4882a593Smuzhiyun #define UART_CTRL_PS 0x00000010 /* Parity select */ 42*4882a593Smuzhiyun #define UART_CTRL_PE 0x00000020 /* Parity enable */ 43*4882a593Smuzhiyun #define UART_CTRL_FL 0x00000040 /* Flow control enable */ 44*4882a593Smuzhiyun #define UART_CTRL_LB 0x00000080 /* Loopback enable */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define APBBASE(port) ((struct grlib_apbuart_regs_map *)((port)->membase)) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define APBBASE_DATA_P(port) (&(APBBASE(port)->data)) 49*4882a593Smuzhiyun #define APBBASE_STATUS_P(port) (&(APBBASE(port)->status)) 50*4882a593Smuzhiyun #define APBBASE_CTRL_P(port) (&(APBBASE(port)->ctrl)) 51*4882a593Smuzhiyun #define APBBASE_SCALAR_P(port) (&(APBBASE(port)->scaler)) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define UART_GET_CHAR(port) (__raw_readl(APBBASE_DATA_P(port))) 54*4882a593Smuzhiyun #define UART_PUT_CHAR(port, v) (__raw_writel(v, APBBASE_DATA_P(port))) 55*4882a593Smuzhiyun #define UART_GET_STATUS(port) (__raw_readl(APBBASE_STATUS_P(port))) 56*4882a593Smuzhiyun #define UART_PUT_STATUS(port, v)(__raw_writel(v, APBBASE_STATUS_P(port))) 57*4882a593Smuzhiyun #define UART_GET_CTRL(port) (__raw_readl(APBBASE_CTRL_P(port))) 58*4882a593Smuzhiyun #define UART_PUT_CTRL(port, v) (__raw_writel(v, APBBASE_CTRL_P(port))) 59*4882a593Smuzhiyun #define UART_GET_SCAL(port) (__raw_readl(APBBASE_SCALAR_P(port))) 60*4882a593Smuzhiyun #define UART_PUT_SCAL(port, v) (__raw_writel(v, APBBASE_SCALAR_P(port))) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define UART_RX_DATA(s) (((s) & UART_STATUS_DR) != 0) 63*4882a593Smuzhiyun #define UART_TX_READY(s) (((s) & UART_STATUS_THE) != 0) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #endif /* __GRLIB_APBUART_H__ */ 66