xref: /OK3568_Linux_fs/kernel/drivers/tty/serial/altera_uart.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * altera_uart.c -- Altera UART driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Based on mcf.c -- Freescale ColdFire UART driver
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * (C) Copyright 2003-2007, Greg Ungerer <gerg@snapgear.com>
8*4882a593Smuzhiyun  * (C) Copyright 2008, Thomas Chou <thomas@wytron.com.tw>
9*4882a593Smuzhiyun  * (C) Copyright 2010, Tobias Klauser <tklauser@distanz.ch>
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/timer.h>
15*4882a593Smuzhiyun #include <linux/interrupt.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/console.h>
18*4882a593Smuzhiyun #include <linux/tty.h>
19*4882a593Smuzhiyun #include <linux/tty_flip.h>
20*4882a593Smuzhiyun #include <linux/serial.h>
21*4882a593Smuzhiyun #include <linux/serial_core.h>
22*4882a593Smuzhiyun #include <linux/platform_device.h>
23*4882a593Smuzhiyun #include <linux/of.h>
24*4882a593Smuzhiyun #include <linux/io.h>
25*4882a593Smuzhiyun #include <linux/altera_uart.h>
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define DRV_NAME "altera_uart"
28*4882a593Smuzhiyun #define SERIAL_ALTERA_MAJOR 204
29*4882a593Smuzhiyun #define SERIAL_ALTERA_MINOR 213
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun /*
32*4882a593Smuzhiyun  * Altera UART register definitions according to the Nios UART datasheet:
33*4882a593Smuzhiyun  * http://www.altera.com/literature/ds/ds_nios_uart.pdf
34*4882a593Smuzhiyun  */
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #define ALTERA_UART_SIZE		32
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #define ALTERA_UART_RXDATA_REG		0
39*4882a593Smuzhiyun #define ALTERA_UART_TXDATA_REG		4
40*4882a593Smuzhiyun #define ALTERA_UART_STATUS_REG		8
41*4882a593Smuzhiyun #define ALTERA_UART_CONTROL_REG		12
42*4882a593Smuzhiyun #define ALTERA_UART_DIVISOR_REG		16
43*4882a593Smuzhiyun #define ALTERA_UART_EOP_REG		20
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun #define ALTERA_UART_STATUS_PE_MSK	0x0001	/* parity error */
46*4882a593Smuzhiyun #define ALTERA_UART_STATUS_FE_MSK	0x0002	/* framing error */
47*4882a593Smuzhiyun #define ALTERA_UART_STATUS_BRK_MSK	0x0004	/* break */
48*4882a593Smuzhiyun #define ALTERA_UART_STATUS_ROE_MSK	0x0008	/* RX overrun error */
49*4882a593Smuzhiyun #define ALTERA_UART_STATUS_TOE_MSK	0x0010	/* TX overrun error */
50*4882a593Smuzhiyun #define ALTERA_UART_STATUS_TMT_MSK	0x0020	/* TX shift register state */
51*4882a593Smuzhiyun #define ALTERA_UART_STATUS_TRDY_MSK	0x0040	/* TX ready */
52*4882a593Smuzhiyun #define ALTERA_UART_STATUS_RRDY_MSK	0x0080	/* RX ready */
53*4882a593Smuzhiyun #define ALTERA_UART_STATUS_E_MSK	0x0100	/* exception condition */
54*4882a593Smuzhiyun #define ALTERA_UART_STATUS_DCTS_MSK	0x0400	/* CTS logic-level change */
55*4882a593Smuzhiyun #define ALTERA_UART_STATUS_CTS_MSK	0x0800	/* CTS logic state */
56*4882a593Smuzhiyun #define ALTERA_UART_STATUS_EOP_MSK	0x1000	/* EOP written/read */
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 						/* Enable interrupt on... */
59*4882a593Smuzhiyun #define ALTERA_UART_CONTROL_PE_MSK	0x0001	/* ...parity error */
60*4882a593Smuzhiyun #define ALTERA_UART_CONTROL_FE_MSK	0x0002	/* ...framing error */
61*4882a593Smuzhiyun #define ALTERA_UART_CONTROL_BRK_MSK	0x0004	/* ...break */
62*4882a593Smuzhiyun #define ALTERA_UART_CONTROL_ROE_MSK	0x0008	/* ...RX overrun */
63*4882a593Smuzhiyun #define ALTERA_UART_CONTROL_TOE_MSK	0x0010	/* ...TX overrun */
64*4882a593Smuzhiyun #define ALTERA_UART_CONTROL_TMT_MSK	0x0020	/* ...TX shift register empty */
65*4882a593Smuzhiyun #define ALTERA_UART_CONTROL_TRDY_MSK	0x0040	/* ...TX ready */
66*4882a593Smuzhiyun #define ALTERA_UART_CONTROL_RRDY_MSK	0x0080	/* ...RX ready */
67*4882a593Smuzhiyun #define ALTERA_UART_CONTROL_E_MSK	0x0100	/* ...exception*/
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun #define ALTERA_UART_CONTROL_TRBK_MSK	0x0200	/* TX break */
70*4882a593Smuzhiyun #define ALTERA_UART_CONTROL_DCTS_MSK	0x0400	/* Interrupt on CTS change */
71*4882a593Smuzhiyun #define ALTERA_UART_CONTROL_RTS_MSK	0x0800	/* RTS signal */
72*4882a593Smuzhiyun #define ALTERA_UART_CONTROL_EOP_MSK	0x1000	/* Interrupt on EOP */
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun /*
75*4882a593Smuzhiyun  * Local per-uart structure.
76*4882a593Smuzhiyun  */
77*4882a593Smuzhiyun struct altera_uart {
78*4882a593Smuzhiyun 	struct uart_port port;
79*4882a593Smuzhiyun 	struct timer_list tmr;
80*4882a593Smuzhiyun 	unsigned int sigs;	/* Local copy of line sigs */
81*4882a593Smuzhiyun 	unsigned short imr;	/* Local IMR mirror */
82*4882a593Smuzhiyun };
83*4882a593Smuzhiyun 
altera_uart_readl(struct uart_port * port,int reg)84*4882a593Smuzhiyun static u32 altera_uart_readl(struct uart_port *port, int reg)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun 	return readl(port->membase + (reg << port->regshift));
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun 
altera_uart_writel(struct uart_port * port,u32 dat,int reg)89*4882a593Smuzhiyun static void altera_uart_writel(struct uart_port *port, u32 dat, int reg)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun 	writel(dat, port->membase + (reg << port->regshift));
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun 
altera_uart_tx_empty(struct uart_port * port)94*4882a593Smuzhiyun static unsigned int altera_uart_tx_empty(struct uart_port *port)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun 	return (altera_uart_readl(port, ALTERA_UART_STATUS_REG) &
97*4882a593Smuzhiyun 		ALTERA_UART_STATUS_TMT_MSK) ? TIOCSER_TEMT : 0;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun 
altera_uart_get_mctrl(struct uart_port * port)100*4882a593Smuzhiyun static unsigned int altera_uart_get_mctrl(struct uart_port *port)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun 	struct altera_uart *pp = container_of(port, struct altera_uart, port);
103*4882a593Smuzhiyun 	unsigned int sigs;
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	sigs = (altera_uart_readl(port, ALTERA_UART_STATUS_REG) &
106*4882a593Smuzhiyun 	     ALTERA_UART_STATUS_CTS_MSK) ? TIOCM_CTS : 0;
107*4882a593Smuzhiyun 	sigs |= (pp->sigs & TIOCM_RTS);
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	return sigs;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun 
altera_uart_update_ctrl_reg(struct altera_uart * pp)112*4882a593Smuzhiyun static void altera_uart_update_ctrl_reg(struct altera_uart *pp)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun 	unsigned short imr = pp->imr;
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	/*
117*4882a593Smuzhiyun 	 * If the device doesn't have an irq, ensure that the irq bits are
118*4882a593Smuzhiyun 	 * masked out to keep the irq line inactive.
119*4882a593Smuzhiyun 	 */
120*4882a593Smuzhiyun 	if (!pp->port.irq)
121*4882a593Smuzhiyun 		imr &= ALTERA_UART_CONTROL_TRBK_MSK | ALTERA_UART_CONTROL_RTS_MSK;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	altera_uart_writel(&pp->port, imr, ALTERA_UART_CONTROL_REG);
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun 
altera_uart_set_mctrl(struct uart_port * port,unsigned int sigs)126*4882a593Smuzhiyun static void altera_uart_set_mctrl(struct uart_port *port, unsigned int sigs)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun 	struct altera_uart *pp = container_of(port, struct altera_uart, port);
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	pp->sigs = sigs;
131*4882a593Smuzhiyun 	if (sigs & TIOCM_RTS)
132*4882a593Smuzhiyun 		pp->imr |= ALTERA_UART_CONTROL_RTS_MSK;
133*4882a593Smuzhiyun 	else
134*4882a593Smuzhiyun 		pp->imr &= ~ALTERA_UART_CONTROL_RTS_MSK;
135*4882a593Smuzhiyun 	altera_uart_update_ctrl_reg(pp);
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun 
altera_uart_start_tx(struct uart_port * port)138*4882a593Smuzhiyun static void altera_uart_start_tx(struct uart_port *port)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun 	struct altera_uart *pp = container_of(port, struct altera_uart, port);
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	pp->imr |= ALTERA_UART_CONTROL_TRDY_MSK;
143*4882a593Smuzhiyun 	altera_uart_update_ctrl_reg(pp);
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun 
altera_uart_stop_tx(struct uart_port * port)146*4882a593Smuzhiyun static void altera_uart_stop_tx(struct uart_port *port)
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun 	struct altera_uart *pp = container_of(port, struct altera_uart, port);
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	pp->imr &= ~ALTERA_UART_CONTROL_TRDY_MSK;
151*4882a593Smuzhiyun 	altera_uart_update_ctrl_reg(pp);
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun 
altera_uart_stop_rx(struct uart_port * port)154*4882a593Smuzhiyun static void altera_uart_stop_rx(struct uart_port *port)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun 	struct altera_uart *pp = container_of(port, struct altera_uart, port);
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	pp->imr &= ~ALTERA_UART_CONTROL_RRDY_MSK;
159*4882a593Smuzhiyun 	altera_uart_update_ctrl_reg(pp);
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun 
altera_uart_break_ctl(struct uart_port * port,int break_state)162*4882a593Smuzhiyun static void altera_uart_break_ctl(struct uart_port *port, int break_state)
163*4882a593Smuzhiyun {
164*4882a593Smuzhiyun 	struct altera_uart *pp = container_of(port, struct altera_uart, port);
165*4882a593Smuzhiyun 	unsigned long flags;
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	spin_lock_irqsave(&port->lock, flags);
168*4882a593Smuzhiyun 	if (break_state == -1)
169*4882a593Smuzhiyun 		pp->imr |= ALTERA_UART_CONTROL_TRBK_MSK;
170*4882a593Smuzhiyun 	else
171*4882a593Smuzhiyun 		pp->imr &= ~ALTERA_UART_CONTROL_TRBK_MSK;
172*4882a593Smuzhiyun 	altera_uart_update_ctrl_reg(pp);
173*4882a593Smuzhiyun 	spin_unlock_irqrestore(&port->lock, flags);
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun 
altera_uart_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)176*4882a593Smuzhiyun static void altera_uart_set_termios(struct uart_port *port,
177*4882a593Smuzhiyun 				    struct ktermios *termios,
178*4882a593Smuzhiyun 				    struct ktermios *old)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun 	unsigned long flags;
181*4882a593Smuzhiyun 	unsigned int baud, baudclk;
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
184*4882a593Smuzhiyun 	baudclk = port->uartclk / baud;
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	if (old)
187*4882a593Smuzhiyun 		tty_termios_copy_hw(termios, old);
188*4882a593Smuzhiyun 	tty_termios_encode_baud_rate(termios, baud, baud);
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 	spin_lock_irqsave(&port->lock, flags);
191*4882a593Smuzhiyun 	uart_update_timeout(port, termios->c_cflag, baud);
192*4882a593Smuzhiyun 	altera_uart_writel(port, baudclk, ALTERA_UART_DIVISOR_REG);
193*4882a593Smuzhiyun 	spin_unlock_irqrestore(&port->lock, flags);
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	/*
196*4882a593Smuzhiyun 	 * FIXME: port->read_status_mask and port->ignore_status_mask
197*4882a593Smuzhiyun 	 * need to be initialized based on termios settings for
198*4882a593Smuzhiyun 	 * INPCK, IGNBRK, IGNPAR, PARMRK, BRKINT
199*4882a593Smuzhiyun 	 */
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun 
altera_uart_rx_chars(struct altera_uart * pp)202*4882a593Smuzhiyun static void altera_uart_rx_chars(struct altera_uart *pp)
203*4882a593Smuzhiyun {
204*4882a593Smuzhiyun 	struct uart_port *port = &pp->port;
205*4882a593Smuzhiyun 	unsigned char ch, flag;
206*4882a593Smuzhiyun 	unsigned short status;
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	while ((status = altera_uart_readl(port, ALTERA_UART_STATUS_REG)) &
209*4882a593Smuzhiyun 	       ALTERA_UART_STATUS_RRDY_MSK) {
210*4882a593Smuzhiyun 		ch = altera_uart_readl(port, ALTERA_UART_RXDATA_REG);
211*4882a593Smuzhiyun 		flag = TTY_NORMAL;
212*4882a593Smuzhiyun 		port->icount.rx++;
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 		if (status & ALTERA_UART_STATUS_E_MSK) {
215*4882a593Smuzhiyun 			altera_uart_writel(port, status,
216*4882a593Smuzhiyun 					   ALTERA_UART_STATUS_REG);
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 			if (status & ALTERA_UART_STATUS_BRK_MSK) {
219*4882a593Smuzhiyun 				port->icount.brk++;
220*4882a593Smuzhiyun 				if (uart_handle_break(port))
221*4882a593Smuzhiyun 					continue;
222*4882a593Smuzhiyun 			} else if (status & ALTERA_UART_STATUS_PE_MSK) {
223*4882a593Smuzhiyun 				port->icount.parity++;
224*4882a593Smuzhiyun 			} else if (status & ALTERA_UART_STATUS_ROE_MSK) {
225*4882a593Smuzhiyun 				port->icount.overrun++;
226*4882a593Smuzhiyun 			} else if (status & ALTERA_UART_STATUS_FE_MSK) {
227*4882a593Smuzhiyun 				port->icount.frame++;
228*4882a593Smuzhiyun 			}
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun 			status &= port->read_status_mask;
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 			if (status & ALTERA_UART_STATUS_BRK_MSK)
233*4882a593Smuzhiyun 				flag = TTY_BREAK;
234*4882a593Smuzhiyun 			else if (status & ALTERA_UART_STATUS_PE_MSK)
235*4882a593Smuzhiyun 				flag = TTY_PARITY;
236*4882a593Smuzhiyun 			else if (status & ALTERA_UART_STATUS_FE_MSK)
237*4882a593Smuzhiyun 				flag = TTY_FRAME;
238*4882a593Smuzhiyun 		}
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 		if (uart_handle_sysrq_char(port, ch))
241*4882a593Smuzhiyun 			continue;
242*4882a593Smuzhiyun 		uart_insert_char(port, status, ALTERA_UART_STATUS_ROE_MSK, ch,
243*4882a593Smuzhiyun 				 flag);
244*4882a593Smuzhiyun 	}
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	spin_unlock(&port->lock);
247*4882a593Smuzhiyun 	tty_flip_buffer_push(&port->state->port);
248*4882a593Smuzhiyun 	spin_lock(&port->lock);
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun 
altera_uart_tx_chars(struct altera_uart * pp)251*4882a593Smuzhiyun static void altera_uart_tx_chars(struct altera_uart *pp)
252*4882a593Smuzhiyun {
253*4882a593Smuzhiyun 	struct uart_port *port = &pp->port;
254*4882a593Smuzhiyun 	struct circ_buf *xmit = &port->state->xmit;
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	if (port->x_char) {
257*4882a593Smuzhiyun 		/* Send special char - probably flow control */
258*4882a593Smuzhiyun 		altera_uart_writel(port, port->x_char, ALTERA_UART_TXDATA_REG);
259*4882a593Smuzhiyun 		port->x_char = 0;
260*4882a593Smuzhiyun 		port->icount.tx++;
261*4882a593Smuzhiyun 		return;
262*4882a593Smuzhiyun 	}
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 	while (altera_uart_readl(port, ALTERA_UART_STATUS_REG) &
265*4882a593Smuzhiyun 	       ALTERA_UART_STATUS_TRDY_MSK) {
266*4882a593Smuzhiyun 		if (xmit->head == xmit->tail)
267*4882a593Smuzhiyun 			break;
268*4882a593Smuzhiyun 		altera_uart_writel(port, xmit->buf[xmit->tail],
269*4882a593Smuzhiyun 		       ALTERA_UART_TXDATA_REG);
270*4882a593Smuzhiyun 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
271*4882a593Smuzhiyun 		port->icount.tx++;
272*4882a593Smuzhiyun 	}
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
275*4882a593Smuzhiyun 		uart_write_wakeup(port);
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 	if (xmit->head == xmit->tail) {
278*4882a593Smuzhiyun 		pp->imr &= ~ALTERA_UART_CONTROL_TRDY_MSK;
279*4882a593Smuzhiyun 		altera_uart_update_ctrl_reg(pp);
280*4882a593Smuzhiyun 	}
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun 
altera_uart_interrupt(int irq,void * data)283*4882a593Smuzhiyun static irqreturn_t altera_uart_interrupt(int irq, void *data)
284*4882a593Smuzhiyun {
285*4882a593Smuzhiyun 	struct uart_port *port = data;
286*4882a593Smuzhiyun 	struct altera_uart *pp = container_of(port, struct altera_uart, port);
287*4882a593Smuzhiyun 	unsigned int isr;
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun 	isr = altera_uart_readl(port, ALTERA_UART_STATUS_REG) & pp->imr;
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	spin_lock(&port->lock);
292*4882a593Smuzhiyun 	if (isr & ALTERA_UART_STATUS_RRDY_MSK)
293*4882a593Smuzhiyun 		altera_uart_rx_chars(pp);
294*4882a593Smuzhiyun 	if (isr & ALTERA_UART_STATUS_TRDY_MSK)
295*4882a593Smuzhiyun 		altera_uart_tx_chars(pp);
296*4882a593Smuzhiyun 	spin_unlock(&port->lock);
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 	return IRQ_RETVAL(isr);
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun 
altera_uart_timer(struct timer_list * t)301*4882a593Smuzhiyun static void altera_uart_timer(struct timer_list *t)
302*4882a593Smuzhiyun {
303*4882a593Smuzhiyun 	struct altera_uart *pp = from_timer(pp, t, tmr);
304*4882a593Smuzhiyun 	struct uart_port *port = &pp->port;
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun 	altera_uart_interrupt(0, port);
307*4882a593Smuzhiyun 	mod_timer(&pp->tmr, jiffies + uart_poll_timeout(port));
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun 
altera_uart_config_port(struct uart_port * port,int flags)310*4882a593Smuzhiyun static void altera_uart_config_port(struct uart_port *port, int flags)
311*4882a593Smuzhiyun {
312*4882a593Smuzhiyun 	port->type = PORT_ALTERA_UART;
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun 	/* Clear mask, so no surprise interrupts. */
315*4882a593Smuzhiyun 	altera_uart_writel(port, 0, ALTERA_UART_CONTROL_REG);
316*4882a593Smuzhiyun 	/* Clear status register */
317*4882a593Smuzhiyun 	altera_uart_writel(port, 0, ALTERA_UART_STATUS_REG);
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun 
altera_uart_startup(struct uart_port * port)320*4882a593Smuzhiyun static int altera_uart_startup(struct uart_port *port)
321*4882a593Smuzhiyun {
322*4882a593Smuzhiyun 	struct altera_uart *pp = container_of(port, struct altera_uart, port);
323*4882a593Smuzhiyun 	unsigned long flags;
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun 	if (!port->irq) {
326*4882a593Smuzhiyun 		timer_setup(&pp->tmr, altera_uart_timer, 0);
327*4882a593Smuzhiyun 		mod_timer(&pp->tmr, jiffies + uart_poll_timeout(port));
328*4882a593Smuzhiyun 	} else {
329*4882a593Smuzhiyun 		int ret;
330*4882a593Smuzhiyun 
331*4882a593Smuzhiyun 		ret = request_irq(port->irq, altera_uart_interrupt, 0,
332*4882a593Smuzhiyun 				DRV_NAME, port);
333*4882a593Smuzhiyun 		if (ret) {
334*4882a593Smuzhiyun 			pr_err(DRV_NAME ": unable to attach Altera UART %d "
335*4882a593Smuzhiyun 			       "interrupt vector=%d\n", port->line, port->irq);
336*4882a593Smuzhiyun 			return ret;
337*4882a593Smuzhiyun 		}
338*4882a593Smuzhiyun 	}
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	spin_lock_irqsave(&port->lock, flags);
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun 	/* Enable RX interrupts now */
343*4882a593Smuzhiyun 	pp->imr = ALTERA_UART_CONTROL_RRDY_MSK;
344*4882a593Smuzhiyun 	altera_uart_update_ctrl_reg(pp);
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun 	spin_unlock_irqrestore(&port->lock, flags);
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun 	return 0;
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun 
altera_uart_shutdown(struct uart_port * port)351*4882a593Smuzhiyun static void altera_uart_shutdown(struct uart_port *port)
352*4882a593Smuzhiyun {
353*4882a593Smuzhiyun 	struct altera_uart *pp = container_of(port, struct altera_uart, port);
354*4882a593Smuzhiyun 	unsigned long flags;
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun 	spin_lock_irqsave(&port->lock, flags);
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun 	/* Disable all interrupts now */
359*4882a593Smuzhiyun 	pp->imr = 0;
360*4882a593Smuzhiyun 	altera_uart_update_ctrl_reg(pp);
361*4882a593Smuzhiyun 
362*4882a593Smuzhiyun 	spin_unlock_irqrestore(&port->lock, flags);
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun 	if (port->irq)
365*4882a593Smuzhiyun 		free_irq(port->irq, port);
366*4882a593Smuzhiyun 	else
367*4882a593Smuzhiyun 		del_timer_sync(&pp->tmr);
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun 
altera_uart_type(struct uart_port * port)370*4882a593Smuzhiyun static const char *altera_uart_type(struct uart_port *port)
371*4882a593Smuzhiyun {
372*4882a593Smuzhiyun 	return (port->type == PORT_ALTERA_UART) ? "Altera UART" : NULL;
373*4882a593Smuzhiyun }
374*4882a593Smuzhiyun 
altera_uart_request_port(struct uart_port * port)375*4882a593Smuzhiyun static int altera_uart_request_port(struct uart_port *port)
376*4882a593Smuzhiyun {
377*4882a593Smuzhiyun 	/* UARTs always present */
378*4882a593Smuzhiyun 	return 0;
379*4882a593Smuzhiyun }
380*4882a593Smuzhiyun 
altera_uart_release_port(struct uart_port * port)381*4882a593Smuzhiyun static void altera_uart_release_port(struct uart_port *port)
382*4882a593Smuzhiyun {
383*4882a593Smuzhiyun 	/* Nothing to release... */
384*4882a593Smuzhiyun }
385*4882a593Smuzhiyun 
altera_uart_verify_port(struct uart_port * port,struct serial_struct * ser)386*4882a593Smuzhiyun static int altera_uart_verify_port(struct uart_port *port,
387*4882a593Smuzhiyun 				   struct serial_struct *ser)
388*4882a593Smuzhiyun {
389*4882a593Smuzhiyun 	if ((ser->type != PORT_UNKNOWN) && (ser->type != PORT_ALTERA_UART))
390*4882a593Smuzhiyun 		return -EINVAL;
391*4882a593Smuzhiyun 	return 0;
392*4882a593Smuzhiyun }
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun #ifdef CONFIG_CONSOLE_POLL
altera_uart_poll_get_char(struct uart_port * port)395*4882a593Smuzhiyun static int altera_uart_poll_get_char(struct uart_port *port)
396*4882a593Smuzhiyun {
397*4882a593Smuzhiyun 	while (!(altera_uart_readl(port, ALTERA_UART_STATUS_REG) &
398*4882a593Smuzhiyun 		 ALTERA_UART_STATUS_RRDY_MSK))
399*4882a593Smuzhiyun 		cpu_relax();
400*4882a593Smuzhiyun 
401*4882a593Smuzhiyun 	return altera_uart_readl(port, ALTERA_UART_RXDATA_REG);
402*4882a593Smuzhiyun }
403*4882a593Smuzhiyun 
altera_uart_poll_put_char(struct uart_port * port,unsigned char c)404*4882a593Smuzhiyun static void altera_uart_poll_put_char(struct uart_port *port, unsigned char c)
405*4882a593Smuzhiyun {
406*4882a593Smuzhiyun 	while (!(altera_uart_readl(port, ALTERA_UART_STATUS_REG) &
407*4882a593Smuzhiyun 		 ALTERA_UART_STATUS_TRDY_MSK))
408*4882a593Smuzhiyun 		cpu_relax();
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 	altera_uart_writel(port, c, ALTERA_UART_TXDATA_REG);
411*4882a593Smuzhiyun }
412*4882a593Smuzhiyun #endif
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun /*
415*4882a593Smuzhiyun  *	Define the basic serial functions we support.
416*4882a593Smuzhiyun  */
417*4882a593Smuzhiyun static const struct uart_ops altera_uart_ops = {
418*4882a593Smuzhiyun 	.tx_empty	= altera_uart_tx_empty,
419*4882a593Smuzhiyun 	.get_mctrl	= altera_uart_get_mctrl,
420*4882a593Smuzhiyun 	.set_mctrl	= altera_uart_set_mctrl,
421*4882a593Smuzhiyun 	.start_tx	= altera_uart_start_tx,
422*4882a593Smuzhiyun 	.stop_tx	= altera_uart_stop_tx,
423*4882a593Smuzhiyun 	.stop_rx	= altera_uart_stop_rx,
424*4882a593Smuzhiyun 	.break_ctl	= altera_uart_break_ctl,
425*4882a593Smuzhiyun 	.startup	= altera_uart_startup,
426*4882a593Smuzhiyun 	.shutdown	= altera_uart_shutdown,
427*4882a593Smuzhiyun 	.set_termios	= altera_uart_set_termios,
428*4882a593Smuzhiyun 	.type		= altera_uart_type,
429*4882a593Smuzhiyun 	.request_port	= altera_uart_request_port,
430*4882a593Smuzhiyun 	.release_port	= altera_uart_release_port,
431*4882a593Smuzhiyun 	.config_port	= altera_uart_config_port,
432*4882a593Smuzhiyun 	.verify_port	= altera_uart_verify_port,
433*4882a593Smuzhiyun #ifdef CONFIG_CONSOLE_POLL
434*4882a593Smuzhiyun 	.poll_get_char	= altera_uart_poll_get_char,
435*4882a593Smuzhiyun 	.poll_put_char	= altera_uart_poll_put_char,
436*4882a593Smuzhiyun #endif
437*4882a593Smuzhiyun };
438*4882a593Smuzhiyun 
439*4882a593Smuzhiyun static struct altera_uart altera_uart_ports[CONFIG_SERIAL_ALTERA_UART_MAXPORTS];
440*4882a593Smuzhiyun 
441*4882a593Smuzhiyun #if defined(CONFIG_SERIAL_ALTERA_UART_CONSOLE)
442*4882a593Smuzhiyun 
altera_uart_console_putc(struct uart_port * port,int c)443*4882a593Smuzhiyun static void altera_uart_console_putc(struct uart_port *port, int c)
444*4882a593Smuzhiyun {
445*4882a593Smuzhiyun 	while (!(altera_uart_readl(port, ALTERA_UART_STATUS_REG) &
446*4882a593Smuzhiyun 		 ALTERA_UART_STATUS_TRDY_MSK))
447*4882a593Smuzhiyun 		cpu_relax();
448*4882a593Smuzhiyun 
449*4882a593Smuzhiyun 	altera_uart_writel(port, c, ALTERA_UART_TXDATA_REG);
450*4882a593Smuzhiyun }
451*4882a593Smuzhiyun 
altera_uart_console_write(struct console * co,const char * s,unsigned int count)452*4882a593Smuzhiyun static void altera_uart_console_write(struct console *co, const char *s,
453*4882a593Smuzhiyun 				      unsigned int count)
454*4882a593Smuzhiyun {
455*4882a593Smuzhiyun 	struct uart_port *port = &(altera_uart_ports + co->index)->port;
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun 	uart_console_write(port, s, count, altera_uart_console_putc);
458*4882a593Smuzhiyun }
459*4882a593Smuzhiyun 
altera_uart_console_setup(struct console * co,char * options)460*4882a593Smuzhiyun static int __init altera_uart_console_setup(struct console *co, char *options)
461*4882a593Smuzhiyun {
462*4882a593Smuzhiyun 	struct uart_port *port;
463*4882a593Smuzhiyun 	int baud = CONFIG_SERIAL_ALTERA_UART_BAUDRATE;
464*4882a593Smuzhiyun 	int bits = 8;
465*4882a593Smuzhiyun 	int parity = 'n';
466*4882a593Smuzhiyun 	int flow = 'n';
467*4882a593Smuzhiyun 
468*4882a593Smuzhiyun 	if (co->index < 0 || co->index >= CONFIG_SERIAL_ALTERA_UART_MAXPORTS)
469*4882a593Smuzhiyun 		return -EINVAL;
470*4882a593Smuzhiyun 	port = &altera_uart_ports[co->index].port;
471*4882a593Smuzhiyun 	if (!port->membase)
472*4882a593Smuzhiyun 		return -ENODEV;
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun 	if (options)
475*4882a593Smuzhiyun 		uart_parse_options(options, &baud, &parity, &bits, &flow);
476*4882a593Smuzhiyun 
477*4882a593Smuzhiyun 	return uart_set_options(port, co, baud, parity, bits, flow);
478*4882a593Smuzhiyun }
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun static struct uart_driver altera_uart_driver;
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun static struct console altera_uart_console = {
483*4882a593Smuzhiyun 	.name	= "ttyAL",
484*4882a593Smuzhiyun 	.write	= altera_uart_console_write,
485*4882a593Smuzhiyun 	.device	= uart_console_device,
486*4882a593Smuzhiyun 	.setup	= altera_uart_console_setup,
487*4882a593Smuzhiyun 	.flags	= CON_PRINTBUFFER,
488*4882a593Smuzhiyun 	.index	= -1,
489*4882a593Smuzhiyun 	.data	= &altera_uart_driver,
490*4882a593Smuzhiyun };
491*4882a593Smuzhiyun 
altera_uart_console_init(void)492*4882a593Smuzhiyun static int __init altera_uart_console_init(void)
493*4882a593Smuzhiyun {
494*4882a593Smuzhiyun 	register_console(&altera_uart_console);
495*4882a593Smuzhiyun 	return 0;
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun 
498*4882a593Smuzhiyun console_initcall(altera_uart_console_init);
499*4882a593Smuzhiyun 
500*4882a593Smuzhiyun #define	ALTERA_UART_CONSOLE	(&altera_uart_console)
501*4882a593Smuzhiyun 
altera_uart_earlycon_write(struct console * co,const char * s,unsigned int count)502*4882a593Smuzhiyun static void altera_uart_earlycon_write(struct console *co, const char *s,
503*4882a593Smuzhiyun 				       unsigned int count)
504*4882a593Smuzhiyun {
505*4882a593Smuzhiyun 	struct earlycon_device *dev = co->data;
506*4882a593Smuzhiyun 
507*4882a593Smuzhiyun 	uart_console_write(&dev->port, s, count, altera_uart_console_putc);
508*4882a593Smuzhiyun }
509*4882a593Smuzhiyun 
altera_uart_earlycon_setup(struct earlycon_device * dev,const char * options)510*4882a593Smuzhiyun static int __init altera_uart_earlycon_setup(struct earlycon_device *dev,
511*4882a593Smuzhiyun 					     const char *options)
512*4882a593Smuzhiyun {
513*4882a593Smuzhiyun 	struct uart_port *port = &dev->port;
514*4882a593Smuzhiyun 
515*4882a593Smuzhiyun 	if (!port->membase)
516*4882a593Smuzhiyun 		return -ENODEV;
517*4882a593Smuzhiyun 
518*4882a593Smuzhiyun 	/* Enable RX interrupts now */
519*4882a593Smuzhiyun 	altera_uart_writel(port, ALTERA_UART_CONTROL_RRDY_MSK,
520*4882a593Smuzhiyun 			   ALTERA_UART_CONTROL_REG);
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun 	if (dev->baud) {
523*4882a593Smuzhiyun 		unsigned int baudclk = port->uartclk / dev->baud;
524*4882a593Smuzhiyun 
525*4882a593Smuzhiyun 		altera_uart_writel(port, baudclk, ALTERA_UART_DIVISOR_REG);
526*4882a593Smuzhiyun 	}
527*4882a593Smuzhiyun 
528*4882a593Smuzhiyun 	dev->con->write = altera_uart_earlycon_write;
529*4882a593Smuzhiyun 	return 0;
530*4882a593Smuzhiyun }
531*4882a593Smuzhiyun 
532*4882a593Smuzhiyun OF_EARLYCON_DECLARE(uart, "altr,uart-1.0", altera_uart_earlycon_setup);
533*4882a593Smuzhiyun 
534*4882a593Smuzhiyun #else
535*4882a593Smuzhiyun 
536*4882a593Smuzhiyun #define	ALTERA_UART_CONSOLE	NULL
537*4882a593Smuzhiyun 
538*4882a593Smuzhiyun #endif /* CONFIG_SERIAL_ALTERA_UART_CONSOLE */
539*4882a593Smuzhiyun 
540*4882a593Smuzhiyun /*
541*4882a593Smuzhiyun  *	Define the altera_uart UART driver structure.
542*4882a593Smuzhiyun  */
543*4882a593Smuzhiyun static struct uart_driver altera_uart_driver = {
544*4882a593Smuzhiyun 	.owner		= THIS_MODULE,
545*4882a593Smuzhiyun 	.driver_name	= DRV_NAME,
546*4882a593Smuzhiyun 	.dev_name	= "ttyAL",
547*4882a593Smuzhiyun 	.major		= SERIAL_ALTERA_MAJOR,
548*4882a593Smuzhiyun 	.minor		= SERIAL_ALTERA_MINOR,
549*4882a593Smuzhiyun 	.nr		= CONFIG_SERIAL_ALTERA_UART_MAXPORTS,
550*4882a593Smuzhiyun 	.cons		= ALTERA_UART_CONSOLE,
551*4882a593Smuzhiyun };
552*4882a593Smuzhiyun 
altera_uart_probe(struct platform_device * pdev)553*4882a593Smuzhiyun static int altera_uart_probe(struct platform_device *pdev)
554*4882a593Smuzhiyun {
555*4882a593Smuzhiyun 	struct altera_uart_platform_uart *platp = dev_get_platdata(&pdev->dev);
556*4882a593Smuzhiyun 	struct uart_port *port;
557*4882a593Smuzhiyun 	struct resource *res_mem;
558*4882a593Smuzhiyun 	struct resource *res_irq;
559*4882a593Smuzhiyun 	int i = pdev->id;
560*4882a593Smuzhiyun 	int ret;
561*4882a593Smuzhiyun 
562*4882a593Smuzhiyun 	/* if id is -1 scan for a free id and use that one */
563*4882a593Smuzhiyun 	if (i == -1) {
564*4882a593Smuzhiyun 		for (i = 0; i < CONFIG_SERIAL_ALTERA_UART_MAXPORTS; i++)
565*4882a593Smuzhiyun 			if (altera_uart_ports[i].port.mapbase == 0)
566*4882a593Smuzhiyun 				break;
567*4882a593Smuzhiyun 	}
568*4882a593Smuzhiyun 
569*4882a593Smuzhiyun 	if (i < 0 || i >= CONFIG_SERIAL_ALTERA_UART_MAXPORTS)
570*4882a593Smuzhiyun 		return -EINVAL;
571*4882a593Smuzhiyun 
572*4882a593Smuzhiyun 	port = &altera_uart_ports[i].port;
573*4882a593Smuzhiyun 
574*4882a593Smuzhiyun 	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
575*4882a593Smuzhiyun 	if (res_mem)
576*4882a593Smuzhiyun 		port->mapbase = res_mem->start;
577*4882a593Smuzhiyun 	else if (platp)
578*4882a593Smuzhiyun 		port->mapbase = platp->mapbase;
579*4882a593Smuzhiyun 	else
580*4882a593Smuzhiyun 		return -EINVAL;
581*4882a593Smuzhiyun 
582*4882a593Smuzhiyun 	res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
583*4882a593Smuzhiyun 	if (res_irq)
584*4882a593Smuzhiyun 		port->irq = res_irq->start;
585*4882a593Smuzhiyun 	else if (platp)
586*4882a593Smuzhiyun 		port->irq = platp->irq;
587*4882a593Smuzhiyun 
588*4882a593Smuzhiyun 	/* Check platform data first so we can override device node data */
589*4882a593Smuzhiyun 	if (platp)
590*4882a593Smuzhiyun 		port->uartclk = platp->uartclk;
591*4882a593Smuzhiyun 	else {
592*4882a593Smuzhiyun 		ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
593*4882a593Smuzhiyun 					   &port->uartclk);
594*4882a593Smuzhiyun 		if (ret)
595*4882a593Smuzhiyun 			return ret;
596*4882a593Smuzhiyun 	}
597*4882a593Smuzhiyun 
598*4882a593Smuzhiyun 	port->membase = ioremap(port->mapbase, ALTERA_UART_SIZE);
599*4882a593Smuzhiyun 	if (!port->membase)
600*4882a593Smuzhiyun 		return -ENOMEM;
601*4882a593Smuzhiyun 
602*4882a593Smuzhiyun 	if (platp)
603*4882a593Smuzhiyun 		port->regshift = platp->bus_shift;
604*4882a593Smuzhiyun 	else
605*4882a593Smuzhiyun 		port->regshift = 0;
606*4882a593Smuzhiyun 
607*4882a593Smuzhiyun 	port->line = i;
608*4882a593Smuzhiyun 	port->type = PORT_ALTERA_UART;
609*4882a593Smuzhiyun 	port->iotype = SERIAL_IO_MEM;
610*4882a593Smuzhiyun 	port->ops = &altera_uart_ops;
611*4882a593Smuzhiyun 	port->flags = UPF_BOOT_AUTOCONF;
612*4882a593Smuzhiyun 	port->dev = &pdev->dev;
613*4882a593Smuzhiyun 
614*4882a593Smuzhiyun 	platform_set_drvdata(pdev, port);
615*4882a593Smuzhiyun 
616*4882a593Smuzhiyun 	uart_add_one_port(&altera_uart_driver, port);
617*4882a593Smuzhiyun 
618*4882a593Smuzhiyun 	return 0;
619*4882a593Smuzhiyun }
620*4882a593Smuzhiyun 
altera_uart_remove(struct platform_device * pdev)621*4882a593Smuzhiyun static int altera_uart_remove(struct platform_device *pdev)
622*4882a593Smuzhiyun {
623*4882a593Smuzhiyun 	struct uart_port *port = platform_get_drvdata(pdev);
624*4882a593Smuzhiyun 
625*4882a593Smuzhiyun 	if (port) {
626*4882a593Smuzhiyun 		uart_remove_one_port(&altera_uart_driver, port);
627*4882a593Smuzhiyun 		port->mapbase = 0;
628*4882a593Smuzhiyun 		iounmap(port->membase);
629*4882a593Smuzhiyun 	}
630*4882a593Smuzhiyun 
631*4882a593Smuzhiyun 	return 0;
632*4882a593Smuzhiyun }
633*4882a593Smuzhiyun 
634*4882a593Smuzhiyun #ifdef CONFIG_OF
635*4882a593Smuzhiyun static const struct of_device_id altera_uart_match[] = {
636*4882a593Smuzhiyun 	{ .compatible = "ALTR,uart-1.0", },
637*4882a593Smuzhiyun 	{ .compatible = "altr,uart-1.0", },
638*4882a593Smuzhiyun 	{},
639*4882a593Smuzhiyun };
640*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, altera_uart_match);
641*4882a593Smuzhiyun #endif /* CONFIG_OF */
642*4882a593Smuzhiyun 
643*4882a593Smuzhiyun static struct platform_driver altera_uart_platform_driver = {
644*4882a593Smuzhiyun 	.probe	= altera_uart_probe,
645*4882a593Smuzhiyun 	.remove	= altera_uart_remove,
646*4882a593Smuzhiyun 	.driver	= {
647*4882a593Smuzhiyun 		.name		= DRV_NAME,
648*4882a593Smuzhiyun 		.of_match_table	= of_match_ptr(altera_uart_match),
649*4882a593Smuzhiyun 	},
650*4882a593Smuzhiyun };
651*4882a593Smuzhiyun 
altera_uart_init(void)652*4882a593Smuzhiyun static int __init altera_uart_init(void)
653*4882a593Smuzhiyun {
654*4882a593Smuzhiyun 	int rc;
655*4882a593Smuzhiyun 
656*4882a593Smuzhiyun 	rc = uart_register_driver(&altera_uart_driver);
657*4882a593Smuzhiyun 	if (rc)
658*4882a593Smuzhiyun 		return rc;
659*4882a593Smuzhiyun 	rc = platform_driver_register(&altera_uart_platform_driver);
660*4882a593Smuzhiyun 	if (rc)
661*4882a593Smuzhiyun 		uart_unregister_driver(&altera_uart_driver);
662*4882a593Smuzhiyun 	return rc;
663*4882a593Smuzhiyun }
664*4882a593Smuzhiyun 
altera_uart_exit(void)665*4882a593Smuzhiyun static void __exit altera_uart_exit(void)
666*4882a593Smuzhiyun {
667*4882a593Smuzhiyun 	platform_driver_unregister(&altera_uart_platform_driver);
668*4882a593Smuzhiyun 	uart_unregister_driver(&altera_uart_driver);
669*4882a593Smuzhiyun }
670*4882a593Smuzhiyun 
671*4882a593Smuzhiyun module_init(altera_uart_init);
672*4882a593Smuzhiyun module_exit(altera_uart_exit);
673*4882a593Smuzhiyun 
674*4882a593Smuzhiyun MODULE_DESCRIPTION("Altera UART driver");
675*4882a593Smuzhiyun MODULE_AUTHOR("Thomas Chou <thomas@wytron.com.tw>");
676*4882a593Smuzhiyun MODULE_LICENSE("GPL");
677*4882a593Smuzhiyun MODULE_ALIAS("platform:" DRV_NAME);
678*4882a593Smuzhiyun MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_ALTERA_MAJOR);
679