1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Probe module for 8250/16550-type PCI serial ports.
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 */
9 #undef DEBUG
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/string.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/delay.h>
16 #include <linux/tty.h>
17 #include <linux/serial_reg.h>
18 #include <linux/serial_core.h>
19 #include <linux/8250_pci.h>
20 #include <linux/bitops.h>
21
22 #include <asm/byteorder.h>
23 #include <asm/io.h>
24
25 #include "8250.h"
26
27 /*
28 * init function returns:
29 * > 0 - number of ports
30 * = 0 - use board->num_ports
31 * < 0 - error
32 */
33 struct pci_serial_quirk {
34 u32 vendor;
35 u32 device;
36 u32 subvendor;
37 u32 subdevice;
38 int (*probe)(struct pci_dev *dev);
39 int (*init)(struct pci_dev *dev);
40 int (*setup)(struct serial_private *,
41 const struct pciserial_board *,
42 struct uart_8250_port *, int);
43 void (*exit)(struct pci_dev *dev);
44 };
45
46 struct f815xxa_data {
47 spinlock_t lock;
48 int idx;
49 };
50
51 struct serial_private {
52 struct pci_dev *dev;
53 unsigned int nr;
54 struct pci_serial_quirk *quirk;
55 const struct pciserial_board *board;
56 int line[];
57 };
58
59 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e
60
61 static const struct pci_device_id pci_use_msi[] = {
62 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
63 0xA000, 0x1000) },
64 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
65 0xA000, 0x1000) },
66 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
67 0xA000, 0x1000) },
68 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
69 PCI_ANY_ID, PCI_ANY_ID) },
70 { }
71 };
72
73 static int pci_default_setup(struct serial_private*,
74 const struct pciserial_board*, struct uart_8250_port *, int);
75
moan_device(const char * str,struct pci_dev * dev)76 static void moan_device(const char *str, struct pci_dev *dev)
77 {
78 pci_err(dev, "%s\n"
79 "Please send the output of lspci -vv, this\n"
80 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
81 "manufacturer and name of serial board or\n"
82 "modem board to <linux-serial@vger.kernel.org>.\n",
83 str, dev->vendor, dev->device,
84 dev->subsystem_vendor, dev->subsystem_device);
85 }
86
87 static int
setup_port(struct serial_private * priv,struct uart_8250_port * port,u8 bar,unsigned int offset,int regshift)88 setup_port(struct serial_private *priv, struct uart_8250_port *port,
89 u8 bar, unsigned int offset, int regshift)
90 {
91 struct pci_dev *dev = priv->dev;
92
93 if (bar >= PCI_STD_NUM_BARS)
94 return -EINVAL;
95
96 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
97 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
98 return -ENOMEM;
99
100 port->port.iotype = UPIO_MEM;
101 port->port.iobase = 0;
102 port->port.mapbase = pci_resource_start(dev, bar) + offset;
103 port->port.membase = pcim_iomap_table(dev)[bar] + offset;
104 port->port.regshift = regshift;
105 } else {
106 port->port.iotype = UPIO_PORT;
107 port->port.iobase = pci_resource_start(dev, bar) + offset;
108 port->port.mapbase = 0;
109 port->port.membase = NULL;
110 port->port.regshift = 0;
111 }
112 return 0;
113 }
114
115 /*
116 * ADDI-DATA GmbH communication cards <info@addi-data.com>
117 */
addidata_apci7800_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)118 static int addidata_apci7800_setup(struct serial_private *priv,
119 const struct pciserial_board *board,
120 struct uart_8250_port *port, int idx)
121 {
122 unsigned int bar = 0, offset = board->first_offset;
123 bar = FL_GET_BASE(board->flags);
124
125 if (idx < 2) {
126 offset += idx * board->uart_offset;
127 } else if ((idx >= 2) && (idx < 4)) {
128 bar += 1;
129 offset += ((idx - 2) * board->uart_offset);
130 } else if ((idx >= 4) && (idx < 6)) {
131 bar += 2;
132 offset += ((idx - 4) * board->uart_offset);
133 } else if (idx >= 6) {
134 bar += 3;
135 offset += ((idx - 6) * board->uart_offset);
136 }
137
138 return setup_port(priv, port, bar, offset, board->reg_shift);
139 }
140
141 /*
142 * AFAVLAB uses a different mixture of BARs and offsets
143 * Not that ugly ;) -- HW
144 */
145 static int
afavlab_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)146 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
147 struct uart_8250_port *port, int idx)
148 {
149 unsigned int bar, offset = board->first_offset;
150
151 bar = FL_GET_BASE(board->flags);
152 if (idx < 4)
153 bar += idx;
154 else {
155 bar = 4;
156 offset += (idx - 4) * board->uart_offset;
157 }
158
159 return setup_port(priv, port, bar, offset, board->reg_shift);
160 }
161
162 /*
163 * HP's Remote Management Console. The Diva chip came in several
164 * different versions. N-class, L2000 and A500 have two Diva chips, each
165 * with 3 UARTs (the third UART on the second chip is unused). Superdome
166 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
167 * one Diva chip, but it has been expanded to 5 UARTs.
168 */
pci_hp_diva_init(struct pci_dev * dev)169 static int pci_hp_diva_init(struct pci_dev *dev)
170 {
171 int rc = 0;
172
173 switch (dev->subsystem_device) {
174 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
175 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
176 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
177 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
178 rc = 3;
179 break;
180 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
181 rc = 2;
182 break;
183 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
184 rc = 4;
185 break;
186 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
187 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
188 rc = 1;
189 break;
190 }
191
192 return rc;
193 }
194
195 /*
196 * HP's Diva chip puts the 4th/5th serial port further out, and
197 * some serial ports are supposed to be hidden on certain models.
198 */
199 static int
pci_hp_diva_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)200 pci_hp_diva_setup(struct serial_private *priv,
201 const struct pciserial_board *board,
202 struct uart_8250_port *port, int idx)
203 {
204 unsigned int offset = board->first_offset;
205 unsigned int bar = FL_GET_BASE(board->flags);
206
207 switch (priv->dev->subsystem_device) {
208 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
209 if (idx == 3)
210 idx++;
211 break;
212 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
213 if (idx > 0)
214 idx++;
215 if (idx > 2)
216 idx++;
217 break;
218 }
219 if (idx > 2)
220 offset = 0x18;
221
222 offset += idx * board->uart_offset;
223
224 return setup_port(priv, port, bar, offset, board->reg_shift);
225 }
226
227 /*
228 * Added for EKF Intel i960 serial boards
229 */
pci_inteli960ni_init(struct pci_dev * dev)230 static int pci_inteli960ni_init(struct pci_dev *dev)
231 {
232 u32 oldval;
233
234 if (!(dev->subsystem_device & 0x1000))
235 return -ENODEV;
236
237 /* is firmware started? */
238 pci_read_config_dword(dev, 0x44, &oldval);
239 if (oldval == 0x00001000L) { /* RESET value */
240 pci_dbg(dev, "Local i960 firmware missing\n");
241 return -ENODEV;
242 }
243 return 0;
244 }
245
246 /*
247 * Some PCI serial cards using the PLX 9050 PCI interface chip require
248 * that the card interrupt be explicitly enabled or disabled. This
249 * seems to be mainly needed on card using the PLX which also use I/O
250 * mapped memory.
251 */
pci_plx9050_init(struct pci_dev * dev)252 static int pci_plx9050_init(struct pci_dev *dev)
253 {
254 u8 irq_config;
255 void __iomem *p;
256
257 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
258 moan_device("no memory in bar 0", dev);
259 return 0;
260 }
261
262 irq_config = 0x41;
263 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
264 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
265 irq_config = 0x43;
266
267 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
268 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
269 /*
270 * As the megawolf cards have the int pins active
271 * high, and have 2 UART chips, both ints must be
272 * enabled on the 9050. Also, the UARTS are set in
273 * 16450 mode by default, so we have to enable the
274 * 16C950 'enhanced' mode so that we can use the
275 * deep FIFOs
276 */
277 irq_config = 0x5b;
278 /*
279 * enable/disable interrupts
280 */
281 p = ioremap(pci_resource_start(dev, 0), 0x80);
282 if (p == NULL)
283 return -ENOMEM;
284 writel(irq_config, p + 0x4c);
285
286 /*
287 * Read the register back to ensure that it took effect.
288 */
289 readl(p + 0x4c);
290 iounmap(p);
291
292 return 0;
293 }
294
pci_plx9050_exit(struct pci_dev * dev)295 static void pci_plx9050_exit(struct pci_dev *dev)
296 {
297 u8 __iomem *p;
298
299 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
300 return;
301
302 /*
303 * disable interrupts
304 */
305 p = ioremap(pci_resource_start(dev, 0), 0x80);
306 if (p != NULL) {
307 writel(0, p + 0x4c);
308
309 /*
310 * Read the register back to ensure that it took effect.
311 */
312 readl(p + 0x4c);
313 iounmap(p);
314 }
315 }
316
317 #define NI8420_INT_ENABLE_REG 0x38
318 #define NI8420_INT_ENABLE_BIT 0x2000
319
pci_ni8420_exit(struct pci_dev * dev)320 static void pci_ni8420_exit(struct pci_dev *dev)
321 {
322 void __iomem *p;
323 unsigned int bar = 0;
324
325 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
326 moan_device("no memory in bar", dev);
327 return;
328 }
329
330 p = pci_ioremap_bar(dev, bar);
331 if (p == NULL)
332 return;
333
334 /* Disable the CPU Interrupt */
335 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
336 p + NI8420_INT_ENABLE_REG);
337 iounmap(p);
338 }
339
340
341 /* MITE registers */
342 #define MITE_IOWBSR1 0xc4
343 #define MITE_IOWCR1 0xf4
344 #define MITE_LCIMR1 0x08
345 #define MITE_LCIMR2 0x10
346
347 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
348
pci_ni8430_exit(struct pci_dev * dev)349 static void pci_ni8430_exit(struct pci_dev *dev)
350 {
351 void __iomem *p;
352 unsigned int bar = 0;
353
354 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
355 moan_device("no memory in bar", dev);
356 return;
357 }
358
359 p = pci_ioremap_bar(dev, bar);
360 if (p == NULL)
361 return;
362
363 /* Disable the CPU Interrupt */
364 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
365 iounmap(p);
366 }
367
368 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
369 static int
sbs_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)370 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
371 struct uart_8250_port *port, int idx)
372 {
373 unsigned int bar, offset = board->first_offset;
374
375 bar = 0;
376
377 if (idx < 4) {
378 /* first four channels map to 0, 0x100, 0x200, 0x300 */
379 offset += idx * board->uart_offset;
380 } else if (idx < 8) {
381 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
382 offset += idx * board->uart_offset + 0xC00;
383 } else /* we have only 8 ports on PMC-OCTALPRO */
384 return 1;
385
386 return setup_port(priv, port, bar, offset, board->reg_shift);
387 }
388
389 /*
390 * This does initialization for PMC OCTALPRO cards:
391 * maps the device memory, resets the UARTs (needed, bc
392 * if the module is removed and inserted again, the card
393 * is in the sleep mode) and enables global interrupt.
394 */
395
396 /* global control register offset for SBS PMC-OctalPro */
397 #define OCT_REG_CR_OFF 0x500
398
sbs_init(struct pci_dev * dev)399 static int sbs_init(struct pci_dev *dev)
400 {
401 u8 __iomem *p;
402
403 p = pci_ioremap_bar(dev, 0);
404
405 if (p == NULL)
406 return -ENOMEM;
407 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
408 writeb(0x10, p + OCT_REG_CR_OFF);
409 udelay(50);
410 writeb(0x0, p + OCT_REG_CR_OFF);
411
412 /* Set bit-2 (INTENABLE) of Control Register */
413 writeb(0x4, p + OCT_REG_CR_OFF);
414 iounmap(p);
415
416 return 0;
417 }
418
419 /*
420 * Disables the global interrupt of PMC-OctalPro
421 */
422
sbs_exit(struct pci_dev * dev)423 static void sbs_exit(struct pci_dev *dev)
424 {
425 u8 __iomem *p;
426
427 p = pci_ioremap_bar(dev, 0);
428 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
429 if (p != NULL)
430 writeb(0, p + OCT_REG_CR_OFF);
431 iounmap(p);
432 }
433
434 /*
435 * SIIG serial cards have an PCI interface chip which also controls
436 * the UART clocking frequency. Each UART can be clocked independently
437 * (except cards equipped with 4 UARTs) and initial clocking settings
438 * are stored in the EEPROM chip. It can cause problems because this
439 * version of serial driver doesn't support differently clocked UART's
440 * on single PCI card. To prevent this, initialization functions set
441 * high frequency clocking for all UART's on given card. It is safe (I
442 * hope) because it doesn't touch EEPROM settings to prevent conflicts
443 * with other OSes (like M$ DOS).
444 *
445 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
446 *
447 * There is two family of SIIG serial cards with different PCI
448 * interface chip and different configuration methods:
449 * - 10x cards have control registers in IO and/or memory space;
450 * - 20x cards have control registers in standard PCI configuration space.
451 *
452 * Note: all 10x cards have PCI device ids 0x10..
453 * all 20x cards have PCI device ids 0x20..
454 *
455 * There are also Quartet Serial cards which use Oxford Semiconductor
456 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
457 *
458 * Note: some SIIG cards are probed by the parport_serial object.
459 */
460
461 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
462 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
463
pci_siig10x_init(struct pci_dev * dev)464 static int pci_siig10x_init(struct pci_dev *dev)
465 {
466 u16 data;
467 void __iomem *p;
468
469 switch (dev->device & 0xfff8) {
470 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
471 data = 0xffdf;
472 break;
473 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
474 data = 0xf7ff;
475 break;
476 default: /* 1S1P, 4S */
477 data = 0xfffb;
478 break;
479 }
480
481 p = ioremap(pci_resource_start(dev, 0), 0x80);
482 if (p == NULL)
483 return -ENOMEM;
484
485 writew(readw(p + 0x28) & data, p + 0x28);
486 readw(p + 0x28);
487 iounmap(p);
488 return 0;
489 }
490
491 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
492 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
493
pci_siig20x_init(struct pci_dev * dev)494 static int pci_siig20x_init(struct pci_dev *dev)
495 {
496 u8 data;
497
498 /* Change clock frequency for the first UART. */
499 pci_read_config_byte(dev, 0x6f, &data);
500 pci_write_config_byte(dev, 0x6f, data & 0xef);
501
502 /* If this card has 2 UART, we have to do the same with second UART. */
503 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
504 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
505 pci_read_config_byte(dev, 0x73, &data);
506 pci_write_config_byte(dev, 0x73, data & 0xef);
507 }
508 return 0;
509 }
510
pci_siig_init(struct pci_dev * dev)511 static int pci_siig_init(struct pci_dev *dev)
512 {
513 unsigned int type = dev->device & 0xff00;
514
515 if (type == 0x1000)
516 return pci_siig10x_init(dev);
517 else if (type == 0x2000)
518 return pci_siig20x_init(dev);
519
520 moan_device("Unknown SIIG card", dev);
521 return -ENODEV;
522 }
523
pci_siig_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)524 static int pci_siig_setup(struct serial_private *priv,
525 const struct pciserial_board *board,
526 struct uart_8250_port *port, int idx)
527 {
528 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
529
530 if (idx > 3) {
531 bar = 4;
532 offset = (idx - 4) * 8;
533 }
534
535 return setup_port(priv, port, bar, offset, 0);
536 }
537
538 /*
539 * Timedia has an explosion of boards, and to avoid the PCI table from
540 * growing *huge*, we use this function to collapse some 70 entries
541 * in the PCI table into one, for sanity's and compactness's sake.
542 */
543 static const unsigned short timedia_single_port[] = {
544 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
545 };
546
547 static const unsigned short timedia_dual_port[] = {
548 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
549 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
550 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
551 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
552 0xD079, 0
553 };
554
555 static const unsigned short timedia_quad_port[] = {
556 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
557 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
558 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
559 0xB157, 0
560 };
561
562 static const unsigned short timedia_eight_port[] = {
563 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
564 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
565 };
566
567 static const struct timedia_struct {
568 int num;
569 const unsigned short *ids;
570 } timedia_data[] = {
571 { 1, timedia_single_port },
572 { 2, timedia_dual_port },
573 { 4, timedia_quad_port },
574 { 8, timedia_eight_port }
575 };
576
577 /*
578 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
579 * listing them individually, this driver merely grabs them all with
580 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
581 * and should be left free to be claimed by parport_serial instead.
582 */
pci_timedia_probe(struct pci_dev * dev)583 static int pci_timedia_probe(struct pci_dev *dev)
584 {
585 /*
586 * Check the third digit of the subdevice ID
587 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
588 */
589 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
590 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n",
591 dev->subsystem_device);
592 return -ENODEV;
593 }
594
595 return 0;
596 }
597
pci_timedia_init(struct pci_dev * dev)598 static int pci_timedia_init(struct pci_dev *dev)
599 {
600 const unsigned short *ids;
601 int i, j;
602
603 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
604 ids = timedia_data[i].ids;
605 for (j = 0; ids[j]; j++)
606 if (dev->subsystem_device == ids[j])
607 return timedia_data[i].num;
608 }
609 return 0;
610 }
611
612 /*
613 * Timedia/SUNIX uses a mixture of BARs and offsets
614 * Ugh, this is ugly as all hell --- TYT
615 */
616 static int
pci_timedia_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)617 pci_timedia_setup(struct serial_private *priv,
618 const struct pciserial_board *board,
619 struct uart_8250_port *port, int idx)
620 {
621 unsigned int bar = 0, offset = board->first_offset;
622
623 switch (idx) {
624 case 0:
625 bar = 0;
626 break;
627 case 1:
628 offset = board->uart_offset;
629 bar = 0;
630 break;
631 case 2:
632 bar = 1;
633 break;
634 case 3:
635 offset = board->uart_offset;
636 fallthrough;
637 case 4: /* BAR 2 */
638 case 5: /* BAR 3 */
639 case 6: /* BAR 4 */
640 case 7: /* BAR 5 */
641 bar = idx - 2;
642 }
643
644 return setup_port(priv, port, bar, offset, board->reg_shift);
645 }
646
647 /*
648 * Some Titan cards are also a little weird
649 */
650 static int
titan_400l_800l_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)651 titan_400l_800l_setup(struct serial_private *priv,
652 const struct pciserial_board *board,
653 struct uart_8250_port *port, int idx)
654 {
655 unsigned int bar, offset = board->first_offset;
656
657 switch (idx) {
658 case 0:
659 bar = 1;
660 break;
661 case 1:
662 bar = 2;
663 break;
664 default:
665 bar = 4;
666 offset = (idx - 2) * board->uart_offset;
667 }
668
669 return setup_port(priv, port, bar, offset, board->reg_shift);
670 }
671
pci_xircom_init(struct pci_dev * dev)672 static int pci_xircom_init(struct pci_dev *dev)
673 {
674 msleep(100);
675 return 0;
676 }
677
pci_ni8420_init(struct pci_dev * dev)678 static int pci_ni8420_init(struct pci_dev *dev)
679 {
680 void __iomem *p;
681 unsigned int bar = 0;
682
683 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
684 moan_device("no memory in bar", dev);
685 return 0;
686 }
687
688 p = pci_ioremap_bar(dev, bar);
689 if (p == NULL)
690 return -ENOMEM;
691
692 /* Enable CPU Interrupt */
693 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
694 p + NI8420_INT_ENABLE_REG);
695
696 iounmap(p);
697 return 0;
698 }
699
700 #define MITE_IOWBSR1_WSIZE 0xa
701 #define MITE_IOWBSR1_WIN_OFFSET 0x800
702 #define MITE_IOWBSR1_WENAB (1 << 7)
703 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
704 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
705 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
706
pci_ni8430_init(struct pci_dev * dev)707 static int pci_ni8430_init(struct pci_dev *dev)
708 {
709 void __iomem *p;
710 struct pci_bus_region region;
711 u32 device_window;
712 unsigned int bar = 0;
713
714 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
715 moan_device("no memory in bar", dev);
716 return 0;
717 }
718
719 p = pci_ioremap_bar(dev, bar);
720 if (p == NULL)
721 return -ENOMEM;
722
723 /*
724 * Set device window address and size in BAR0, while acknowledging that
725 * the resource structure may contain a translated address that differs
726 * from the address the device responds to.
727 */
728 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
729 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
730 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
731 writel(device_window, p + MITE_IOWBSR1);
732
733 /* Set window access to go to RAMSEL IO address space */
734 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
735 p + MITE_IOWCR1);
736
737 /* Enable IO Bus Interrupt 0 */
738 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
739
740 /* Enable CPU Interrupt */
741 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
742
743 iounmap(p);
744 return 0;
745 }
746
747 /* UART Port Control Register */
748 #define NI8430_PORTCON 0x0f
749 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
750
751 static int
pci_ni8430_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)752 pci_ni8430_setup(struct serial_private *priv,
753 const struct pciserial_board *board,
754 struct uart_8250_port *port, int idx)
755 {
756 struct pci_dev *dev = priv->dev;
757 void __iomem *p;
758 unsigned int bar, offset = board->first_offset;
759
760 if (idx >= board->num_ports)
761 return 1;
762
763 bar = FL_GET_BASE(board->flags);
764 offset += idx * board->uart_offset;
765
766 p = pci_ioremap_bar(dev, bar);
767 if (!p)
768 return -ENOMEM;
769
770 /* enable the transceiver */
771 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
772 p + offset + NI8430_PORTCON);
773
774 iounmap(p);
775
776 return setup_port(priv, port, bar, offset, board->reg_shift);
777 }
778
pci_netmos_9900_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)779 static int pci_netmos_9900_setup(struct serial_private *priv,
780 const struct pciserial_board *board,
781 struct uart_8250_port *port, int idx)
782 {
783 unsigned int bar;
784
785 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
786 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
787 /* netmos apparently orders BARs by datasheet layout, so serial
788 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
789 */
790 bar = 3 * idx;
791
792 return setup_port(priv, port, bar, 0, board->reg_shift);
793 } else {
794 return pci_default_setup(priv, board, port, idx);
795 }
796 }
797
798 /* the 99xx series comes with a range of device IDs and a variety
799 * of capabilities:
800 *
801 * 9900 has varying capabilities and can cascade to sub-controllers
802 * (cascading should be purely internal)
803 * 9904 is hardwired with 4 serial ports
804 * 9912 and 9922 are hardwired with 2 serial ports
805 */
pci_netmos_9900_numports(struct pci_dev * dev)806 static int pci_netmos_9900_numports(struct pci_dev *dev)
807 {
808 unsigned int c = dev->class;
809 unsigned int pi;
810 unsigned short sub_serports;
811
812 pi = c & 0xff;
813
814 if (pi == 2)
815 return 1;
816
817 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
818 /* two possibilities: 0x30ps encodes number of parallel and
819 * serial ports, or 0x1000 indicates *something*. This is not
820 * immediately obvious, since the 2s1p+4s configuration seems
821 * to offer all functionality on functions 0..2, while still
822 * advertising the same function 3 as the 4s+2s1p config.
823 */
824 sub_serports = dev->subsystem_device & 0xf;
825 if (sub_serports > 0)
826 return sub_serports;
827
828 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
829 return 0;
830 }
831
832 moan_device("unknown NetMos/Mostech program interface", dev);
833 return 0;
834 }
835
pci_netmos_init(struct pci_dev * dev)836 static int pci_netmos_init(struct pci_dev *dev)
837 {
838 /* subdevice 0x00PS means <P> parallel, <S> serial */
839 unsigned int num_serial = dev->subsystem_device & 0xf;
840
841 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
842 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
843 return 0;
844
845 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
846 dev->subsystem_device == 0x0299)
847 return 0;
848
849 switch (dev->device) { /* FALLTHROUGH on all */
850 case PCI_DEVICE_ID_NETMOS_9904:
851 case PCI_DEVICE_ID_NETMOS_9912:
852 case PCI_DEVICE_ID_NETMOS_9922:
853 case PCI_DEVICE_ID_NETMOS_9900:
854 num_serial = pci_netmos_9900_numports(dev);
855 break;
856
857 default:
858 break;
859 }
860
861 if (num_serial == 0) {
862 moan_device("unknown NetMos/Mostech device", dev);
863 return -ENODEV;
864 }
865
866 return num_serial;
867 }
868
869 /*
870 * These chips are available with optionally one parallel port and up to
871 * two serial ports. Unfortunately they all have the same product id.
872 *
873 * Basic configuration is done over a region of 32 I/O ports. The base
874 * ioport is called INTA or INTC, depending on docs/other drivers.
875 *
876 * The region of the 32 I/O ports is configured in POSIO0R...
877 */
878
879 /* registers */
880 #define ITE_887x_MISCR 0x9c
881 #define ITE_887x_INTCBAR 0x78
882 #define ITE_887x_UARTBAR 0x7c
883 #define ITE_887x_PS0BAR 0x10
884 #define ITE_887x_POSIO0 0x60
885
886 /* I/O space size */
887 #define ITE_887x_IOSIZE 32
888 /* I/O space size (bits 26-24; 8 bytes = 011b) */
889 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
890 /* I/O space size (bits 26-24; 32 bytes = 101b) */
891 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
892 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
893 #define ITE_887x_POSIO_SPEED (3 << 29)
894 /* enable IO_Space bit */
895 #define ITE_887x_POSIO_ENABLE (1 << 31)
896
897 /* inta_addr are the configuration addresses of the ITE */
898 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 };
pci_ite887x_init(struct pci_dev * dev)899 static int pci_ite887x_init(struct pci_dev *dev)
900 {
901 int ret, i, type;
902 struct resource *iobase = NULL;
903 u32 miscr, uartbar, ioport;
904
905 /* search for the base-ioport */
906 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) {
907 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
908 "ite887x");
909 if (iobase != NULL) {
910 /* write POSIO0R - speed | size | ioport */
911 pci_write_config_dword(dev, ITE_887x_POSIO0,
912 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
913 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
914 /* write INTCBAR - ioport */
915 pci_write_config_dword(dev, ITE_887x_INTCBAR,
916 inta_addr[i]);
917 ret = inb(inta_addr[i]);
918 if (ret != 0xff) {
919 /* ioport connected */
920 break;
921 }
922 release_region(iobase->start, ITE_887x_IOSIZE);
923 }
924 }
925
926 if (i == ARRAY_SIZE(inta_addr)) {
927 pci_err(dev, "could not find iobase\n");
928 return -ENODEV;
929 }
930
931 /* start of undocumented type checking (see parport_pc.c) */
932 type = inb(iobase->start + 0x18) & 0x0f;
933
934 switch (type) {
935 case 0x2: /* ITE8871 (1P) */
936 case 0xa: /* ITE8875 (1P) */
937 ret = 0;
938 break;
939 case 0xe: /* ITE8872 (2S1P) */
940 ret = 2;
941 break;
942 case 0x6: /* ITE8873 (1S) */
943 ret = 1;
944 break;
945 case 0x8: /* ITE8874 (2S) */
946 ret = 2;
947 break;
948 default:
949 moan_device("Unknown ITE887x", dev);
950 ret = -ENODEV;
951 }
952
953 /* configure all serial ports */
954 for (i = 0; i < ret; i++) {
955 /* read the I/O port from the device */
956 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
957 &ioport);
958 ioport &= 0x0000FF00; /* the actual base address */
959 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
960 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
961 ITE_887x_POSIO_IOSIZE_8 | ioport);
962
963 /* write the ioport to the UARTBAR */
964 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
965 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
966 uartbar |= (ioport << (16 * i)); /* set the ioport */
967 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
968
969 /* get current config */
970 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
971 /* disable interrupts (UARTx_Routing[3:0]) */
972 miscr &= ~(0xf << (12 - 4 * i));
973 /* activate the UART (UARTx_En) */
974 miscr |= 1 << (23 - i);
975 /* write new config with activated UART */
976 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
977 }
978
979 if (ret <= 0) {
980 /* the device has no UARTs if we get here */
981 release_region(iobase->start, ITE_887x_IOSIZE);
982 }
983
984 return ret;
985 }
986
pci_ite887x_exit(struct pci_dev * dev)987 static void pci_ite887x_exit(struct pci_dev *dev)
988 {
989 u32 ioport;
990 /* the ioport is bit 0-15 in POSIO0R */
991 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
992 ioport &= 0xffff;
993 release_region(ioport, ITE_887x_IOSIZE);
994 }
995
996 /*
997 * Oxford Semiconductor Inc.
998 * Check if an OxSemi device is part of the Tornado range of devices.
999 */
1000 #define PCI_VENDOR_ID_ENDRUN 0x7401
1001 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1002
pci_oxsemi_tornado_p(struct pci_dev * dev)1003 static bool pci_oxsemi_tornado_p(struct pci_dev *dev)
1004 {
1005 /* OxSemi Tornado devices are all 0xCxxx */
1006 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1007 (dev->device & 0xf000) != 0xc000)
1008 return false;
1009
1010 /* EndRun devices are all 0xExxx */
1011 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1012 (dev->device & 0xf000) != 0xe000)
1013 return false;
1014
1015 return true;
1016 }
1017
1018 /*
1019 * Determine the number of ports available on a Tornado device.
1020 */
pci_oxsemi_tornado_init(struct pci_dev * dev)1021 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1022 {
1023 u8 __iomem *p;
1024 unsigned long deviceID;
1025 unsigned int number_uarts = 0;
1026
1027 if (!pci_oxsemi_tornado_p(dev))
1028 return 0;
1029
1030 p = pci_iomap(dev, 0, 5);
1031 if (p == NULL)
1032 return -ENOMEM;
1033
1034 deviceID = ioread32(p);
1035 /* Tornado device */
1036 if (deviceID == 0x07000200) {
1037 number_uarts = ioread8(p + 4);
1038 pci_dbg(dev, "%d ports detected on %s PCI Express device\n",
1039 number_uarts,
1040 dev->vendor == PCI_VENDOR_ID_ENDRUN ?
1041 "EndRun" : "Oxford");
1042 }
1043 pci_iounmap(dev, p);
1044 return number_uarts;
1045 }
1046
pci_asix_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1047 static int pci_asix_setup(struct serial_private *priv,
1048 const struct pciserial_board *board,
1049 struct uart_8250_port *port, int idx)
1050 {
1051 port->bugs |= UART_BUG_PARITY;
1052 return pci_default_setup(priv, board, port, idx);
1053 }
1054
1055 /* Quatech devices have their own extra interface features */
1056
1057 struct quatech_feature {
1058 u16 devid;
1059 bool amcc;
1060 };
1061
1062 #define QPCR_TEST_FOR1 0x3F
1063 #define QPCR_TEST_GET1 0x00
1064 #define QPCR_TEST_FOR2 0x40
1065 #define QPCR_TEST_GET2 0x40
1066 #define QPCR_TEST_FOR3 0x80
1067 #define QPCR_TEST_GET3 0x40
1068 #define QPCR_TEST_FOR4 0xC0
1069 #define QPCR_TEST_GET4 0x80
1070
1071 #define QOPR_CLOCK_X1 0x0000
1072 #define QOPR_CLOCK_X2 0x0001
1073 #define QOPR_CLOCK_X4 0x0002
1074 #define QOPR_CLOCK_X8 0x0003
1075 #define QOPR_CLOCK_RATE_MASK 0x0003
1076
1077
1078 static struct quatech_feature quatech_cards[] = {
1079 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1080 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1081 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1082 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1083 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1084 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1085 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1086 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1087 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1088 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1089 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1090 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1091 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1092 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1093 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1094 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1095 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1096 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1097 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1098 { 0, }
1099 };
1100
pci_quatech_amcc(struct pci_dev * dev)1101 static int pci_quatech_amcc(struct pci_dev *dev)
1102 {
1103 struct quatech_feature *qf = &quatech_cards[0];
1104 while (qf->devid) {
1105 if (qf->devid == dev->device)
1106 return qf->amcc;
1107 qf++;
1108 }
1109 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device);
1110 return 0;
1111 };
1112
pci_quatech_rqopr(struct uart_8250_port * port)1113 static int pci_quatech_rqopr(struct uart_8250_port *port)
1114 {
1115 unsigned long base = port->port.iobase;
1116 u8 LCR, val;
1117
1118 LCR = inb(base + UART_LCR);
1119 outb(0xBF, base + UART_LCR);
1120 val = inb(base + UART_SCR);
1121 outb(LCR, base + UART_LCR);
1122 return val;
1123 }
1124
pci_quatech_wqopr(struct uart_8250_port * port,u8 qopr)1125 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1126 {
1127 unsigned long base = port->port.iobase;
1128 u8 LCR;
1129
1130 LCR = inb(base + UART_LCR);
1131 outb(0xBF, base + UART_LCR);
1132 inb(base + UART_SCR);
1133 outb(qopr, base + UART_SCR);
1134 outb(LCR, base + UART_LCR);
1135 }
1136
pci_quatech_rqmcr(struct uart_8250_port * port)1137 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1138 {
1139 unsigned long base = port->port.iobase;
1140 u8 LCR, val, qmcr;
1141
1142 LCR = inb(base + UART_LCR);
1143 outb(0xBF, base + UART_LCR);
1144 val = inb(base + UART_SCR);
1145 outb(val | 0x10, base + UART_SCR);
1146 qmcr = inb(base + UART_MCR);
1147 outb(val, base + UART_SCR);
1148 outb(LCR, base + UART_LCR);
1149
1150 return qmcr;
1151 }
1152
pci_quatech_wqmcr(struct uart_8250_port * port,u8 qmcr)1153 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1154 {
1155 unsigned long base = port->port.iobase;
1156 u8 LCR, val;
1157
1158 LCR = inb(base + UART_LCR);
1159 outb(0xBF, base + UART_LCR);
1160 val = inb(base + UART_SCR);
1161 outb(val | 0x10, base + UART_SCR);
1162 outb(qmcr, base + UART_MCR);
1163 outb(val, base + UART_SCR);
1164 outb(LCR, base + UART_LCR);
1165 }
1166
pci_quatech_has_qmcr(struct uart_8250_port * port)1167 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1168 {
1169 unsigned long base = port->port.iobase;
1170 u8 LCR, val;
1171
1172 LCR = inb(base + UART_LCR);
1173 outb(0xBF, base + UART_LCR);
1174 val = inb(base + UART_SCR);
1175 if (val & 0x20) {
1176 outb(0x80, UART_LCR);
1177 if (!(inb(UART_SCR) & 0x20)) {
1178 outb(LCR, base + UART_LCR);
1179 return 1;
1180 }
1181 }
1182 return 0;
1183 }
1184
pci_quatech_test(struct uart_8250_port * port)1185 static int pci_quatech_test(struct uart_8250_port *port)
1186 {
1187 u8 reg, qopr;
1188
1189 qopr = pci_quatech_rqopr(port);
1190 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1191 reg = pci_quatech_rqopr(port) & 0xC0;
1192 if (reg != QPCR_TEST_GET1)
1193 return -EINVAL;
1194 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1195 reg = pci_quatech_rqopr(port) & 0xC0;
1196 if (reg != QPCR_TEST_GET2)
1197 return -EINVAL;
1198 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1199 reg = pci_quatech_rqopr(port) & 0xC0;
1200 if (reg != QPCR_TEST_GET3)
1201 return -EINVAL;
1202 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1203 reg = pci_quatech_rqopr(port) & 0xC0;
1204 if (reg != QPCR_TEST_GET4)
1205 return -EINVAL;
1206
1207 pci_quatech_wqopr(port, qopr);
1208 return 0;
1209 }
1210
pci_quatech_clock(struct uart_8250_port * port)1211 static int pci_quatech_clock(struct uart_8250_port *port)
1212 {
1213 u8 qopr, reg, set;
1214 unsigned long clock;
1215
1216 if (pci_quatech_test(port) < 0)
1217 return 1843200;
1218
1219 qopr = pci_quatech_rqopr(port);
1220
1221 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1222 reg = pci_quatech_rqopr(port);
1223 if (reg & QOPR_CLOCK_X8) {
1224 clock = 1843200;
1225 goto out;
1226 }
1227 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1228 reg = pci_quatech_rqopr(port);
1229 if (!(reg & QOPR_CLOCK_X8)) {
1230 clock = 1843200;
1231 goto out;
1232 }
1233 reg &= QOPR_CLOCK_X8;
1234 if (reg == QOPR_CLOCK_X2) {
1235 clock = 3685400;
1236 set = QOPR_CLOCK_X2;
1237 } else if (reg == QOPR_CLOCK_X4) {
1238 clock = 7372800;
1239 set = QOPR_CLOCK_X4;
1240 } else if (reg == QOPR_CLOCK_X8) {
1241 clock = 14745600;
1242 set = QOPR_CLOCK_X8;
1243 } else {
1244 clock = 1843200;
1245 set = QOPR_CLOCK_X1;
1246 }
1247 qopr &= ~QOPR_CLOCK_RATE_MASK;
1248 qopr |= set;
1249
1250 out:
1251 pci_quatech_wqopr(port, qopr);
1252 return clock;
1253 }
1254
pci_quatech_rs422(struct uart_8250_port * port)1255 static int pci_quatech_rs422(struct uart_8250_port *port)
1256 {
1257 u8 qmcr;
1258 int rs422 = 0;
1259
1260 if (!pci_quatech_has_qmcr(port))
1261 return 0;
1262 qmcr = pci_quatech_rqmcr(port);
1263 pci_quatech_wqmcr(port, 0xFF);
1264 if (pci_quatech_rqmcr(port))
1265 rs422 = 1;
1266 pci_quatech_wqmcr(port, qmcr);
1267 return rs422;
1268 }
1269
pci_quatech_init(struct pci_dev * dev)1270 static int pci_quatech_init(struct pci_dev *dev)
1271 {
1272 if (pci_quatech_amcc(dev)) {
1273 unsigned long base = pci_resource_start(dev, 0);
1274 if (base) {
1275 u32 tmp;
1276
1277 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1278 tmp = inl(base + 0x3c);
1279 outl(tmp | 0x01000000, base + 0x3c);
1280 outl(tmp &= ~0x01000000, base + 0x3c);
1281 }
1282 }
1283 return 0;
1284 }
1285
pci_quatech_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1286 static int pci_quatech_setup(struct serial_private *priv,
1287 const struct pciserial_board *board,
1288 struct uart_8250_port *port, int idx)
1289 {
1290 /* Needed by pci_quatech calls below */
1291 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1292 /* Set up the clocking */
1293 port->port.uartclk = pci_quatech_clock(port);
1294 /* For now just warn about RS422 */
1295 if (pci_quatech_rs422(port))
1296 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n");
1297 return pci_default_setup(priv, board, port, idx);
1298 }
1299
pci_quatech_exit(struct pci_dev * dev)1300 static void pci_quatech_exit(struct pci_dev *dev)
1301 {
1302 }
1303
pci_default_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1304 static int pci_default_setup(struct serial_private *priv,
1305 const struct pciserial_board *board,
1306 struct uart_8250_port *port, int idx)
1307 {
1308 unsigned int bar, offset = board->first_offset, maxnr;
1309
1310 bar = FL_GET_BASE(board->flags);
1311 if (board->flags & FL_BASE_BARS)
1312 bar += idx;
1313 else
1314 offset += idx * board->uart_offset;
1315
1316 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1317 (board->reg_shift + 3);
1318
1319 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1320 return 1;
1321
1322 return setup_port(priv, port, bar, offset, board->reg_shift);
1323 }
1324 static void
pericom_do_set_divisor(struct uart_port * port,unsigned int baud,unsigned int quot,unsigned int quot_frac)1325 pericom_do_set_divisor(struct uart_port *port, unsigned int baud,
1326 unsigned int quot, unsigned int quot_frac)
1327 {
1328 int scr;
1329 int lcr;
1330
1331 for (scr = 16; scr > 4; scr--) {
1332 unsigned int maxrate = port->uartclk / scr;
1333 unsigned int divisor = max(maxrate / baud, 1U);
1334 int delta = maxrate / divisor - baud;
1335
1336 if (baud > maxrate + baud / 50)
1337 continue;
1338
1339 if (delta > baud / 50)
1340 divisor++;
1341
1342 if (divisor > 0xffff)
1343 continue;
1344
1345 /* Update delta due to possible divisor change */
1346 delta = maxrate / divisor - baud;
1347 if (abs(delta) < baud / 50) {
1348 lcr = serial_port_in(port, UART_LCR);
1349 serial_port_out(port, UART_LCR, lcr | 0x80);
1350 serial_port_out(port, UART_DLL, divisor & 0xff);
1351 serial_port_out(port, UART_DLM, divisor >> 8 & 0xff);
1352 serial_port_out(port, 2, 16 - scr);
1353 serial_port_out(port, UART_LCR, lcr);
1354 return;
1355 }
1356 }
1357 }
pci_pericom_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1358 static int pci_pericom_setup(struct serial_private *priv,
1359 const struct pciserial_board *board,
1360 struct uart_8250_port *port, int idx)
1361 {
1362 unsigned int bar, offset = board->first_offset, maxnr;
1363
1364 bar = FL_GET_BASE(board->flags);
1365 if (board->flags & FL_BASE_BARS)
1366 bar += idx;
1367 else
1368 offset += idx * board->uart_offset;
1369
1370
1371 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1372 (board->reg_shift + 3);
1373
1374 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1375 return 1;
1376
1377 port->port.set_divisor = pericom_do_set_divisor;
1378
1379 return setup_port(priv, port, bar, offset, board->reg_shift);
1380 }
1381
pci_pericom_setup_four_at_eight(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1382 static int pci_pericom_setup_four_at_eight(struct serial_private *priv,
1383 const struct pciserial_board *board,
1384 struct uart_8250_port *port, int idx)
1385 {
1386 unsigned int bar, offset = board->first_offset, maxnr;
1387
1388 bar = FL_GET_BASE(board->flags);
1389 if (board->flags & FL_BASE_BARS)
1390 bar += idx;
1391 else
1392 offset += idx * board->uart_offset;
1393
1394 if (idx==3)
1395 offset = 0x38;
1396
1397 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1398 (board->reg_shift + 3);
1399
1400 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1401 return 1;
1402
1403 port->port.set_divisor = pericom_do_set_divisor;
1404
1405 return setup_port(priv, port, bar, offset, board->reg_shift);
1406 }
1407
1408 static int
ce4100_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1409 ce4100_serial_setup(struct serial_private *priv,
1410 const struct pciserial_board *board,
1411 struct uart_8250_port *port, int idx)
1412 {
1413 int ret;
1414
1415 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1416 port->port.iotype = UPIO_MEM32;
1417 port->port.type = PORT_XSCALE;
1418 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1419 port->port.regshift = 2;
1420
1421 return ret;
1422 }
1423
1424 static int
pci_omegapci_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1425 pci_omegapci_setup(struct serial_private *priv,
1426 const struct pciserial_board *board,
1427 struct uart_8250_port *port, int idx)
1428 {
1429 return setup_port(priv, port, 2, idx * 8, 0);
1430 }
1431
1432 static int
pci_brcm_trumanage_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1433 pci_brcm_trumanage_setup(struct serial_private *priv,
1434 const struct pciserial_board *board,
1435 struct uart_8250_port *port, int idx)
1436 {
1437 int ret = pci_default_setup(priv, board, port, idx);
1438
1439 port->port.type = PORT_BRCM_TRUMANAGE;
1440 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1441 return ret;
1442 }
1443
1444 /* RTS will control by MCR if this bit is 0 */
1445 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1446 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1447 #define FINTEK_RTS_INVERT BIT(5)
1448
1449 /* We should do proper H/W transceiver setting before change to RS485 mode */
pci_fintek_rs485_config(struct uart_port * port,struct serial_rs485 * rs485)1450 static int pci_fintek_rs485_config(struct uart_port *port,
1451 struct serial_rs485 *rs485)
1452 {
1453 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1454 u8 setting;
1455 u8 *index = (u8 *) port->private_data;
1456
1457 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1458
1459 if (!rs485)
1460 rs485 = &port->rs485;
1461 else if (rs485->flags & SER_RS485_ENABLED)
1462 memset(rs485->padding, 0, sizeof(rs485->padding));
1463 else
1464 memset(rs485, 0, sizeof(*rs485));
1465
1466 /* F81504/508/512 not support RTS delay before or after send */
1467 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1468
1469 if (rs485->flags & SER_RS485_ENABLED) {
1470 /* Enable RTS H/W control mode */
1471 setting |= FINTEK_RTS_CONTROL_BY_HW;
1472
1473 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1474 /* RTS driving high on TX */
1475 setting &= ~FINTEK_RTS_INVERT;
1476 } else {
1477 /* RTS driving low on TX */
1478 setting |= FINTEK_RTS_INVERT;
1479 }
1480
1481 rs485->delay_rts_after_send = 0;
1482 rs485->delay_rts_before_send = 0;
1483 } else {
1484 /* Disable RTS H/W control mode */
1485 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1486 }
1487
1488 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1489
1490 if (rs485 != &port->rs485)
1491 port->rs485 = *rs485;
1492
1493 return 0;
1494 }
1495
pci_fintek_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1496 static int pci_fintek_setup(struct serial_private *priv,
1497 const struct pciserial_board *board,
1498 struct uart_8250_port *port, int idx)
1499 {
1500 struct pci_dev *pdev = priv->dev;
1501 u8 *data;
1502 u8 config_base;
1503 u16 iobase;
1504
1505 config_base = 0x40 + 0x08 * idx;
1506
1507 /* Get the io address from configuration space */
1508 pci_read_config_word(pdev, config_base + 4, &iobase);
1509
1510 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase);
1511
1512 port->port.iotype = UPIO_PORT;
1513 port->port.iobase = iobase;
1514 port->port.rs485_config = pci_fintek_rs485_config;
1515
1516 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1517 if (!data)
1518 return -ENOMEM;
1519
1520 /* preserve index in PCI configuration space */
1521 *data = idx;
1522 port->port.private_data = data;
1523
1524 return 0;
1525 }
1526
pci_fintek_init(struct pci_dev * dev)1527 static int pci_fintek_init(struct pci_dev *dev)
1528 {
1529 unsigned long iobase;
1530 u32 max_port, i;
1531 resource_size_t bar_data[3];
1532 u8 config_base;
1533 struct serial_private *priv = pci_get_drvdata(dev);
1534
1535 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1536 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1537 !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1538 return -ENODEV;
1539
1540 switch (dev->device) {
1541 case 0x1104: /* 4 ports */
1542 case 0x1108: /* 8 ports */
1543 max_port = dev->device & 0xff;
1544 break;
1545 case 0x1112: /* 12 ports */
1546 max_port = 12;
1547 break;
1548 default:
1549 return -EINVAL;
1550 }
1551
1552 /* Get the io address dispatch from the BIOS */
1553 bar_data[0] = pci_resource_start(dev, 5);
1554 bar_data[1] = pci_resource_start(dev, 4);
1555 bar_data[2] = pci_resource_start(dev, 3);
1556
1557 for (i = 0; i < max_port; ++i) {
1558 /* UART0 configuration offset start from 0x40 */
1559 config_base = 0x40 + 0x08 * i;
1560
1561 /* Calculate Real IO Port */
1562 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1563
1564 /* Enable UART I/O port */
1565 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1566
1567 /* Select 128-byte FIFO and 8x FIFO threshold */
1568 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1569
1570 /* LSB UART */
1571 pci_write_config_byte(dev, config_base + 0x04,
1572 (u8)(iobase & 0xff));
1573
1574 /* MSB UART */
1575 pci_write_config_byte(dev, config_base + 0x05,
1576 (u8)((iobase & 0xff00) >> 8));
1577
1578 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1579
1580 if (!priv) {
1581 /* First init without port data
1582 * force init to RS232 Mode
1583 */
1584 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1585 }
1586 }
1587
1588 return max_port;
1589 }
1590
f815xxa_mem_serial_out(struct uart_port * p,int offset,int value)1591 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value)
1592 {
1593 struct f815xxa_data *data = p->private_data;
1594 unsigned long flags;
1595
1596 spin_lock_irqsave(&data->lock, flags);
1597 writeb(value, p->membase + offset);
1598 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */
1599 spin_unlock_irqrestore(&data->lock, flags);
1600 }
1601
pci_fintek_f815xxa_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1602 static int pci_fintek_f815xxa_setup(struct serial_private *priv,
1603 const struct pciserial_board *board,
1604 struct uart_8250_port *port, int idx)
1605 {
1606 struct pci_dev *pdev = priv->dev;
1607 struct f815xxa_data *data;
1608
1609 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
1610 if (!data)
1611 return -ENOMEM;
1612
1613 data->idx = idx;
1614 spin_lock_init(&data->lock);
1615
1616 port->port.private_data = data;
1617 port->port.iotype = UPIO_MEM;
1618 port->port.flags |= UPF_IOREMAP;
1619 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx;
1620 port->port.serial_out = f815xxa_mem_serial_out;
1621
1622 return 0;
1623 }
1624
pci_fintek_f815xxa_init(struct pci_dev * dev)1625 static int pci_fintek_f815xxa_init(struct pci_dev *dev)
1626 {
1627 u32 max_port, i;
1628 int config_base;
1629
1630 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM))
1631 return -ENODEV;
1632
1633 switch (dev->device) {
1634 case 0x1204: /* 4 ports */
1635 case 0x1208: /* 8 ports */
1636 max_port = dev->device & 0xff;
1637 break;
1638 case 0x1212: /* 12 ports */
1639 max_port = 12;
1640 break;
1641 default:
1642 return -EINVAL;
1643 }
1644
1645 /* Set to mmio decode */
1646 pci_write_config_byte(dev, 0x209, 0x40);
1647
1648 for (i = 0; i < max_port; ++i) {
1649 /* UART0 configuration offset start from 0x2A0 */
1650 config_base = 0x2A0 + 0x08 * i;
1651
1652 /* Select 128-byte FIFO and 8x FIFO threshold */
1653 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1654
1655 /* Enable UART I/O port */
1656 pci_write_config_byte(dev, config_base + 0, 0x01);
1657 }
1658
1659 return max_port;
1660 }
1661
skip_tx_en_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1662 static int skip_tx_en_setup(struct serial_private *priv,
1663 const struct pciserial_board *board,
1664 struct uart_8250_port *port, int idx)
1665 {
1666 port->port.quirks |= UPQ_NO_TXEN_TEST;
1667 pci_dbg(priv->dev,
1668 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1669 priv->dev->vendor, priv->dev->device,
1670 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1671
1672 return pci_default_setup(priv, board, port, idx);
1673 }
1674
kt_handle_break(struct uart_port * p)1675 static void kt_handle_break(struct uart_port *p)
1676 {
1677 struct uart_8250_port *up = up_to_u8250p(p);
1678 /*
1679 * On receipt of a BI, serial device in Intel ME (Intel
1680 * management engine) needs to have its fifos cleared for sane
1681 * SOL (Serial Over Lan) output.
1682 */
1683 serial8250_clear_and_reinit_fifos(up);
1684 }
1685
kt_serial_in(struct uart_port * p,int offset)1686 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1687 {
1688 struct uart_8250_port *up = up_to_u8250p(p);
1689 unsigned int val;
1690
1691 /*
1692 * When the Intel ME (management engine) gets reset its serial
1693 * port registers could return 0 momentarily. Functions like
1694 * serial8250_console_write, read and save the IER, perform
1695 * some operation and then restore it. In order to avoid
1696 * setting IER register inadvertently to 0, if the value read
1697 * is 0, double check with ier value in uart_8250_port and use
1698 * that instead. up->ier should be the same value as what is
1699 * currently configured.
1700 */
1701 val = inb(p->iobase + offset);
1702 if (offset == UART_IER) {
1703 if (val == 0)
1704 val = up->ier;
1705 }
1706 return val;
1707 }
1708
kt_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1709 static int kt_serial_setup(struct serial_private *priv,
1710 const struct pciserial_board *board,
1711 struct uart_8250_port *port, int idx)
1712 {
1713 port->port.flags |= UPF_BUG_THRE;
1714 port->port.serial_in = kt_serial_in;
1715 port->port.handle_break = kt_handle_break;
1716 return skip_tx_en_setup(priv, board, port, idx);
1717 }
1718
pci_eg20t_init(struct pci_dev * dev)1719 static int pci_eg20t_init(struct pci_dev *dev)
1720 {
1721 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1722 return -ENODEV;
1723 #else
1724 return 0;
1725 #endif
1726 }
1727
1728 static int
pci_wch_ch353_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1729 pci_wch_ch353_setup(struct serial_private *priv,
1730 const struct pciserial_board *board,
1731 struct uart_8250_port *port, int idx)
1732 {
1733 port->port.flags |= UPF_FIXED_TYPE;
1734 port->port.type = PORT_16550A;
1735 return pci_default_setup(priv, board, port, idx);
1736 }
1737
1738 static int
pci_wch_ch355_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1739 pci_wch_ch355_setup(struct serial_private *priv,
1740 const struct pciserial_board *board,
1741 struct uart_8250_port *port, int idx)
1742 {
1743 port->port.flags |= UPF_FIXED_TYPE;
1744 port->port.type = PORT_16550A;
1745 return pci_default_setup(priv, board, port, idx);
1746 }
1747
1748 static int
pci_wch_ch38x_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1749 pci_wch_ch38x_setup(struct serial_private *priv,
1750 const struct pciserial_board *board,
1751 struct uart_8250_port *port, int idx)
1752 {
1753 port->port.flags |= UPF_FIXED_TYPE;
1754 port->port.type = PORT_16850;
1755 return pci_default_setup(priv, board, port, idx);
1756 }
1757
1758
1759 #define CH384_XINT_ENABLE_REG 0xEB
1760 #define CH384_XINT_ENABLE_BIT 0x02
1761
pci_wch_ch38x_init(struct pci_dev * dev)1762 static int pci_wch_ch38x_init(struct pci_dev *dev)
1763 {
1764 int max_port;
1765 unsigned long iobase;
1766
1767
1768 switch (dev->device) {
1769 case 0x3853: /* 8 ports */
1770 max_port = 8;
1771 break;
1772 default:
1773 return -EINVAL;
1774 }
1775
1776 iobase = pci_resource_start(dev, 0);
1777 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG);
1778
1779 return max_port;
1780 }
1781
pci_wch_ch38x_exit(struct pci_dev * dev)1782 static void pci_wch_ch38x_exit(struct pci_dev *dev)
1783 {
1784 unsigned long iobase;
1785
1786 iobase = pci_resource_start(dev, 0);
1787 outb(0x0, iobase + CH384_XINT_ENABLE_REG);
1788 }
1789
1790
1791 static int
pci_sunix_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1792 pci_sunix_setup(struct serial_private *priv,
1793 const struct pciserial_board *board,
1794 struct uart_8250_port *port, int idx)
1795 {
1796 int bar;
1797 int offset;
1798
1799 port->port.flags |= UPF_FIXED_TYPE;
1800 port->port.type = PORT_SUNIX;
1801
1802 if (idx < 4) {
1803 bar = 0;
1804 offset = idx * board->uart_offset;
1805 } else {
1806 bar = 1;
1807 idx -= 4;
1808 idx = div_s64_rem(idx, 4, &offset);
1809 offset = idx * 64 + offset * board->uart_offset;
1810 }
1811
1812 return setup_port(priv, port, bar, offset, 0);
1813 }
1814
1815 static int
pci_moxa_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1816 pci_moxa_setup(struct serial_private *priv,
1817 const struct pciserial_board *board,
1818 struct uart_8250_port *port, int idx)
1819 {
1820 unsigned int bar = FL_GET_BASE(board->flags);
1821 int offset;
1822
1823 if (board->num_ports == 4 && idx == 3)
1824 offset = 7 * board->uart_offset;
1825 else
1826 offset = idx * board->uart_offset;
1827
1828 return setup_port(priv, port, bar, offset, 0);
1829 }
1830
1831 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1832 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1833 #define PCI_DEVICE_ID_OCTPRO 0x0001
1834 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1835 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1836 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1837 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1838 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1839 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1840 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1841 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1842 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1843 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1844 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1845 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1846 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1847 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1848 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1849 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1850 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1851 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1852 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1853 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1854 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1855 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1856 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1857 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1858 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1859 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1860 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1861 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1862 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1863 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1864 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1865 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1866 #define PCI_VENDOR_ID_WCH 0x4348
1867 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1868 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1869 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1870 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1871 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1872 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
1873 #define PCI_VENDOR_ID_AGESTAR 0x5372
1874 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1875 #define PCI_VENDOR_ID_ASIX 0x9710
1876 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1877 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1878
1879 #define PCIE_VENDOR_ID_WCH 0x1c00
1880 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1881 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1882 #define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853
1883 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
1884
1885 #define PCI_VENDOR_ID_ACCESIO 0x494f
1886 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051
1887 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053
1888 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C
1889 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E
1890 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091
1891 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093
1892 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099
1893 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B
1894 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1
1895 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3
1896 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA
1897 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC
1898 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108
1899 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110
1900 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111
1901 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118
1902 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119
1903 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152
1904 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A
1905 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190
1906 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191
1907 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198
1908 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199
1909 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0
1910 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A
1911 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B
1912 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A
1913 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B
1914 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098
1915 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9
1916 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9
1917 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9
1918 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8
1919
1920
1921 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024
1922 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
1923 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045
1924 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144
1925 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160
1926 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161
1927 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182
1928 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183
1929 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322
1930 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342
1931 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381
1932 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683
1933
1934 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1935 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1936 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1937
1938 /*
1939 * Master list of serial port init/setup/exit quirks.
1940 * This does not describe the general nature of the port.
1941 * (ie, baud base, number and location of ports, etc)
1942 *
1943 * This list is ordered alphabetically by vendor then device.
1944 * Specific entries must come before more generic entries.
1945 */
1946 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1947 /*
1948 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1949 */
1950 {
1951 .vendor = PCI_VENDOR_ID_AMCC,
1952 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1953 .subvendor = PCI_ANY_ID,
1954 .subdevice = PCI_ANY_ID,
1955 .setup = addidata_apci7800_setup,
1956 },
1957 /*
1958 * AFAVLAB cards - these may be called via parport_serial
1959 * It is not clear whether this applies to all products.
1960 */
1961 {
1962 .vendor = PCI_VENDOR_ID_AFAVLAB,
1963 .device = PCI_ANY_ID,
1964 .subvendor = PCI_ANY_ID,
1965 .subdevice = PCI_ANY_ID,
1966 .setup = afavlab_setup,
1967 },
1968 /*
1969 * HP Diva
1970 */
1971 {
1972 .vendor = PCI_VENDOR_ID_HP,
1973 .device = PCI_DEVICE_ID_HP_DIVA,
1974 .subvendor = PCI_ANY_ID,
1975 .subdevice = PCI_ANY_ID,
1976 .init = pci_hp_diva_init,
1977 .setup = pci_hp_diva_setup,
1978 },
1979 /*
1980 * HPE PCI serial device
1981 */
1982 {
1983 .vendor = PCI_VENDOR_ID_HP_3PAR,
1984 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL,
1985 .subvendor = PCI_ANY_ID,
1986 .subdevice = PCI_ANY_ID,
1987 .setup = pci_hp_diva_setup,
1988 },
1989 /*
1990 * Intel
1991 */
1992 {
1993 .vendor = PCI_VENDOR_ID_INTEL,
1994 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1995 .subvendor = 0xe4bf,
1996 .subdevice = PCI_ANY_ID,
1997 .init = pci_inteli960ni_init,
1998 .setup = pci_default_setup,
1999 },
2000 {
2001 .vendor = PCI_VENDOR_ID_INTEL,
2002 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
2003 .subvendor = PCI_ANY_ID,
2004 .subdevice = PCI_ANY_ID,
2005 .setup = skip_tx_en_setup,
2006 },
2007 {
2008 .vendor = PCI_VENDOR_ID_INTEL,
2009 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
2010 .subvendor = PCI_ANY_ID,
2011 .subdevice = PCI_ANY_ID,
2012 .setup = skip_tx_en_setup,
2013 },
2014 {
2015 .vendor = PCI_VENDOR_ID_INTEL,
2016 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
2017 .subvendor = PCI_ANY_ID,
2018 .subdevice = PCI_ANY_ID,
2019 .setup = skip_tx_en_setup,
2020 },
2021 {
2022 .vendor = PCI_VENDOR_ID_INTEL,
2023 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2024 .subvendor = PCI_ANY_ID,
2025 .subdevice = PCI_ANY_ID,
2026 .setup = ce4100_serial_setup,
2027 },
2028 {
2029 .vendor = PCI_VENDOR_ID_INTEL,
2030 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2031 .subvendor = PCI_ANY_ID,
2032 .subdevice = PCI_ANY_ID,
2033 .setup = kt_serial_setup,
2034 },
2035 /*
2036 * ITE
2037 */
2038 {
2039 .vendor = PCI_VENDOR_ID_ITE,
2040 .device = PCI_DEVICE_ID_ITE_8872,
2041 .subvendor = PCI_ANY_ID,
2042 .subdevice = PCI_ANY_ID,
2043 .init = pci_ite887x_init,
2044 .setup = pci_default_setup,
2045 .exit = pci_ite887x_exit,
2046 },
2047 /*
2048 * National Instruments
2049 */
2050 {
2051 .vendor = PCI_VENDOR_ID_NI,
2052 .device = PCI_DEVICE_ID_NI_PCI23216,
2053 .subvendor = PCI_ANY_ID,
2054 .subdevice = PCI_ANY_ID,
2055 .init = pci_ni8420_init,
2056 .setup = pci_default_setup,
2057 .exit = pci_ni8420_exit,
2058 },
2059 {
2060 .vendor = PCI_VENDOR_ID_NI,
2061 .device = PCI_DEVICE_ID_NI_PCI2328,
2062 .subvendor = PCI_ANY_ID,
2063 .subdevice = PCI_ANY_ID,
2064 .init = pci_ni8420_init,
2065 .setup = pci_default_setup,
2066 .exit = pci_ni8420_exit,
2067 },
2068 {
2069 .vendor = PCI_VENDOR_ID_NI,
2070 .device = PCI_DEVICE_ID_NI_PCI2324,
2071 .subvendor = PCI_ANY_ID,
2072 .subdevice = PCI_ANY_ID,
2073 .init = pci_ni8420_init,
2074 .setup = pci_default_setup,
2075 .exit = pci_ni8420_exit,
2076 },
2077 {
2078 .vendor = PCI_VENDOR_ID_NI,
2079 .device = PCI_DEVICE_ID_NI_PCI2322,
2080 .subvendor = PCI_ANY_ID,
2081 .subdevice = PCI_ANY_ID,
2082 .init = pci_ni8420_init,
2083 .setup = pci_default_setup,
2084 .exit = pci_ni8420_exit,
2085 },
2086 {
2087 .vendor = PCI_VENDOR_ID_NI,
2088 .device = PCI_DEVICE_ID_NI_PCI2324I,
2089 .subvendor = PCI_ANY_ID,
2090 .subdevice = PCI_ANY_ID,
2091 .init = pci_ni8420_init,
2092 .setup = pci_default_setup,
2093 .exit = pci_ni8420_exit,
2094 },
2095 {
2096 .vendor = PCI_VENDOR_ID_NI,
2097 .device = PCI_DEVICE_ID_NI_PCI2322I,
2098 .subvendor = PCI_ANY_ID,
2099 .subdevice = PCI_ANY_ID,
2100 .init = pci_ni8420_init,
2101 .setup = pci_default_setup,
2102 .exit = pci_ni8420_exit,
2103 },
2104 {
2105 .vendor = PCI_VENDOR_ID_NI,
2106 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2107 .subvendor = PCI_ANY_ID,
2108 .subdevice = PCI_ANY_ID,
2109 .init = pci_ni8420_init,
2110 .setup = pci_default_setup,
2111 .exit = pci_ni8420_exit,
2112 },
2113 {
2114 .vendor = PCI_VENDOR_ID_NI,
2115 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2116 .subvendor = PCI_ANY_ID,
2117 .subdevice = PCI_ANY_ID,
2118 .init = pci_ni8420_init,
2119 .setup = pci_default_setup,
2120 .exit = pci_ni8420_exit,
2121 },
2122 {
2123 .vendor = PCI_VENDOR_ID_NI,
2124 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2125 .subvendor = PCI_ANY_ID,
2126 .subdevice = PCI_ANY_ID,
2127 .init = pci_ni8420_init,
2128 .setup = pci_default_setup,
2129 .exit = pci_ni8420_exit,
2130 },
2131 {
2132 .vendor = PCI_VENDOR_ID_NI,
2133 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2134 .subvendor = PCI_ANY_ID,
2135 .subdevice = PCI_ANY_ID,
2136 .init = pci_ni8420_init,
2137 .setup = pci_default_setup,
2138 .exit = pci_ni8420_exit,
2139 },
2140 {
2141 .vendor = PCI_VENDOR_ID_NI,
2142 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2143 .subvendor = PCI_ANY_ID,
2144 .subdevice = PCI_ANY_ID,
2145 .init = pci_ni8420_init,
2146 .setup = pci_default_setup,
2147 .exit = pci_ni8420_exit,
2148 },
2149 {
2150 .vendor = PCI_VENDOR_ID_NI,
2151 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2152 .subvendor = PCI_ANY_ID,
2153 .subdevice = PCI_ANY_ID,
2154 .init = pci_ni8420_init,
2155 .setup = pci_default_setup,
2156 .exit = pci_ni8420_exit,
2157 },
2158 {
2159 .vendor = PCI_VENDOR_ID_NI,
2160 .device = PCI_ANY_ID,
2161 .subvendor = PCI_ANY_ID,
2162 .subdevice = PCI_ANY_ID,
2163 .init = pci_ni8430_init,
2164 .setup = pci_ni8430_setup,
2165 .exit = pci_ni8430_exit,
2166 },
2167 /* Quatech */
2168 {
2169 .vendor = PCI_VENDOR_ID_QUATECH,
2170 .device = PCI_ANY_ID,
2171 .subvendor = PCI_ANY_ID,
2172 .subdevice = PCI_ANY_ID,
2173 .init = pci_quatech_init,
2174 .setup = pci_quatech_setup,
2175 .exit = pci_quatech_exit,
2176 },
2177 /*
2178 * Panacom
2179 */
2180 {
2181 .vendor = PCI_VENDOR_ID_PANACOM,
2182 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2183 .subvendor = PCI_ANY_ID,
2184 .subdevice = PCI_ANY_ID,
2185 .init = pci_plx9050_init,
2186 .setup = pci_default_setup,
2187 .exit = pci_plx9050_exit,
2188 },
2189 {
2190 .vendor = PCI_VENDOR_ID_PANACOM,
2191 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2192 .subvendor = PCI_ANY_ID,
2193 .subdevice = PCI_ANY_ID,
2194 .init = pci_plx9050_init,
2195 .setup = pci_default_setup,
2196 .exit = pci_plx9050_exit,
2197 },
2198 /*
2199 * Pericom (Only 7954 - It have a offset jump for port 4)
2200 */
2201 {
2202 .vendor = PCI_VENDOR_ID_PERICOM,
2203 .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954,
2204 .subvendor = PCI_ANY_ID,
2205 .subdevice = PCI_ANY_ID,
2206 .setup = pci_pericom_setup_four_at_eight,
2207 },
2208 /*
2209 * PLX
2210 */
2211 {
2212 .vendor = PCI_VENDOR_ID_PLX,
2213 .device = PCI_DEVICE_ID_PLX_9050,
2214 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2215 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2216 .init = pci_plx9050_init,
2217 .setup = pci_default_setup,
2218 .exit = pci_plx9050_exit,
2219 },
2220 {
2221 .vendor = PCI_VENDOR_ID_PLX,
2222 .device = PCI_DEVICE_ID_PLX_9050,
2223 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2224 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2225 .init = pci_plx9050_init,
2226 .setup = pci_default_setup,
2227 .exit = pci_plx9050_exit,
2228 },
2229 {
2230 .vendor = PCI_VENDOR_ID_PLX,
2231 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2232 .subvendor = PCI_VENDOR_ID_PLX,
2233 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2234 .init = pci_plx9050_init,
2235 .setup = pci_default_setup,
2236 .exit = pci_plx9050_exit,
2237 },
2238 {
2239 .vendor = PCI_VENDOR_ID_ACCESIO,
2240 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
2241 .subvendor = PCI_ANY_ID,
2242 .subdevice = PCI_ANY_ID,
2243 .setup = pci_pericom_setup_four_at_eight,
2244 },
2245 {
2246 .vendor = PCI_VENDOR_ID_ACCESIO,
2247 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
2248 .subvendor = PCI_ANY_ID,
2249 .subdevice = PCI_ANY_ID,
2250 .setup = pci_pericom_setup_four_at_eight,
2251 },
2252 {
2253 .vendor = PCI_VENDOR_ID_ACCESIO,
2254 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
2255 .subvendor = PCI_ANY_ID,
2256 .subdevice = PCI_ANY_ID,
2257 .setup = pci_pericom_setup_four_at_eight,
2258 },
2259 {
2260 .vendor = PCI_VENDOR_ID_ACCESIO,
2261 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
2262 .subvendor = PCI_ANY_ID,
2263 .subdevice = PCI_ANY_ID,
2264 .setup = pci_pericom_setup_four_at_eight,
2265 },
2266 {
2267 .vendor = PCI_VENDOR_ID_ACCESIO,
2268 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
2269 .subvendor = PCI_ANY_ID,
2270 .subdevice = PCI_ANY_ID,
2271 .setup = pci_pericom_setup_four_at_eight,
2272 },
2273 {
2274 .vendor = PCI_VENDOR_ID_ACCESIO,
2275 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
2276 .subvendor = PCI_ANY_ID,
2277 .subdevice = PCI_ANY_ID,
2278 .setup = pci_pericom_setup_four_at_eight,
2279 },
2280 {
2281 .vendor = PCI_VENDOR_ID_ACCESIO,
2282 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
2283 .subvendor = PCI_ANY_ID,
2284 .subdevice = PCI_ANY_ID,
2285 .setup = pci_pericom_setup_four_at_eight,
2286 },
2287 {
2288 .vendor = PCI_VENDOR_ID_ACCESIO,
2289 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
2290 .subvendor = PCI_ANY_ID,
2291 .subdevice = PCI_ANY_ID,
2292 .setup = pci_pericom_setup_four_at_eight,
2293 },
2294 {
2295 .vendor = PCI_VENDOR_ID_ACCESIO,
2296 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
2297 .subvendor = PCI_ANY_ID,
2298 .subdevice = PCI_ANY_ID,
2299 .setup = pci_pericom_setup_four_at_eight,
2300 },
2301 {
2302 .vendor = PCI_VENDOR_ID_ACCESIO,
2303 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
2304 .subvendor = PCI_ANY_ID,
2305 .subdevice = PCI_ANY_ID,
2306 .setup = pci_pericom_setup_four_at_eight,
2307 },
2308 {
2309 .vendor = PCI_VENDOR_ID_ACCESIO,
2310 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
2311 .subvendor = PCI_ANY_ID,
2312 .subdevice = PCI_ANY_ID,
2313 .setup = pci_pericom_setup_four_at_eight,
2314 },
2315 {
2316 .vendor = PCI_VENDOR_ID_ACCESIO,
2317 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
2318 .subvendor = PCI_ANY_ID,
2319 .subdevice = PCI_ANY_ID,
2320 .setup = pci_pericom_setup_four_at_eight,
2321 },
2322 {
2323 .vendor = PCI_VENDOR_ID_ACCESIO,
2324 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
2325 .subvendor = PCI_ANY_ID,
2326 .subdevice = PCI_ANY_ID,
2327 .setup = pci_pericom_setup_four_at_eight,
2328 },
2329 {
2330 .vendor = PCI_VENDOR_ID_ACCESIO,
2331 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
2332 .subvendor = PCI_ANY_ID,
2333 .subdevice = PCI_ANY_ID,
2334 .setup = pci_pericom_setup_four_at_eight,
2335 },
2336 {
2337 .vendor = PCI_VENDOR_ID_ACCESIO,
2338 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
2339 .subvendor = PCI_ANY_ID,
2340 .subdevice = PCI_ANY_ID,
2341 .setup = pci_pericom_setup_four_at_eight,
2342 },
2343 {
2344 .vendor = PCI_VENDOR_ID_ACCESIO,
2345 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
2346 .subvendor = PCI_ANY_ID,
2347 .subdevice = PCI_ANY_ID,
2348 .setup = pci_pericom_setup_four_at_eight,
2349 },
2350 {
2351 .vendor = PCI_VENDOR_ID_ACCESIO,
2352 .device = PCI_ANY_ID,
2353 .subvendor = PCI_ANY_ID,
2354 .subdevice = PCI_ANY_ID,
2355 .setup = pci_pericom_setup,
2356 }, /*
2357 * SBS Technologies, Inc., PMC-OCTALPRO 232
2358 */
2359 {
2360 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2361 .device = PCI_DEVICE_ID_OCTPRO,
2362 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2363 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2364 .init = sbs_init,
2365 .setup = sbs_setup,
2366 .exit = sbs_exit,
2367 },
2368 /*
2369 * SBS Technologies, Inc., PMC-OCTALPRO 422
2370 */
2371 {
2372 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2373 .device = PCI_DEVICE_ID_OCTPRO,
2374 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2375 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2376 .init = sbs_init,
2377 .setup = sbs_setup,
2378 .exit = sbs_exit,
2379 },
2380 /*
2381 * SBS Technologies, Inc., P-Octal 232
2382 */
2383 {
2384 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2385 .device = PCI_DEVICE_ID_OCTPRO,
2386 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2387 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2388 .init = sbs_init,
2389 .setup = sbs_setup,
2390 .exit = sbs_exit,
2391 },
2392 /*
2393 * SBS Technologies, Inc., P-Octal 422
2394 */
2395 {
2396 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2397 .device = PCI_DEVICE_ID_OCTPRO,
2398 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2399 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2400 .init = sbs_init,
2401 .setup = sbs_setup,
2402 .exit = sbs_exit,
2403 },
2404 /*
2405 * SIIG cards - these may be called via parport_serial
2406 */
2407 {
2408 .vendor = PCI_VENDOR_ID_SIIG,
2409 .device = PCI_ANY_ID,
2410 .subvendor = PCI_ANY_ID,
2411 .subdevice = PCI_ANY_ID,
2412 .init = pci_siig_init,
2413 .setup = pci_siig_setup,
2414 },
2415 /*
2416 * Titan cards
2417 */
2418 {
2419 .vendor = PCI_VENDOR_ID_TITAN,
2420 .device = PCI_DEVICE_ID_TITAN_400L,
2421 .subvendor = PCI_ANY_ID,
2422 .subdevice = PCI_ANY_ID,
2423 .setup = titan_400l_800l_setup,
2424 },
2425 {
2426 .vendor = PCI_VENDOR_ID_TITAN,
2427 .device = PCI_DEVICE_ID_TITAN_800L,
2428 .subvendor = PCI_ANY_ID,
2429 .subdevice = PCI_ANY_ID,
2430 .setup = titan_400l_800l_setup,
2431 },
2432 /*
2433 * Timedia cards
2434 */
2435 {
2436 .vendor = PCI_VENDOR_ID_TIMEDIA,
2437 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2438 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2439 .subdevice = PCI_ANY_ID,
2440 .probe = pci_timedia_probe,
2441 .init = pci_timedia_init,
2442 .setup = pci_timedia_setup,
2443 },
2444 {
2445 .vendor = PCI_VENDOR_ID_TIMEDIA,
2446 .device = PCI_ANY_ID,
2447 .subvendor = PCI_ANY_ID,
2448 .subdevice = PCI_ANY_ID,
2449 .setup = pci_timedia_setup,
2450 },
2451 /*
2452 * Sunix PCI serial boards
2453 */
2454 {
2455 .vendor = PCI_VENDOR_ID_SUNIX,
2456 .device = PCI_DEVICE_ID_SUNIX_1999,
2457 .subvendor = PCI_VENDOR_ID_SUNIX,
2458 .subdevice = PCI_ANY_ID,
2459 .setup = pci_sunix_setup,
2460 },
2461 /*
2462 * Xircom cards
2463 */
2464 {
2465 .vendor = PCI_VENDOR_ID_XIRCOM,
2466 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2467 .subvendor = PCI_ANY_ID,
2468 .subdevice = PCI_ANY_ID,
2469 .init = pci_xircom_init,
2470 .setup = pci_default_setup,
2471 },
2472 /*
2473 * Netmos cards - these may be called via parport_serial
2474 */
2475 {
2476 .vendor = PCI_VENDOR_ID_NETMOS,
2477 .device = PCI_ANY_ID,
2478 .subvendor = PCI_ANY_ID,
2479 .subdevice = PCI_ANY_ID,
2480 .init = pci_netmos_init,
2481 .setup = pci_netmos_9900_setup,
2482 },
2483 /*
2484 * EndRun Technologies
2485 */
2486 {
2487 .vendor = PCI_VENDOR_ID_ENDRUN,
2488 .device = PCI_ANY_ID,
2489 .subvendor = PCI_ANY_ID,
2490 .subdevice = PCI_ANY_ID,
2491 .init = pci_oxsemi_tornado_init,
2492 .setup = pci_default_setup,
2493 },
2494 /*
2495 * For Oxford Semiconductor Tornado based devices
2496 */
2497 {
2498 .vendor = PCI_VENDOR_ID_OXSEMI,
2499 .device = PCI_ANY_ID,
2500 .subvendor = PCI_ANY_ID,
2501 .subdevice = PCI_ANY_ID,
2502 .init = pci_oxsemi_tornado_init,
2503 .setup = pci_default_setup,
2504 },
2505 {
2506 .vendor = PCI_VENDOR_ID_MAINPINE,
2507 .device = PCI_ANY_ID,
2508 .subvendor = PCI_ANY_ID,
2509 .subdevice = PCI_ANY_ID,
2510 .init = pci_oxsemi_tornado_init,
2511 .setup = pci_default_setup,
2512 },
2513 {
2514 .vendor = PCI_VENDOR_ID_DIGI,
2515 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2516 .subvendor = PCI_SUBVENDOR_ID_IBM,
2517 .subdevice = PCI_ANY_ID,
2518 .init = pci_oxsemi_tornado_init,
2519 .setup = pci_default_setup,
2520 },
2521 {
2522 .vendor = PCI_VENDOR_ID_INTEL,
2523 .device = 0x8811,
2524 .subvendor = PCI_ANY_ID,
2525 .subdevice = PCI_ANY_ID,
2526 .init = pci_eg20t_init,
2527 .setup = pci_default_setup,
2528 },
2529 {
2530 .vendor = PCI_VENDOR_ID_INTEL,
2531 .device = 0x8812,
2532 .subvendor = PCI_ANY_ID,
2533 .subdevice = PCI_ANY_ID,
2534 .init = pci_eg20t_init,
2535 .setup = pci_default_setup,
2536 },
2537 {
2538 .vendor = PCI_VENDOR_ID_INTEL,
2539 .device = 0x8813,
2540 .subvendor = PCI_ANY_ID,
2541 .subdevice = PCI_ANY_ID,
2542 .init = pci_eg20t_init,
2543 .setup = pci_default_setup,
2544 },
2545 {
2546 .vendor = PCI_VENDOR_ID_INTEL,
2547 .device = 0x8814,
2548 .subvendor = PCI_ANY_ID,
2549 .subdevice = PCI_ANY_ID,
2550 .init = pci_eg20t_init,
2551 .setup = pci_default_setup,
2552 },
2553 {
2554 .vendor = 0x10DB,
2555 .device = 0x8027,
2556 .subvendor = PCI_ANY_ID,
2557 .subdevice = PCI_ANY_ID,
2558 .init = pci_eg20t_init,
2559 .setup = pci_default_setup,
2560 },
2561 {
2562 .vendor = 0x10DB,
2563 .device = 0x8028,
2564 .subvendor = PCI_ANY_ID,
2565 .subdevice = PCI_ANY_ID,
2566 .init = pci_eg20t_init,
2567 .setup = pci_default_setup,
2568 },
2569 {
2570 .vendor = 0x10DB,
2571 .device = 0x8029,
2572 .subvendor = PCI_ANY_ID,
2573 .subdevice = PCI_ANY_ID,
2574 .init = pci_eg20t_init,
2575 .setup = pci_default_setup,
2576 },
2577 {
2578 .vendor = 0x10DB,
2579 .device = 0x800C,
2580 .subvendor = PCI_ANY_ID,
2581 .subdevice = PCI_ANY_ID,
2582 .init = pci_eg20t_init,
2583 .setup = pci_default_setup,
2584 },
2585 {
2586 .vendor = 0x10DB,
2587 .device = 0x800D,
2588 .subvendor = PCI_ANY_ID,
2589 .subdevice = PCI_ANY_ID,
2590 .init = pci_eg20t_init,
2591 .setup = pci_default_setup,
2592 },
2593 /*
2594 * Cronyx Omega PCI (PLX-chip based)
2595 */
2596 {
2597 .vendor = PCI_VENDOR_ID_PLX,
2598 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2599 .subvendor = PCI_ANY_ID,
2600 .subdevice = PCI_ANY_ID,
2601 .setup = pci_omegapci_setup,
2602 },
2603 /* WCH CH353 1S1P card (16550 clone) */
2604 {
2605 .vendor = PCI_VENDOR_ID_WCH,
2606 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2607 .subvendor = PCI_ANY_ID,
2608 .subdevice = PCI_ANY_ID,
2609 .setup = pci_wch_ch353_setup,
2610 },
2611 /* WCH CH353 2S1P card (16550 clone) */
2612 {
2613 .vendor = PCI_VENDOR_ID_WCH,
2614 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2615 .subvendor = PCI_ANY_ID,
2616 .subdevice = PCI_ANY_ID,
2617 .setup = pci_wch_ch353_setup,
2618 },
2619 /* WCH CH353 4S card (16550 clone) */
2620 {
2621 .vendor = PCI_VENDOR_ID_WCH,
2622 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2623 .subvendor = PCI_ANY_ID,
2624 .subdevice = PCI_ANY_ID,
2625 .setup = pci_wch_ch353_setup,
2626 },
2627 /* WCH CH353 2S1PF card (16550 clone) */
2628 {
2629 .vendor = PCI_VENDOR_ID_WCH,
2630 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2631 .subvendor = PCI_ANY_ID,
2632 .subdevice = PCI_ANY_ID,
2633 .setup = pci_wch_ch353_setup,
2634 },
2635 /* WCH CH352 2S card (16550 clone) */
2636 {
2637 .vendor = PCI_VENDOR_ID_WCH,
2638 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2639 .subvendor = PCI_ANY_ID,
2640 .subdevice = PCI_ANY_ID,
2641 .setup = pci_wch_ch353_setup,
2642 },
2643 /* WCH CH355 4S card (16550 clone) */
2644 {
2645 .vendor = PCI_VENDOR_ID_WCH,
2646 .device = PCI_DEVICE_ID_WCH_CH355_4S,
2647 .subvendor = PCI_ANY_ID,
2648 .subdevice = PCI_ANY_ID,
2649 .setup = pci_wch_ch355_setup,
2650 },
2651 /* WCH CH382 2S card (16850 clone) */
2652 {
2653 .vendor = PCIE_VENDOR_ID_WCH,
2654 .device = PCIE_DEVICE_ID_WCH_CH382_2S,
2655 .subvendor = PCI_ANY_ID,
2656 .subdevice = PCI_ANY_ID,
2657 .setup = pci_wch_ch38x_setup,
2658 },
2659 /* WCH CH382 2S1P card (16850 clone) */
2660 {
2661 .vendor = PCIE_VENDOR_ID_WCH,
2662 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2663 .subvendor = PCI_ANY_ID,
2664 .subdevice = PCI_ANY_ID,
2665 .setup = pci_wch_ch38x_setup,
2666 },
2667 /* WCH CH384 4S card (16850 clone) */
2668 {
2669 .vendor = PCIE_VENDOR_ID_WCH,
2670 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2671 .subvendor = PCI_ANY_ID,
2672 .subdevice = PCI_ANY_ID,
2673 .setup = pci_wch_ch38x_setup,
2674 },
2675 /* WCH CH384 8S card (16850 clone) */
2676 {
2677 .vendor = PCIE_VENDOR_ID_WCH,
2678 .device = PCIE_DEVICE_ID_WCH_CH384_8S,
2679 .subvendor = PCI_ANY_ID,
2680 .subdevice = PCI_ANY_ID,
2681 .init = pci_wch_ch38x_init,
2682 .exit = pci_wch_ch38x_exit,
2683 .setup = pci_wch_ch38x_setup,
2684 },
2685 /*
2686 * ASIX devices with FIFO bug
2687 */
2688 {
2689 .vendor = PCI_VENDOR_ID_ASIX,
2690 .device = PCI_ANY_ID,
2691 .subvendor = PCI_ANY_ID,
2692 .subdevice = PCI_ANY_ID,
2693 .setup = pci_asix_setup,
2694 },
2695 /*
2696 * Broadcom TruManage (NetXtreme)
2697 */
2698 {
2699 .vendor = PCI_VENDOR_ID_BROADCOM,
2700 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2701 .subvendor = PCI_ANY_ID,
2702 .subdevice = PCI_ANY_ID,
2703 .setup = pci_brcm_trumanage_setup,
2704 },
2705 {
2706 .vendor = 0x1c29,
2707 .device = 0x1104,
2708 .subvendor = PCI_ANY_ID,
2709 .subdevice = PCI_ANY_ID,
2710 .setup = pci_fintek_setup,
2711 .init = pci_fintek_init,
2712 },
2713 {
2714 .vendor = 0x1c29,
2715 .device = 0x1108,
2716 .subvendor = PCI_ANY_ID,
2717 .subdevice = PCI_ANY_ID,
2718 .setup = pci_fintek_setup,
2719 .init = pci_fintek_init,
2720 },
2721 {
2722 .vendor = 0x1c29,
2723 .device = 0x1112,
2724 .subvendor = PCI_ANY_ID,
2725 .subdevice = PCI_ANY_ID,
2726 .setup = pci_fintek_setup,
2727 .init = pci_fintek_init,
2728 },
2729 /*
2730 * MOXA
2731 */
2732 {
2733 .vendor = PCI_VENDOR_ID_MOXA,
2734 .device = PCI_ANY_ID,
2735 .subvendor = PCI_ANY_ID,
2736 .subdevice = PCI_ANY_ID,
2737 .setup = pci_moxa_setup,
2738 },
2739 {
2740 .vendor = 0x1c29,
2741 .device = 0x1204,
2742 .subvendor = PCI_ANY_ID,
2743 .subdevice = PCI_ANY_ID,
2744 .setup = pci_fintek_f815xxa_setup,
2745 .init = pci_fintek_f815xxa_init,
2746 },
2747 {
2748 .vendor = 0x1c29,
2749 .device = 0x1208,
2750 .subvendor = PCI_ANY_ID,
2751 .subdevice = PCI_ANY_ID,
2752 .setup = pci_fintek_f815xxa_setup,
2753 .init = pci_fintek_f815xxa_init,
2754 },
2755 {
2756 .vendor = 0x1c29,
2757 .device = 0x1212,
2758 .subvendor = PCI_ANY_ID,
2759 .subdevice = PCI_ANY_ID,
2760 .setup = pci_fintek_f815xxa_setup,
2761 .init = pci_fintek_f815xxa_init,
2762 },
2763
2764 /*
2765 * Default "match everything" terminator entry
2766 */
2767 {
2768 .vendor = PCI_ANY_ID,
2769 .device = PCI_ANY_ID,
2770 .subvendor = PCI_ANY_ID,
2771 .subdevice = PCI_ANY_ID,
2772 .setup = pci_default_setup,
2773 }
2774 };
2775
quirk_id_matches(u32 quirk_id,u32 dev_id)2776 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2777 {
2778 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2779 }
2780
find_quirk(struct pci_dev * dev)2781 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2782 {
2783 struct pci_serial_quirk *quirk;
2784
2785 for (quirk = pci_serial_quirks; ; quirk++)
2786 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2787 quirk_id_matches(quirk->device, dev->device) &&
2788 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2789 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2790 break;
2791 return quirk;
2792 }
2793
2794 /*
2795 * This is the configuration table for all of the PCI serial boards
2796 * which we support. It is directly indexed by the pci_board_num_t enum
2797 * value, which is encoded in the pci_device_id PCI probe table's
2798 * driver_data member.
2799 *
2800 * The makeup of these names are:
2801 * pbn_bn{_bt}_n_baud{_offsetinhex}
2802 *
2803 * bn = PCI BAR number
2804 * bt = Index using PCI BARs
2805 * n = number of serial ports
2806 * baud = baud rate
2807 * offsetinhex = offset for each sequential port (in hex)
2808 *
2809 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2810 *
2811 * Please note: in theory if n = 1, _bt infix should make no difference.
2812 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2813 */
2814 enum pci_board_num_t {
2815 pbn_default = 0,
2816
2817 pbn_b0_1_115200,
2818 pbn_b0_2_115200,
2819 pbn_b0_4_115200,
2820 pbn_b0_5_115200,
2821 pbn_b0_8_115200,
2822
2823 pbn_b0_1_921600,
2824 pbn_b0_2_921600,
2825 pbn_b0_4_921600,
2826
2827 pbn_b0_2_1130000,
2828
2829 pbn_b0_4_1152000,
2830
2831 pbn_b0_4_1250000,
2832
2833 pbn_b0_2_1843200,
2834 pbn_b0_4_1843200,
2835
2836 pbn_b0_1_3906250,
2837
2838 pbn_b0_bt_1_115200,
2839 pbn_b0_bt_2_115200,
2840 pbn_b0_bt_4_115200,
2841 pbn_b0_bt_8_115200,
2842
2843 pbn_b0_bt_1_460800,
2844 pbn_b0_bt_2_460800,
2845 pbn_b0_bt_4_460800,
2846
2847 pbn_b0_bt_1_921600,
2848 pbn_b0_bt_2_921600,
2849 pbn_b0_bt_4_921600,
2850 pbn_b0_bt_8_921600,
2851
2852 pbn_b1_1_115200,
2853 pbn_b1_2_115200,
2854 pbn_b1_4_115200,
2855 pbn_b1_8_115200,
2856 pbn_b1_16_115200,
2857
2858 pbn_b1_1_921600,
2859 pbn_b1_2_921600,
2860 pbn_b1_4_921600,
2861 pbn_b1_8_921600,
2862
2863 pbn_b1_2_1250000,
2864
2865 pbn_b1_bt_1_115200,
2866 pbn_b1_bt_2_115200,
2867 pbn_b1_bt_4_115200,
2868
2869 pbn_b1_bt_2_921600,
2870
2871 pbn_b1_1_1382400,
2872 pbn_b1_2_1382400,
2873 pbn_b1_4_1382400,
2874 pbn_b1_8_1382400,
2875
2876 pbn_b2_1_115200,
2877 pbn_b2_2_115200,
2878 pbn_b2_4_115200,
2879 pbn_b2_8_115200,
2880
2881 pbn_b2_1_460800,
2882 pbn_b2_4_460800,
2883 pbn_b2_8_460800,
2884 pbn_b2_16_460800,
2885
2886 pbn_b2_1_921600,
2887 pbn_b2_4_921600,
2888 pbn_b2_8_921600,
2889
2890 pbn_b2_8_1152000,
2891
2892 pbn_b2_bt_1_115200,
2893 pbn_b2_bt_2_115200,
2894 pbn_b2_bt_4_115200,
2895
2896 pbn_b2_bt_2_921600,
2897 pbn_b2_bt_4_921600,
2898
2899 pbn_b3_2_115200,
2900 pbn_b3_4_115200,
2901 pbn_b3_8_115200,
2902
2903 pbn_b4_bt_2_921600,
2904 pbn_b4_bt_4_921600,
2905 pbn_b4_bt_8_921600,
2906
2907 /*
2908 * Board-specific versions.
2909 */
2910 pbn_panacom,
2911 pbn_panacom2,
2912 pbn_panacom4,
2913 pbn_plx_romulus,
2914 pbn_oxsemi,
2915 pbn_oxsemi_1_3906250,
2916 pbn_oxsemi_2_3906250,
2917 pbn_oxsemi_4_3906250,
2918 pbn_oxsemi_8_3906250,
2919 pbn_intel_i960,
2920 pbn_sgi_ioc3,
2921 pbn_computone_4,
2922 pbn_computone_6,
2923 pbn_computone_8,
2924 pbn_sbsxrsio,
2925 pbn_pasemi_1682M,
2926 pbn_ni8430_2,
2927 pbn_ni8430_4,
2928 pbn_ni8430_8,
2929 pbn_ni8430_16,
2930 pbn_ADDIDATA_PCIe_1_3906250,
2931 pbn_ADDIDATA_PCIe_2_3906250,
2932 pbn_ADDIDATA_PCIe_4_3906250,
2933 pbn_ADDIDATA_PCIe_8_3906250,
2934 pbn_ce4100_1_115200,
2935 pbn_omegapci,
2936 pbn_NETMOS9900_2s_115200,
2937 pbn_brcm_trumanage,
2938 pbn_fintek_4,
2939 pbn_fintek_8,
2940 pbn_fintek_12,
2941 pbn_fintek_F81504A,
2942 pbn_fintek_F81508A,
2943 pbn_fintek_F81512A,
2944 pbn_wch382_2,
2945 pbn_wch384_4,
2946 pbn_wch384_8,
2947 pbn_pericom_PI7C9X7951,
2948 pbn_pericom_PI7C9X7952,
2949 pbn_pericom_PI7C9X7954,
2950 pbn_pericom_PI7C9X7958,
2951 pbn_sunix_pci_1s,
2952 pbn_sunix_pci_2s,
2953 pbn_sunix_pci_4s,
2954 pbn_sunix_pci_8s,
2955 pbn_sunix_pci_16s,
2956 pbn_titan_1_4000000,
2957 pbn_titan_2_4000000,
2958 pbn_titan_4_4000000,
2959 pbn_titan_8_4000000,
2960 pbn_moxa8250_2p,
2961 pbn_moxa8250_4p,
2962 pbn_moxa8250_8p,
2963 };
2964
2965 /*
2966 * uart_offset - the space between channels
2967 * reg_shift - describes how the UART registers are mapped
2968 * to PCI memory by the card.
2969 * For example IER register on SBS, Inc. PMC-OctPro is located at
2970 * offset 0x10 from the UART base, while UART_IER is defined as 1
2971 * in include/linux/serial_reg.h,
2972 * see first lines of serial_in() and serial_out() in 8250.c
2973 */
2974
2975 static struct pciserial_board pci_boards[] = {
2976 [pbn_default] = {
2977 .flags = FL_BASE0,
2978 .num_ports = 1,
2979 .base_baud = 115200,
2980 .uart_offset = 8,
2981 },
2982 [pbn_b0_1_115200] = {
2983 .flags = FL_BASE0,
2984 .num_ports = 1,
2985 .base_baud = 115200,
2986 .uart_offset = 8,
2987 },
2988 [pbn_b0_2_115200] = {
2989 .flags = FL_BASE0,
2990 .num_ports = 2,
2991 .base_baud = 115200,
2992 .uart_offset = 8,
2993 },
2994 [pbn_b0_4_115200] = {
2995 .flags = FL_BASE0,
2996 .num_ports = 4,
2997 .base_baud = 115200,
2998 .uart_offset = 8,
2999 },
3000 [pbn_b0_5_115200] = {
3001 .flags = FL_BASE0,
3002 .num_ports = 5,
3003 .base_baud = 115200,
3004 .uart_offset = 8,
3005 },
3006 [pbn_b0_8_115200] = {
3007 .flags = FL_BASE0,
3008 .num_ports = 8,
3009 .base_baud = 115200,
3010 .uart_offset = 8,
3011 },
3012 [pbn_b0_1_921600] = {
3013 .flags = FL_BASE0,
3014 .num_ports = 1,
3015 .base_baud = 921600,
3016 .uart_offset = 8,
3017 },
3018 [pbn_b0_2_921600] = {
3019 .flags = FL_BASE0,
3020 .num_ports = 2,
3021 .base_baud = 921600,
3022 .uart_offset = 8,
3023 },
3024 [pbn_b0_4_921600] = {
3025 .flags = FL_BASE0,
3026 .num_ports = 4,
3027 .base_baud = 921600,
3028 .uart_offset = 8,
3029 },
3030
3031 [pbn_b0_2_1130000] = {
3032 .flags = FL_BASE0,
3033 .num_ports = 2,
3034 .base_baud = 1130000,
3035 .uart_offset = 8,
3036 },
3037
3038 [pbn_b0_4_1152000] = {
3039 .flags = FL_BASE0,
3040 .num_ports = 4,
3041 .base_baud = 1152000,
3042 .uart_offset = 8,
3043 },
3044
3045 [pbn_b0_4_1250000] = {
3046 .flags = FL_BASE0,
3047 .num_ports = 4,
3048 .base_baud = 1250000,
3049 .uart_offset = 8,
3050 },
3051
3052 [pbn_b0_2_1843200] = {
3053 .flags = FL_BASE0,
3054 .num_ports = 2,
3055 .base_baud = 1843200,
3056 .uart_offset = 8,
3057 },
3058 [pbn_b0_4_1843200] = {
3059 .flags = FL_BASE0,
3060 .num_ports = 4,
3061 .base_baud = 1843200,
3062 .uart_offset = 8,
3063 },
3064
3065 [pbn_b0_1_3906250] = {
3066 .flags = FL_BASE0,
3067 .num_ports = 1,
3068 .base_baud = 3906250,
3069 .uart_offset = 8,
3070 },
3071
3072 [pbn_b0_bt_1_115200] = {
3073 .flags = FL_BASE0|FL_BASE_BARS,
3074 .num_ports = 1,
3075 .base_baud = 115200,
3076 .uart_offset = 8,
3077 },
3078 [pbn_b0_bt_2_115200] = {
3079 .flags = FL_BASE0|FL_BASE_BARS,
3080 .num_ports = 2,
3081 .base_baud = 115200,
3082 .uart_offset = 8,
3083 },
3084 [pbn_b0_bt_4_115200] = {
3085 .flags = FL_BASE0|FL_BASE_BARS,
3086 .num_ports = 4,
3087 .base_baud = 115200,
3088 .uart_offset = 8,
3089 },
3090 [pbn_b0_bt_8_115200] = {
3091 .flags = FL_BASE0|FL_BASE_BARS,
3092 .num_ports = 8,
3093 .base_baud = 115200,
3094 .uart_offset = 8,
3095 },
3096
3097 [pbn_b0_bt_1_460800] = {
3098 .flags = FL_BASE0|FL_BASE_BARS,
3099 .num_ports = 1,
3100 .base_baud = 460800,
3101 .uart_offset = 8,
3102 },
3103 [pbn_b0_bt_2_460800] = {
3104 .flags = FL_BASE0|FL_BASE_BARS,
3105 .num_ports = 2,
3106 .base_baud = 460800,
3107 .uart_offset = 8,
3108 },
3109 [pbn_b0_bt_4_460800] = {
3110 .flags = FL_BASE0|FL_BASE_BARS,
3111 .num_ports = 4,
3112 .base_baud = 460800,
3113 .uart_offset = 8,
3114 },
3115
3116 [pbn_b0_bt_1_921600] = {
3117 .flags = FL_BASE0|FL_BASE_BARS,
3118 .num_ports = 1,
3119 .base_baud = 921600,
3120 .uart_offset = 8,
3121 },
3122 [pbn_b0_bt_2_921600] = {
3123 .flags = FL_BASE0|FL_BASE_BARS,
3124 .num_ports = 2,
3125 .base_baud = 921600,
3126 .uart_offset = 8,
3127 },
3128 [pbn_b0_bt_4_921600] = {
3129 .flags = FL_BASE0|FL_BASE_BARS,
3130 .num_ports = 4,
3131 .base_baud = 921600,
3132 .uart_offset = 8,
3133 },
3134 [pbn_b0_bt_8_921600] = {
3135 .flags = FL_BASE0|FL_BASE_BARS,
3136 .num_ports = 8,
3137 .base_baud = 921600,
3138 .uart_offset = 8,
3139 },
3140
3141 [pbn_b1_1_115200] = {
3142 .flags = FL_BASE1,
3143 .num_ports = 1,
3144 .base_baud = 115200,
3145 .uart_offset = 8,
3146 },
3147 [pbn_b1_2_115200] = {
3148 .flags = FL_BASE1,
3149 .num_ports = 2,
3150 .base_baud = 115200,
3151 .uart_offset = 8,
3152 },
3153 [pbn_b1_4_115200] = {
3154 .flags = FL_BASE1,
3155 .num_ports = 4,
3156 .base_baud = 115200,
3157 .uart_offset = 8,
3158 },
3159 [pbn_b1_8_115200] = {
3160 .flags = FL_BASE1,
3161 .num_ports = 8,
3162 .base_baud = 115200,
3163 .uart_offset = 8,
3164 },
3165 [pbn_b1_16_115200] = {
3166 .flags = FL_BASE1,
3167 .num_ports = 16,
3168 .base_baud = 115200,
3169 .uart_offset = 8,
3170 },
3171
3172 [pbn_b1_1_921600] = {
3173 .flags = FL_BASE1,
3174 .num_ports = 1,
3175 .base_baud = 921600,
3176 .uart_offset = 8,
3177 },
3178 [pbn_b1_2_921600] = {
3179 .flags = FL_BASE1,
3180 .num_ports = 2,
3181 .base_baud = 921600,
3182 .uart_offset = 8,
3183 },
3184 [pbn_b1_4_921600] = {
3185 .flags = FL_BASE1,
3186 .num_ports = 4,
3187 .base_baud = 921600,
3188 .uart_offset = 8,
3189 },
3190 [pbn_b1_8_921600] = {
3191 .flags = FL_BASE1,
3192 .num_ports = 8,
3193 .base_baud = 921600,
3194 .uart_offset = 8,
3195 },
3196 [pbn_b1_2_1250000] = {
3197 .flags = FL_BASE1,
3198 .num_ports = 2,
3199 .base_baud = 1250000,
3200 .uart_offset = 8,
3201 },
3202
3203 [pbn_b1_bt_1_115200] = {
3204 .flags = FL_BASE1|FL_BASE_BARS,
3205 .num_ports = 1,
3206 .base_baud = 115200,
3207 .uart_offset = 8,
3208 },
3209 [pbn_b1_bt_2_115200] = {
3210 .flags = FL_BASE1|FL_BASE_BARS,
3211 .num_ports = 2,
3212 .base_baud = 115200,
3213 .uart_offset = 8,
3214 },
3215 [pbn_b1_bt_4_115200] = {
3216 .flags = FL_BASE1|FL_BASE_BARS,
3217 .num_ports = 4,
3218 .base_baud = 115200,
3219 .uart_offset = 8,
3220 },
3221
3222 [pbn_b1_bt_2_921600] = {
3223 .flags = FL_BASE1|FL_BASE_BARS,
3224 .num_ports = 2,
3225 .base_baud = 921600,
3226 .uart_offset = 8,
3227 },
3228
3229 [pbn_b1_1_1382400] = {
3230 .flags = FL_BASE1,
3231 .num_ports = 1,
3232 .base_baud = 1382400,
3233 .uart_offset = 8,
3234 },
3235 [pbn_b1_2_1382400] = {
3236 .flags = FL_BASE1,
3237 .num_ports = 2,
3238 .base_baud = 1382400,
3239 .uart_offset = 8,
3240 },
3241 [pbn_b1_4_1382400] = {
3242 .flags = FL_BASE1,
3243 .num_ports = 4,
3244 .base_baud = 1382400,
3245 .uart_offset = 8,
3246 },
3247 [pbn_b1_8_1382400] = {
3248 .flags = FL_BASE1,
3249 .num_ports = 8,
3250 .base_baud = 1382400,
3251 .uart_offset = 8,
3252 },
3253
3254 [pbn_b2_1_115200] = {
3255 .flags = FL_BASE2,
3256 .num_ports = 1,
3257 .base_baud = 115200,
3258 .uart_offset = 8,
3259 },
3260 [pbn_b2_2_115200] = {
3261 .flags = FL_BASE2,
3262 .num_ports = 2,
3263 .base_baud = 115200,
3264 .uart_offset = 8,
3265 },
3266 [pbn_b2_4_115200] = {
3267 .flags = FL_BASE2,
3268 .num_ports = 4,
3269 .base_baud = 115200,
3270 .uart_offset = 8,
3271 },
3272 [pbn_b2_8_115200] = {
3273 .flags = FL_BASE2,
3274 .num_ports = 8,
3275 .base_baud = 115200,
3276 .uart_offset = 8,
3277 },
3278
3279 [pbn_b2_1_460800] = {
3280 .flags = FL_BASE2,
3281 .num_ports = 1,
3282 .base_baud = 460800,
3283 .uart_offset = 8,
3284 },
3285 [pbn_b2_4_460800] = {
3286 .flags = FL_BASE2,
3287 .num_ports = 4,
3288 .base_baud = 460800,
3289 .uart_offset = 8,
3290 },
3291 [pbn_b2_8_460800] = {
3292 .flags = FL_BASE2,
3293 .num_ports = 8,
3294 .base_baud = 460800,
3295 .uart_offset = 8,
3296 },
3297 [pbn_b2_16_460800] = {
3298 .flags = FL_BASE2,
3299 .num_ports = 16,
3300 .base_baud = 460800,
3301 .uart_offset = 8,
3302 },
3303
3304 [pbn_b2_1_921600] = {
3305 .flags = FL_BASE2,
3306 .num_ports = 1,
3307 .base_baud = 921600,
3308 .uart_offset = 8,
3309 },
3310 [pbn_b2_4_921600] = {
3311 .flags = FL_BASE2,
3312 .num_ports = 4,
3313 .base_baud = 921600,
3314 .uart_offset = 8,
3315 },
3316 [pbn_b2_8_921600] = {
3317 .flags = FL_BASE2,
3318 .num_ports = 8,
3319 .base_baud = 921600,
3320 .uart_offset = 8,
3321 },
3322
3323 [pbn_b2_8_1152000] = {
3324 .flags = FL_BASE2,
3325 .num_ports = 8,
3326 .base_baud = 1152000,
3327 .uart_offset = 8,
3328 },
3329
3330 [pbn_b2_bt_1_115200] = {
3331 .flags = FL_BASE2|FL_BASE_BARS,
3332 .num_ports = 1,
3333 .base_baud = 115200,
3334 .uart_offset = 8,
3335 },
3336 [pbn_b2_bt_2_115200] = {
3337 .flags = FL_BASE2|FL_BASE_BARS,
3338 .num_ports = 2,
3339 .base_baud = 115200,
3340 .uart_offset = 8,
3341 },
3342 [pbn_b2_bt_4_115200] = {
3343 .flags = FL_BASE2|FL_BASE_BARS,
3344 .num_ports = 4,
3345 .base_baud = 115200,
3346 .uart_offset = 8,
3347 },
3348
3349 [pbn_b2_bt_2_921600] = {
3350 .flags = FL_BASE2|FL_BASE_BARS,
3351 .num_ports = 2,
3352 .base_baud = 921600,
3353 .uart_offset = 8,
3354 },
3355 [pbn_b2_bt_4_921600] = {
3356 .flags = FL_BASE2|FL_BASE_BARS,
3357 .num_ports = 4,
3358 .base_baud = 921600,
3359 .uart_offset = 8,
3360 },
3361
3362 [pbn_b3_2_115200] = {
3363 .flags = FL_BASE3,
3364 .num_ports = 2,
3365 .base_baud = 115200,
3366 .uart_offset = 8,
3367 },
3368 [pbn_b3_4_115200] = {
3369 .flags = FL_BASE3,
3370 .num_ports = 4,
3371 .base_baud = 115200,
3372 .uart_offset = 8,
3373 },
3374 [pbn_b3_8_115200] = {
3375 .flags = FL_BASE3,
3376 .num_ports = 8,
3377 .base_baud = 115200,
3378 .uart_offset = 8,
3379 },
3380
3381 [pbn_b4_bt_2_921600] = {
3382 .flags = FL_BASE4,
3383 .num_ports = 2,
3384 .base_baud = 921600,
3385 .uart_offset = 8,
3386 },
3387 [pbn_b4_bt_4_921600] = {
3388 .flags = FL_BASE4,
3389 .num_ports = 4,
3390 .base_baud = 921600,
3391 .uart_offset = 8,
3392 },
3393 [pbn_b4_bt_8_921600] = {
3394 .flags = FL_BASE4,
3395 .num_ports = 8,
3396 .base_baud = 921600,
3397 .uart_offset = 8,
3398 },
3399
3400 /*
3401 * Entries following this are board-specific.
3402 */
3403
3404 /*
3405 * Panacom - IOMEM
3406 */
3407 [pbn_panacom] = {
3408 .flags = FL_BASE2,
3409 .num_ports = 2,
3410 .base_baud = 921600,
3411 .uart_offset = 0x400,
3412 .reg_shift = 7,
3413 },
3414 [pbn_panacom2] = {
3415 .flags = FL_BASE2|FL_BASE_BARS,
3416 .num_ports = 2,
3417 .base_baud = 921600,
3418 .uart_offset = 0x400,
3419 .reg_shift = 7,
3420 },
3421 [pbn_panacom4] = {
3422 .flags = FL_BASE2|FL_BASE_BARS,
3423 .num_ports = 4,
3424 .base_baud = 921600,
3425 .uart_offset = 0x400,
3426 .reg_shift = 7,
3427 },
3428
3429 /* I think this entry is broken - the first_offset looks wrong --rmk */
3430 [pbn_plx_romulus] = {
3431 .flags = FL_BASE2,
3432 .num_ports = 4,
3433 .base_baud = 921600,
3434 .uart_offset = 8 << 2,
3435 .reg_shift = 2,
3436 .first_offset = 0x03,
3437 },
3438
3439 /*
3440 * This board uses the size of PCI Base region 0 to
3441 * signal now many ports are available
3442 */
3443 [pbn_oxsemi] = {
3444 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3445 .num_ports = 32,
3446 .base_baud = 115200,
3447 .uart_offset = 8,
3448 },
3449 [pbn_oxsemi_1_3906250] = {
3450 .flags = FL_BASE0,
3451 .num_ports = 1,
3452 .base_baud = 3906250,
3453 .uart_offset = 0x200,
3454 .first_offset = 0x1000,
3455 },
3456 [pbn_oxsemi_2_3906250] = {
3457 .flags = FL_BASE0,
3458 .num_ports = 2,
3459 .base_baud = 3906250,
3460 .uart_offset = 0x200,
3461 .first_offset = 0x1000,
3462 },
3463 [pbn_oxsemi_4_3906250] = {
3464 .flags = FL_BASE0,
3465 .num_ports = 4,
3466 .base_baud = 3906250,
3467 .uart_offset = 0x200,
3468 .first_offset = 0x1000,
3469 },
3470 [pbn_oxsemi_8_3906250] = {
3471 .flags = FL_BASE0,
3472 .num_ports = 8,
3473 .base_baud = 3906250,
3474 .uart_offset = 0x200,
3475 .first_offset = 0x1000,
3476 },
3477
3478
3479 /*
3480 * EKF addition for i960 Boards form EKF with serial port.
3481 * Max 256 ports.
3482 */
3483 [pbn_intel_i960] = {
3484 .flags = FL_BASE0,
3485 .num_ports = 32,
3486 .base_baud = 921600,
3487 .uart_offset = 8 << 2,
3488 .reg_shift = 2,
3489 .first_offset = 0x10000,
3490 },
3491 [pbn_sgi_ioc3] = {
3492 .flags = FL_BASE0|FL_NOIRQ,
3493 .num_ports = 1,
3494 .base_baud = 458333,
3495 .uart_offset = 8,
3496 .reg_shift = 0,
3497 .first_offset = 0x20178,
3498 },
3499
3500 /*
3501 * Computone - uses IOMEM.
3502 */
3503 [pbn_computone_4] = {
3504 .flags = FL_BASE0,
3505 .num_ports = 4,
3506 .base_baud = 921600,
3507 .uart_offset = 0x40,
3508 .reg_shift = 2,
3509 .first_offset = 0x200,
3510 },
3511 [pbn_computone_6] = {
3512 .flags = FL_BASE0,
3513 .num_ports = 6,
3514 .base_baud = 921600,
3515 .uart_offset = 0x40,
3516 .reg_shift = 2,
3517 .first_offset = 0x200,
3518 },
3519 [pbn_computone_8] = {
3520 .flags = FL_BASE0,
3521 .num_ports = 8,
3522 .base_baud = 921600,
3523 .uart_offset = 0x40,
3524 .reg_shift = 2,
3525 .first_offset = 0x200,
3526 },
3527 [pbn_sbsxrsio] = {
3528 .flags = FL_BASE0,
3529 .num_ports = 8,
3530 .base_baud = 460800,
3531 .uart_offset = 256,
3532 .reg_shift = 4,
3533 },
3534 /*
3535 * PA Semi PWRficient PA6T-1682M on-chip UART
3536 */
3537 [pbn_pasemi_1682M] = {
3538 .flags = FL_BASE0,
3539 .num_ports = 1,
3540 .base_baud = 8333333,
3541 },
3542 /*
3543 * National Instruments 843x
3544 */
3545 [pbn_ni8430_16] = {
3546 .flags = FL_BASE0,
3547 .num_ports = 16,
3548 .base_baud = 3686400,
3549 .uart_offset = 0x10,
3550 .first_offset = 0x800,
3551 },
3552 [pbn_ni8430_8] = {
3553 .flags = FL_BASE0,
3554 .num_ports = 8,
3555 .base_baud = 3686400,
3556 .uart_offset = 0x10,
3557 .first_offset = 0x800,
3558 },
3559 [pbn_ni8430_4] = {
3560 .flags = FL_BASE0,
3561 .num_ports = 4,
3562 .base_baud = 3686400,
3563 .uart_offset = 0x10,
3564 .first_offset = 0x800,
3565 },
3566 [pbn_ni8430_2] = {
3567 .flags = FL_BASE0,
3568 .num_ports = 2,
3569 .base_baud = 3686400,
3570 .uart_offset = 0x10,
3571 .first_offset = 0x800,
3572 },
3573 /*
3574 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3575 */
3576 [pbn_ADDIDATA_PCIe_1_3906250] = {
3577 .flags = FL_BASE0,
3578 .num_ports = 1,
3579 .base_baud = 3906250,
3580 .uart_offset = 0x200,
3581 .first_offset = 0x1000,
3582 },
3583 [pbn_ADDIDATA_PCIe_2_3906250] = {
3584 .flags = FL_BASE0,
3585 .num_ports = 2,
3586 .base_baud = 3906250,
3587 .uart_offset = 0x200,
3588 .first_offset = 0x1000,
3589 },
3590 [pbn_ADDIDATA_PCIe_4_3906250] = {
3591 .flags = FL_BASE0,
3592 .num_ports = 4,
3593 .base_baud = 3906250,
3594 .uart_offset = 0x200,
3595 .first_offset = 0x1000,
3596 },
3597 [pbn_ADDIDATA_PCIe_8_3906250] = {
3598 .flags = FL_BASE0,
3599 .num_ports = 8,
3600 .base_baud = 3906250,
3601 .uart_offset = 0x200,
3602 .first_offset = 0x1000,
3603 },
3604 [pbn_ce4100_1_115200] = {
3605 .flags = FL_BASE_BARS,
3606 .num_ports = 2,
3607 .base_baud = 921600,
3608 .reg_shift = 2,
3609 },
3610 [pbn_omegapci] = {
3611 .flags = FL_BASE0,
3612 .num_ports = 8,
3613 .base_baud = 115200,
3614 .uart_offset = 0x200,
3615 },
3616 [pbn_NETMOS9900_2s_115200] = {
3617 .flags = FL_BASE0,
3618 .num_ports = 2,
3619 .base_baud = 115200,
3620 },
3621 [pbn_brcm_trumanage] = {
3622 .flags = FL_BASE0,
3623 .num_ports = 1,
3624 .reg_shift = 2,
3625 .base_baud = 115200,
3626 },
3627 [pbn_fintek_4] = {
3628 .num_ports = 4,
3629 .uart_offset = 8,
3630 .base_baud = 115200,
3631 .first_offset = 0x40,
3632 },
3633 [pbn_fintek_8] = {
3634 .num_ports = 8,
3635 .uart_offset = 8,
3636 .base_baud = 115200,
3637 .first_offset = 0x40,
3638 },
3639 [pbn_fintek_12] = {
3640 .num_ports = 12,
3641 .uart_offset = 8,
3642 .base_baud = 115200,
3643 .first_offset = 0x40,
3644 },
3645 [pbn_fintek_F81504A] = {
3646 .num_ports = 4,
3647 .uart_offset = 8,
3648 .base_baud = 115200,
3649 },
3650 [pbn_fintek_F81508A] = {
3651 .num_ports = 8,
3652 .uart_offset = 8,
3653 .base_baud = 115200,
3654 },
3655 [pbn_fintek_F81512A] = {
3656 .num_ports = 12,
3657 .uart_offset = 8,
3658 .base_baud = 115200,
3659 },
3660 [pbn_wch382_2] = {
3661 .flags = FL_BASE0,
3662 .num_ports = 2,
3663 .base_baud = 115200,
3664 .uart_offset = 8,
3665 .first_offset = 0xC0,
3666 },
3667 [pbn_wch384_4] = {
3668 .flags = FL_BASE0,
3669 .num_ports = 4,
3670 .base_baud = 115200,
3671 .uart_offset = 8,
3672 .first_offset = 0xC0,
3673 },
3674 [pbn_wch384_8] = {
3675 .flags = FL_BASE0,
3676 .num_ports = 8,
3677 .base_baud = 115200,
3678 .uart_offset = 8,
3679 .first_offset = 0x00,
3680 },
3681 /*
3682 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3683 */
3684 [pbn_pericom_PI7C9X7951] = {
3685 .flags = FL_BASE0,
3686 .num_ports = 1,
3687 .base_baud = 921600,
3688 .uart_offset = 0x8,
3689 },
3690 [pbn_pericom_PI7C9X7952] = {
3691 .flags = FL_BASE0,
3692 .num_ports = 2,
3693 .base_baud = 921600,
3694 .uart_offset = 0x8,
3695 },
3696 [pbn_pericom_PI7C9X7954] = {
3697 .flags = FL_BASE0,
3698 .num_ports = 4,
3699 .base_baud = 921600,
3700 .uart_offset = 0x8,
3701 },
3702 [pbn_pericom_PI7C9X7958] = {
3703 .flags = FL_BASE0,
3704 .num_ports = 8,
3705 .base_baud = 921600,
3706 .uart_offset = 0x8,
3707 },
3708 [pbn_sunix_pci_1s] = {
3709 .num_ports = 1,
3710 .base_baud = 921600,
3711 .uart_offset = 0x8,
3712 },
3713 [pbn_sunix_pci_2s] = {
3714 .num_ports = 2,
3715 .base_baud = 921600,
3716 .uart_offset = 0x8,
3717 },
3718 [pbn_sunix_pci_4s] = {
3719 .num_ports = 4,
3720 .base_baud = 921600,
3721 .uart_offset = 0x8,
3722 },
3723 [pbn_sunix_pci_8s] = {
3724 .num_ports = 8,
3725 .base_baud = 921600,
3726 .uart_offset = 0x8,
3727 },
3728 [pbn_sunix_pci_16s] = {
3729 .num_ports = 16,
3730 .base_baud = 921600,
3731 .uart_offset = 0x8,
3732 },
3733 [pbn_titan_1_4000000] = {
3734 .flags = FL_BASE0,
3735 .num_ports = 1,
3736 .base_baud = 4000000,
3737 .uart_offset = 0x200,
3738 .first_offset = 0x1000,
3739 },
3740 [pbn_titan_2_4000000] = {
3741 .flags = FL_BASE0,
3742 .num_ports = 2,
3743 .base_baud = 4000000,
3744 .uart_offset = 0x200,
3745 .first_offset = 0x1000,
3746 },
3747 [pbn_titan_4_4000000] = {
3748 .flags = FL_BASE0,
3749 .num_ports = 4,
3750 .base_baud = 4000000,
3751 .uart_offset = 0x200,
3752 .first_offset = 0x1000,
3753 },
3754 [pbn_titan_8_4000000] = {
3755 .flags = FL_BASE0,
3756 .num_ports = 8,
3757 .base_baud = 4000000,
3758 .uart_offset = 0x200,
3759 .first_offset = 0x1000,
3760 },
3761 [pbn_moxa8250_2p] = {
3762 .flags = FL_BASE1,
3763 .num_ports = 2,
3764 .base_baud = 921600,
3765 .uart_offset = 0x200,
3766 },
3767 [pbn_moxa8250_4p] = {
3768 .flags = FL_BASE1,
3769 .num_ports = 4,
3770 .base_baud = 921600,
3771 .uart_offset = 0x200,
3772 },
3773 [pbn_moxa8250_8p] = {
3774 .flags = FL_BASE1,
3775 .num_ports = 8,
3776 .base_baud = 921600,
3777 .uart_offset = 0x200,
3778 },
3779 };
3780
3781 static const struct pci_device_id blacklist[] = {
3782 /* softmodems */
3783 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3784 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3785 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3786
3787 /* multi-io cards handled by parport_serial */
3788 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3789 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3790 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3791
3792 /* Intel platforms with MID UART */
3793 { PCI_VDEVICE(INTEL, 0x081b), },
3794 { PCI_VDEVICE(INTEL, 0x081c), },
3795 { PCI_VDEVICE(INTEL, 0x081d), },
3796 { PCI_VDEVICE(INTEL, 0x1191), },
3797 { PCI_VDEVICE(INTEL, 0x18d8), },
3798 { PCI_VDEVICE(INTEL, 0x19d8), },
3799
3800 /* Intel platforms with DesignWare UART */
3801 { PCI_VDEVICE(INTEL, 0x0936), },
3802 { PCI_VDEVICE(INTEL, 0x0f0a), },
3803 { PCI_VDEVICE(INTEL, 0x0f0c), },
3804 { PCI_VDEVICE(INTEL, 0x228a), },
3805 { PCI_VDEVICE(INTEL, 0x228c), },
3806 { PCI_VDEVICE(INTEL, 0x4b96), },
3807 { PCI_VDEVICE(INTEL, 0x4b97), },
3808 { PCI_VDEVICE(INTEL, 0x4b98), },
3809 { PCI_VDEVICE(INTEL, 0x4b99), },
3810 { PCI_VDEVICE(INTEL, 0x4b9a), },
3811 { PCI_VDEVICE(INTEL, 0x4b9b), },
3812 { PCI_VDEVICE(INTEL, 0x9ce3), },
3813 { PCI_VDEVICE(INTEL, 0x9ce4), },
3814
3815 /* Exar devices */
3816 { PCI_VDEVICE(EXAR, PCI_ANY_ID), },
3817 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), },
3818
3819 /* End of the black list */
3820 { }
3821 };
3822
serial_pci_is_class_communication(struct pci_dev * dev)3823 static int serial_pci_is_class_communication(struct pci_dev *dev)
3824 {
3825 /*
3826 * If it is not a communications device or the programming
3827 * interface is greater than 6, give up.
3828 */
3829 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3830 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
3831 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3832 (dev->class & 0xff) > 6)
3833 return -ENODEV;
3834
3835 return 0;
3836 }
3837
3838 /*
3839 * Given a complete unknown PCI device, try to use some heuristics to
3840 * guess what the configuration might be, based on the pitiful PCI
3841 * serial specs. Returns 0 on success, -ENODEV on failure.
3842 */
3843 static int
serial_pci_guess_board(struct pci_dev * dev,struct pciserial_board * board)3844 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3845 {
3846 int num_iomem, num_port, first_port = -1, i;
3847 int rc;
3848
3849 rc = serial_pci_is_class_communication(dev);
3850 if (rc)
3851 return rc;
3852
3853 /*
3854 * Should we try to make guesses for multiport serial devices later?
3855 */
3856 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
3857 return -ENODEV;
3858
3859 num_iomem = num_port = 0;
3860 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
3861 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3862 num_port++;
3863 if (first_port == -1)
3864 first_port = i;
3865 }
3866 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3867 num_iomem++;
3868 }
3869
3870 /*
3871 * If there is 1 or 0 iomem regions, and exactly one port,
3872 * use it. We guess the number of ports based on the IO
3873 * region size.
3874 */
3875 if (num_iomem <= 1 && num_port == 1) {
3876 board->flags = first_port;
3877 board->num_ports = pci_resource_len(dev, first_port) / 8;
3878 return 0;
3879 }
3880
3881 /*
3882 * Now guess if we've got a board which indexes by BARs.
3883 * Each IO BAR should be 8 bytes, and they should follow
3884 * consecutively.
3885 */
3886 first_port = -1;
3887 num_port = 0;
3888 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
3889 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3890 pci_resource_len(dev, i) == 8 &&
3891 (first_port == -1 || (first_port + num_port) == i)) {
3892 num_port++;
3893 if (first_port == -1)
3894 first_port = i;
3895 }
3896 }
3897
3898 if (num_port > 1) {
3899 board->flags = first_port | FL_BASE_BARS;
3900 board->num_ports = num_port;
3901 return 0;
3902 }
3903
3904 return -ENODEV;
3905 }
3906
3907 static inline int
serial_pci_matches(const struct pciserial_board * board,const struct pciserial_board * guessed)3908 serial_pci_matches(const struct pciserial_board *board,
3909 const struct pciserial_board *guessed)
3910 {
3911 return
3912 board->num_ports == guessed->num_ports &&
3913 board->base_baud == guessed->base_baud &&
3914 board->uart_offset == guessed->uart_offset &&
3915 board->reg_shift == guessed->reg_shift &&
3916 board->first_offset == guessed->first_offset;
3917 }
3918
3919 struct serial_private *
pciserial_init_ports(struct pci_dev * dev,const struct pciserial_board * board)3920 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3921 {
3922 struct uart_8250_port uart;
3923 struct serial_private *priv;
3924 struct pci_serial_quirk *quirk;
3925 int rc, nr_ports, i;
3926
3927 nr_ports = board->num_ports;
3928
3929 /*
3930 * Find an init and setup quirks.
3931 */
3932 quirk = find_quirk(dev);
3933
3934 /*
3935 * Run the new-style initialization function.
3936 * The initialization function returns:
3937 * <0 - error
3938 * 0 - use board->num_ports
3939 * >0 - number of ports
3940 */
3941 if (quirk->init) {
3942 rc = quirk->init(dev);
3943 if (rc < 0) {
3944 priv = ERR_PTR(rc);
3945 goto err_out;
3946 }
3947 if (rc)
3948 nr_ports = rc;
3949 }
3950
3951 priv = kzalloc(sizeof(struct serial_private) +
3952 sizeof(unsigned int) * nr_ports,
3953 GFP_KERNEL);
3954 if (!priv) {
3955 priv = ERR_PTR(-ENOMEM);
3956 goto err_deinit;
3957 }
3958
3959 priv->dev = dev;
3960 priv->quirk = quirk;
3961
3962 memset(&uart, 0, sizeof(uart));
3963 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3964 uart.port.uartclk = board->base_baud * 16;
3965
3966 if (board->flags & FL_NOIRQ) {
3967 uart.port.irq = 0;
3968 } else {
3969 if (pci_match_id(pci_use_msi, dev)) {
3970 pci_dbg(dev, "Using MSI(-X) interrupts\n");
3971 pci_set_master(dev);
3972 uart.port.flags &= ~UPF_SHARE_IRQ;
3973 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
3974 } else {
3975 pci_dbg(dev, "Using legacy interrupts\n");
3976 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY);
3977 }
3978 if (rc < 0) {
3979 kfree(priv);
3980 priv = ERR_PTR(rc);
3981 goto err_deinit;
3982 }
3983
3984 uart.port.irq = pci_irq_vector(dev, 0);
3985 }
3986
3987 uart.port.dev = &dev->dev;
3988
3989 for (i = 0; i < nr_ports; i++) {
3990 if (quirk->setup(priv, board, &uart, i))
3991 break;
3992
3993 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3994 uart.port.iobase, uart.port.irq, uart.port.iotype);
3995
3996 priv->line[i] = serial8250_register_8250_port(&uart);
3997 if (priv->line[i] < 0) {
3998 pci_err(dev,
3999 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4000 uart.port.iobase, uart.port.irq,
4001 uart.port.iotype, priv->line[i]);
4002 break;
4003 }
4004 }
4005 priv->nr = i;
4006 priv->board = board;
4007 return priv;
4008
4009 err_deinit:
4010 if (quirk->exit)
4011 quirk->exit(dev);
4012 err_out:
4013 return priv;
4014 }
4015 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4016
pciserial_detach_ports(struct serial_private * priv)4017 static void pciserial_detach_ports(struct serial_private *priv)
4018 {
4019 struct pci_serial_quirk *quirk;
4020 int i;
4021
4022 for (i = 0; i < priv->nr; i++)
4023 serial8250_unregister_port(priv->line[i]);
4024
4025 /*
4026 * Find the exit quirks.
4027 */
4028 quirk = find_quirk(priv->dev);
4029 if (quirk->exit)
4030 quirk->exit(priv->dev);
4031 }
4032
pciserial_remove_ports(struct serial_private * priv)4033 void pciserial_remove_ports(struct serial_private *priv)
4034 {
4035 pciserial_detach_ports(priv);
4036 kfree(priv);
4037 }
4038 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4039
pciserial_suspend_ports(struct serial_private * priv)4040 void pciserial_suspend_ports(struct serial_private *priv)
4041 {
4042 int i;
4043
4044 for (i = 0; i < priv->nr; i++)
4045 if (priv->line[i] >= 0)
4046 serial8250_suspend_port(priv->line[i]);
4047
4048 /*
4049 * Ensure that every init quirk is properly torn down
4050 */
4051 if (priv->quirk->exit)
4052 priv->quirk->exit(priv->dev);
4053 }
4054 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4055
pciserial_resume_ports(struct serial_private * priv)4056 void pciserial_resume_ports(struct serial_private *priv)
4057 {
4058 int i;
4059
4060 /*
4061 * Ensure that the board is correctly configured.
4062 */
4063 if (priv->quirk->init)
4064 priv->quirk->init(priv->dev);
4065
4066 for (i = 0; i < priv->nr; i++)
4067 if (priv->line[i] >= 0)
4068 serial8250_resume_port(priv->line[i]);
4069 }
4070 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4071
4072 /*
4073 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4074 * to the arrangement of serial ports on a PCI card.
4075 */
4076 static int
pciserial_init_one(struct pci_dev * dev,const struct pci_device_id * ent)4077 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4078 {
4079 struct pci_serial_quirk *quirk;
4080 struct serial_private *priv;
4081 const struct pciserial_board *board;
4082 const struct pci_device_id *exclude;
4083 struct pciserial_board tmp;
4084 int rc;
4085
4086 quirk = find_quirk(dev);
4087 if (quirk->probe) {
4088 rc = quirk->probe(dev);
4089 if (rc)
4090 return rc;
4091 }
4092
4093 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4094 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data);
4095 return -EINVAL;
4096 }
4097
4098 board = &pci_boards[ent->driver_data];
4099
4100 exclude = pci_match_id(blacklist, dev);
4101 if (exclude)
4102 return -ENODEV;
4103
4104 rc = pcim_enable_device(dev);
4105 pci_save_state(dev);
4106 if (rc)
4107 return rc;
4108
4109 if (ent->driver_data == pbn_default) {
4110 /*
4111 * Use a copy of the pci_board entry for this;
4112 * avoid changing entries in the table.
4113 */
4114 memcpy(&tmp, board, sizeof(struct pciserial_board));
4115 board = &tmp;
4116
4117 /*
4118 * We matched one of our class entries. Try to
4119 * determine the parameters of this board.
4120 */
4121 rc = serial_pci_guess_board(dev, &tmp);
4122 if (rc)
4123 return rc;
4124 } else {
4125 /*
4126 * We matched an explicit entry. If we are able to
4127 * detect this boards settings with our heuristic,
4128 * then we no longer need this entry.
4129 */
4130 memcpy(&tmp, &pci_boards[pbn_default],
4131 sizeof(struct pciserial_board));
4132 rc = serial_pci_guess_board(dev, &tmp);
4133 if (rc == 0 && serial_pci_matches(board, &tmp))
4134 moan_device("Redundant entry in serial pci_table.",
4135 dev);
4136 }
4137
4138 priv = pciserial_init_ports(dev, board);
4139 if (IS_ERR(priv))
4140 return PTR_ERR(priv);
4141
4142 pci_set_drvdata(dev, priv);
4143 return 0;
4144 }
4145
pciserial_remove_one(struct pci_dev * dev)4146 static void pciserial_remove_one(struct pci_dev *dev)
4147 {
4148 struct serial_private *priv = pci_get_drvdata(dev);
4149
4150 pciserial_remove_ports(priv);
4151 }
4152
4153 #ifdef CONFIG_PM_SLEEP
pciserial_suspend_one(struct device * dev)4154 static int pciserial_suspend_one(struct device *dev)
4155 {
4156 struct serial_private *priv = dev_get_drvdata(dev);
4157
4158 if (priv)
4159 pciserial_suspend_ports(priv);
4160
4161 return 0;
4162 }
4163
pciserial_resume_one(struct device * dev)4164 static int pciserial_resume_one(struct device *dev)
4165 {
4166 struct pci_dev *pdev = to_pci_dev(dev);
4167 struct serial_private *priv = pci_get_drvdata(pdev);
4168 int err;
4169
4170 if (priv) {
4171 /*
4172 * The device may have been disabled. Re-enable it.
4173 */
4174 err = pci_enable_device(pdev);
4175 /* FIXME: We cannot simply error out here */
4176 if (err)
4177 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n");
4178 pciserial_resume_ports(priv);
4179 }
4180 return 0;
4181 }
4182 #endif
4183
4184 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4185 pciserial_resume_one);
4186
4187 static const struct pci_device_id serial_pci_tbl[] = {
4188 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4189 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4190 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4191 pbn_b2_8_921600 },
4192 /* Advantech also use 0x3618 and 0xf618 */
4193 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4194 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4195 pbn_b0_4_921600 },
4196 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4197 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4198 pbn_b0_4_921600 },
4199 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4200 PCI_SUBVENDOR_ID_CONNECT_TECH,
4201 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4202 pbn_b1_8_1382400 },
4203 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4204 PCI_SUBVENDOR_ID_CONNECT_TECH,
4205 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4206 pbn_b1_4_1382400 },
4207 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4208 PCI_SUBVENDOR_ID_CONNECT_TECH,
4209 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4210 pbn_b1_2_1382400 },
4211 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4212 PCI_SUBVENDOR_ID_CONNECT_TECH,
4213 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4214 pbn_b1_8_1382400 },
4215 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4216 PCI_SUBVENDOR_ID_CONNECT_TECH,
4217 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4218 pbn_b1_4_1382400 },
4219 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4220 PCI_SUBVENDOR_ID_CONNECT_TECH,
4221 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4222 pbn_b1_2_1382400 },
4223 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4224 PCI_SUBVENDOR_ID_CONNECT_TECH,
4225 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4226 pbn_b1_8_921600 },
4227 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4228 PCI_SUBVENDOR_ID_CONNECT_TECH,
4229 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4230 pbn_b1_8_921600 },
4231 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4232 PCI_SUBVENDOR_ID_CONNECT_TECH,
4233 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4234 pbn_b1_4_921600 },
4235 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4236 PCI_SUBVENDOR_ID_CONNECT_TECH,
4237 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4238 pbn_b1_4_921600 },
4239 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4240 PCI_SUBVENDOR_ID_CONNECT_TECH,
4241 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4242 pbn_b1_2_921600 },
4243 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4244 PCI_SUBVENDOR_ID_CONNECT_TECH,
4245 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4246 pbn_b1_8_921600 },
4247 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4248 PCI_SUBVENDOR_ID_CONNECT_TECH,
4249 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4250 pbn_b1_8_921600 },
4251 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4252 PCI_SUBVENDOR_ID_CONNECT_TECH,
4253 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4254 pbn_b1_4_921600 },
4255 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4256 PCI_SUBVENDOR_ID_CONNECT_TECH,
4257 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4258 pbn_b1_2_1250000 },
4259 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4260 PCI_SUBVENDOR_ID_CONNECT_TECH,
4261 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4262 pbn_b0_2_1843200 },
4263 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4264 PCI_SUBVENDOR_ID_CONNECT_TECH,
4265 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4266 pbn_b0_4_1843200 },
4267 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4268 PCI_VENDOR_ID_AFAVLAB,
4269 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4270 pbn_b0_4_1152000 },
4271 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4272 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4273 pbn_b2_bt_1_115200 },
4274 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4275 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4276 pbn_b2_bt_2_115200 },
4277 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4278 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4279 pbn_b2_bt_4_115200 },
4280 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4281 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4282 pbn_b2_bt_2_115200 },
4283 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4284 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4285 pbn_b2_bt_4_115200 },
4286 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4287 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4288 pbn_b2_8_115200 },
4289 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4290 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4291 pbn_b2_8_460800 },
4292 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4293 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4294 pbn_b2_8_115200 },
4295
4296 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4297 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4298 pbn_b2_bt_2_115200 },
4299 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4300 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4301 pbn_b2_bt_2_921600 },
4302 /*
4303 * VScom SPCOM800, from sl@s.pl
4304 */
4305 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4306 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4307 pbn_b2_8_921600 },
4308 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4309 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4310 pbn_b2_4_921600 },
4311 /* Unknown card - subdevice 0x1584 */
4312 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4313 PCI_VENDOR_ID_PLX,
4314 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4315 pbn_b2_4_115200 },
4316 /* Unknown card - subdevice 0x1588 */
4317 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4318 PCI_VENDOR_ID_PLX,
4319 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4320 pbn_b2_8_115200 },
4321 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4322 PCI_SUBVENDOR_ID_KEYSPAN,
4323 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4324 pbn_panacom },
4325 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4326 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4327 pbn_panacom4 },
4328 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4329 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4330 pbn_panacom2 },
4331 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4332 PCI_VENDOR_ID_ESDGMBH,
4333 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4334 pbn_b2_4_115200 },
4335 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4336 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4337 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4338 pbn_b2_4_460800 },
4339 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4340 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4341 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4342 pbn_b2_8_460800 },
4343 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4344 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4345 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4346 pbn_b2_16_460800 },
4347 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4348 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4349 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4350 pbn_b2_16_460800 },
4351 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4352 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4353 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4354 pbn_b2_4_460800 },
4355 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4356 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4357 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4358 pbn_b2_8_460800 },
4359 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4360 PCI_SUBVENDOR_ID_EXSYS,
4361 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4362 pbn_b2_4_115200 },
4363 /*
4364 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4365 * (Exoray@isys.ca)
4366 */
4367 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4368 0x10b5, 0x106a, 0, 0,
4369 pbn_plx_romulus },
4370 /*
4371 * Quatech cards. These actually have configurable clocks but for
4372 * now we just use the default.
4373 *
4374 * 100 series are RS232, 200 series RS422,
4375 */
4376 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4377 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4378 pbn_b1_4_115200 },
4379 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4380 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4381 pbn_b1_2_115200 },
4382 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4383 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4384 pbn_b2_2_115200 },
4385 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4386 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4387 pbn_b1_2_115200 },
4388 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4389 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4390 pbn_b2_2_115200 },
4391 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4392 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4393 pbn_b1_4_115200 },
4394 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4395 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4396 pbn_b1_8_115200 },
4397 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4398 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4399 pbn_b1_8_115200 },
4400 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4401 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4402 pbn_b1_4_115200 },
4403 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4404 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4405 pbn_b1_2_115200 },
4406 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4407 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4408 pbn_b1_4_115200 },
4409 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4410 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4411 pbn_b1_2_115200 },
4412 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4413 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4414 pbn_b2_4_115200 },
4415 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4416 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4417 pbn_b2_2_115200 },
4418 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4419 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4420 pbn_b2_1_115200 },
4421 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4422 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4423 pbn_b2_4_115200 },
4424 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4425 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4426 pbn_b2_2_115200 },
4427 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4428 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4429 pbn_b2_1_115200 },
4430 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4431 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4432 pbn_b0_8_115200 },
4433
4434 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4435 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4436 0, 0,
4437 pbn_b0_4_921600 },
4438 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4439 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4440 0, 0,
4441 pbn_b0_4_1152000 },
4442 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4443 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4444 pbn_b0_bt_2_921600 },
4445
4446 /*
4447 * The below card is a little controversial since it is the
4448 * subject of a PCI vendor/device ID clash. (See
4449 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4450 * For now just used the hex ID 0x950a.
4451 */
4452 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4453 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4454 0, 0, pbn_b0_2_115200 },
4455 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4456 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4457 0, 0, pbn_b0_2_115200 },
4458 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4459 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4460 pbn_b0_2_1130000 },
4461 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4462 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4463 pbn_b0_1_921600 },
4464 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4465 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4466 pbn_b0_4_115200 },
4467 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4468 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4469 pbn_b0_bt_2_921600 },
4470 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4471 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4472 pbn_b2_8_1152000 },
4473
4474 /*
4475 * Oxford Semiconductor Inc. Tornado PCI express device range.
4476 */
4477 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4478 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4479 pbn_b0_1_3906250 },
4480 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4481 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4482 pbn_b0_1_3906250 },
4483 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4484 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4485 pbn_oxsemi_1_3906250 },
4486 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4487 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4488 pbn_oxsemi_1_3906250 },
4489 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4490 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4491 pbn_b0_1_3906250 },
4492 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4493 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4494 pbn_b0_1_3906250 },
4495 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4496 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4497 pbn_oxsemi_1_3906250 },
4498 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4499 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4500 pbn_oxsemi_1_3906250 },
4501 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4502 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4503 pbn_b0_1_3906250 },
4504 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4505 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4506 pbn_b0_1_3906250 },
4507 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4508 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4509 pbn_b0_1_3906250 },
4510 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4511 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4512 pbn_b0_1_3906250 },
4513 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4514 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4515 pbn_oxsemi_2_3906250 },
4516 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4517 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4518 pbn_oxsemi_2_3906250 },
4519 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4520 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4521 pbn_oxsemi_4_3906250 },
4522 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4523 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4524 pbn_oxsemi_4_3906250 },
4525 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4526 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4527 pbn_oxsemi_8_3906250 },
4528 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4529 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4530 pbn_oxsemi_8_3906250 },
4531 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4532 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4533 pbn_oxsemi_1_3906250 },
4534 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4535 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4536 pbn_oxsemi_1_3906250 },
4537 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4538 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4539 pbn_oxsemi_1_3906250 },
4540 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4541 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4542 pbn_oxsemi_1_3906250 },
4543 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4544 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4545 pbn_oxsemi_1_3906250 },
4546 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4547 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4548 pbn_oxsemi_1_3906250 },
4549 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4550 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4551 pbn_oxsemi_1_3906250 },
4552 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4553 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4554 pbn_oxsemi_1_3906250 },
4555 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4556 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4557 pbn_oxsemi_1_3906250 },
4558 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4559 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4560 pbn_oxsemi_1_3906250 },
4561 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4562 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4563 pbn_oxsemi_1_3906250 },
4564 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4565 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4566 pbn_oxsemi_1_3906250 },
4567 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4568 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4569 pbn_oxsemi_1_3906250 },
4570 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4571 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4572 pbn_oxsemi_1_3906250 },
4573 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4574 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4575 pbn_oxsemi_1_3906250 },
4576 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4577 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4578 pbn_oxsemi_1_3906250 },
4579 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4580 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4581 pbn_oxsemi_1_3906250 },
4582 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4583 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4584 pbn_oxsemi_1_3906250 },
4585 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4586 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4587 pbn_oxsemi_1_3906250 },
4588 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4589 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4590 pbn_oxsemi_1_3906250 },
4591 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4592 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4593 pbn_oxsemi_1_3906250 },
4594 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596 pbn_oxsemi_1_3906250 },
4597 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4598 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4599 pbn_oxsemi_1_3906250 },
4600 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4601 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4602 pbn_oxsemi_1_3906250 },
4603 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605 pbn_oxsemi_1_3906250 },
4606 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4607 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4608 pbn_oxsemi_1_3906250 },
4609 /*
4610 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4611 */
4612 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4613 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4614 pbn_oxsemi_1_3906250 },
4615 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4616 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4617 pbn_oxsemi_2_3906250 },
4618 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4619 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4620 pbn_oxsemi_4_3906250 },
4621 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4622 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4623 pbn_oxsemi_8_3906250 },
4624
4625 /*
4626 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4627 */
4628 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4629 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4630 pbn_oxsemi_2_3906250 },
4631 /*
4632 * EndRun Technologies. PCI express device range.
4633 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952.
4634 */
4635 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4636 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4637 pbn_oxsemi_2_3906250 },
4638
4639 /*
4640 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4641 * from skokodyn@yahoo.com
4642 */
4643 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4644 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4645 pbn_sbsxrsio },
4646 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4647 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4648 pbn_sbsxrsio },
4649 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4650 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4651 pbn_sbsxrsio },
4652 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4653 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4654 pbn_sbsxrsio },
4655
4656 /*
4657 * Digitan DS560-558, from jimd@esoft.com
4658 */
4659 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4660 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4661 pbn_b1_1_115200 },
4662
4663 /*
4664 * Titan Electronic cards
4665 * The 400L and 800L have a custom setup quirk.
4666 */
4667 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4668 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4669 pbn_b0_1_921600 },
4670 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4671 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4672 pbn_b0_2_921600 },
4673 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4674 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4675 pbn_b0_4_921600 },
4676 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4677 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4678 pbn_b0_4_921600 },
4679 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4680 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4681 pbn_b1_1_921600 },
4682 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4683 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4684 pbn_b1_bt_2_921600 },
4685 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4686 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4687 pbn_b0_bt_4_921600 },
4688 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4689 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4690 pbn_b0_bt_8_921600 },
4691 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4692 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4693 pbn_b4_bt_2_921600 },
4694 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4695 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4696 pbn_b4_bt_4_921600 },
4697 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4698 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4699 pbn_b4_bt_8_921600 },
4700 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4701 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4702 pbn_b0_4_921600 },
4703 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4704 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4705 pbn_b0_4_921600 },
4706 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4707 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4708 pbn_b0_4_921600 },
4709 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4710 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4711 pbn_titan_1_4000000 },
4712 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4713 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4714 pbn_titan_2_4000000 },
4715 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4716 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4717 pbn_titan_4_4000000 },
4718 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4719 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4720 pbn_titan_8_4000000 },
4721 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4722 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4723 pbn_titan_2_4000000 },
4724 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4725 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4726 pbn_titan_2_4000000 },
4727 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4728 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4729 pbn_b0_bt_2_921600 },
4730 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4731 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4732 pbn_b0_4_921600 },
4733 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4734 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4735 pbn_b0_4_921600 },
4736 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4737 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4738 pbn_b0_4_921600 },
4739 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4740 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4741 pbn_b0_4_921600 },
4742
4743 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4744 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4745 pbn_b2_1_460800 },
4746 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4747 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4748 pbn_b2_1_460800 },
4749 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4750 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4751 pbn_b2_1_460800 },
4752 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4753 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4754 pbn_b2_bt_2_921600 },
4755 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4756 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4757 pbn_b2_bt_2_921600 },
4758 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4759 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4760 pbn_b2_bt_2_921600 },
4761 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4762 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4763 pbn_b2_bt_4_921600 },
4764 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4765 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4766 pbn_b2_bt_4_921600 },
4767 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4768 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4769 pbn_b2_bt_4_921600 },
4770 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4771 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4772 pbn_b0_1_921600 },
4773 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4774 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4775 pbn_b0_1_921600 },
4776 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4777 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4778 pbn_b0_1_921600 },
4779 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4780 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4781 pbn_b0_bt_2_921600 },
4782 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4783 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4784 pbn_b0_bt_2_921600 },
4785 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4786 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4787 pbn_b0_bt_2_921600 },
4788 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4789 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4790 pbn_b0_bt_4_921600 },
4791 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4792 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4793 pbn_b0_bt_4_921600 },
4794 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4795 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4796 pbn_b0_bt_4_921600 },
4797 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4798 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4799 pbn_b0_bt_8_921600 },
4800 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4801 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4802 pbn_b0_bt_8_921600 },
4803 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4804 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4805 pbn_b0_bt_8_921600 },
4806
4807 /*
4808 * Computone devices submitted by Doug McNash dmcnash@computone.com
4809 */
4810 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4811 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4812 0, 0, pbn_computone_4 },
4813 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4814 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4815 0, 0, pbn_computone_8 },
4816 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4817 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4818 0, 0, pbn_computone_6 },
4819
4820 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4821 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4822 pbn_oxsemi },
4823 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4824 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4825 pbn_b0_bt_1_921600 },
4826
4827 /*
4828 * Sunix PCI serial boards
4829 */
4830 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4831 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0,
4832 pbn_sunix_pci_1s },
4833 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4834 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0,
4835 pbn_sunix_pci_2s },
4836 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4837 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0,
4838 pbn_sunix_pci_4s },
4839 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4840 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0,
4841 pbn_sunix_pci_4s },
4842 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4843 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0,
4844 pbn_sunix_pci_8s },
4845 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4846 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0,
4847 pbn_sunix_pci_8s },
4848 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4849 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0,
4850 pbn_sunix_pci_16s },
4851
4852 /*
4853 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4854 */
4855 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4856 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4857 pbn_b0_bt_8_115200 },
4858 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4859 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4860 pbn_b0_bt_8_115200 },
4861
4862 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4863 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4864 pbn_b0_bt_2_115200 },
4865 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4866 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4867 pbn_b0_bt_2_115200 },
4868 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4869 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4870 pbn_b0_bt_2_115200 },
4871 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4872 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4873 pbn_b0_bt_2_115200 },
4874 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4875 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4876 pbn_b0_bt_2_115200 },
4877 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4878 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4879 pbn_b0_bt_4_460800 },
4880 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4881 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4882 pbn_b0_bt_4_460800 },
4883 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4884 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4885 pbn_b0_bt_2_460800 },
4886 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4887 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4888 pbn_b0_bt_2_460800 },
4889 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4890 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4891 pbn_b0_bt_2_460800 },
4892 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4893 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4894 pbn_b0_bt_1_115200 },
4895 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4896 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4897 pbn_b0_bt_1_460800 },
4898
4899 /*
4900 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4901 * Cards are identified by their subsystem vendor IDs, which
4902 * (in hex) match the model number.
4903 *
4904 * Note that JC140x are RS422/485 cards which require ox950
4905 * ACR = 0x10, and as such are not currently fully supported.
4906 */
4907 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4908 0x1204, 0x0004, 0, 0,
4909 pbn_b0_4_921600 },
4910 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4911 0x1208, 0x0004, 0, 0,
4912 pbn_b0_4_921600 },
4913 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4914 0x1402, 0x0002, 0, 0,
4915 pbn_b0_2_921600 }, */
4916 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4917 0x1404, 0x0004, 0, 0,
4918 pbn_b0_4_921600 }, */
4919 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4920 0x1208, 0x0004, 0, 0,
4921 pbn_b0_4_921600 },
4922
4923 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4924 0x1204, 0x0004, 0, 0,
4925 pbn_b0_4_921600 },
4926 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4927 0x1208, 0x0004, 0, 0,
4928 pbn_b0_4_921600 },
4929 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4930 0x1208, 0x0004, 0, 0,
4931 pbn_b0_4_921600 },
4932 /*
4933 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4934 */
4935 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4936 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4937 pbn_b1_1_1382400 },
4938
4939 /*
4940 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4941 */
4942 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4944 pbn_b1_1_1382400 },
4945
4946 /*
4947 * RAStel 2 port modem, gerg@moreton.com.au
4948 */
4949 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4950 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4951 pbn_b2_bt_2_115200 },
4952
4953 /*
4954 * EKF addition for i960 Boards form EKF with serial port
4955 */
4956 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4957 0xE4BF, PCI_ANY_ID, 0, 0,
4958 pbn_intel_i960 },
4959
4960 /*
4961 * Xircom Cardbus/Ethernet combos
4962 */
4963 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4964 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4965 pbn_b0_1_115200 },
4966 /*
4967 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4968 */
4969 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4970 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4971 pbn_b0_1_115200 },
4972
4973 /*
4974 * Untested PCI modems, sent in from various folks...
4975 */
4976
4977 /*
4978 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4979 */
4980 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4981 0x1048, 0x1500, 0, 0,
4982 pbn_b1_1_115200 },
4983
4984 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4985 0xFF00, 0, 0, 0,
4986 pbn_sgi_ioc3 },
4987
4988 /*
4989 * HP Diva card
4990 */
4991 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4992 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4993 pbn_b1_1_115200 },
4994 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4995 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4996 pbn_b0_5_115200 },
4997 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4998 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4999 pbn_b2_1_115200 },
5000 /* HPE PCI serial device */
5001 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
5002 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5003 pbn_b1_1_115200 },
5004
5005 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5006 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5007 pbn_b3_2_115200 },
5008 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5009 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5010 pbn_b3_4_115200 },
5011 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5012 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5013 pbn_b3_8_115200 },
5014 /*
5015 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
5016 */
5017 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
5018 PCI_ANY_ID, PCI_ANY_ID,
5019 0,
5020 0, pbn_pericom_PI7C9X7951 },
5021 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
5022 PCI_ANY_ID, PCI_ANY_ID,
5023 0,
5024 0, pbn_pericom_PI7C9X7952 },
5025 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
5026 PCI_ANY_ID, PCI_ANY_ID,
5027 0,
5028 0, pbn_pericom_PI7C9X7954 },
5029 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
5030 PCI_ANY_ID, PCI_ANY_ID,
5031 0,
5032 0, pbn_pericom_PI7C9X7958 },
5033 /*
5034 * ACCES I/O Products quad
5035 */
5036 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB,
5037 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5038 pbn_pericom_PI7C9X7952 },
5039 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S,
5040 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5041 pbn_pericom_PI7C9X7952 },
5042 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
5043 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5044 pbn_pericom_PI7C9X7954 },
5045 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
5046 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5047 pbn_pericom_PI7C9X7954 },
5048 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB,
5049 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5050 pbn_pericom_PI7C9X7952 },
5051 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2,
5052 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5053 pbn_pericom_PI7C9X7952 },
5054 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
5055 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5056 pbn_pericom_PI7C9X7954 },
5057 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
5058 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5059 pbn_pericom_PI7C9X7954 },
5060 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB,
5061 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5062 pbn_pericom_PI7C9X7952 },
5063 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM,
5064 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5065 pbn_pericom_PI7C9X7952 },
5066 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
5067 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5068 pbn_pericom_PI7C9X7954 },
5069 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
5070 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5071 pbn_pericom_PI7C9X7954 },
5072 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1,
5073 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5074 pbn_pericom_PI7C9X7951 },
5075 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2,
5076 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5077 pbn_pericom_PI7C9X7952 },
5078 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2,
5079 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5080 pbn_pericom_PI7C9X7952 },
5081 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
5082 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5083 pbn_pericom_PI7C9X7954 },
5084 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
5085 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5086 pbn_pericom_PI7C9X7954 },
5087 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S,
5088 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5089 pbn_pericom_PI7C9X7952 },
5090 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
5091 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5092 pbn_pericom_PI7C9X7954 },
5093 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2,
5094 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5095 pbn_pericom_PI7C9X7952 },
5096 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2,
5097 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5098 pbn_pericom_PI7C9X7952 },
5099 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
5100 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5101 pbn_pericom_PI7C9X7954 },
5102 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
5103 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5104 pbn_pericom_PI7C9X7954 },
5105 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM,
5106 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5107 pbn_pericom_PI7C9X7952 },
5108 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
5109 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5110 pbn_pericom_PI7C9X7954 },
5111 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
5112 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5113 pbn_pericom_PI7C9X7954 },
5114 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8,
5115 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5116 pbn_pericom_PI7C9X7958 },
5117 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8,
5118 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5119 pbn_pericom_PI7C9X7958 },
5120 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
5121 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5122 pbn_pericom_PI7C9X7954 },
5123 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8,
5124 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5125 pbn_pericom_PI7C9X7958 },
5126 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
5127 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5128 pbn_pericom_PI7C9X7954 },
5129 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM,
5130 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5131 pbn_pericom_PI7C9X7958 },
5132 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
5133 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5134 pbn_pericom_PI7C9X7954 },
5135 /*
5136 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5137 */
5138 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5139 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5140 pbn_b0_1_115200 },
5141 /*
5142 * ITE
5143 */
5144 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5145 PCI_ANY_ID, PCI_ANY_ID,
5146 0, 0,
5147 pbn_b1_bt_1_115200 },
5148
5149 /*
5150 * IntaShield IS-200
5151 */
5152 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5153 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
5154 pbn_b2_2_115200 },
5155 /*
5156 * IntaShield IS-400
5157 */
5158 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5159 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5160 pbn_b2_4_115200 },
5161 /* Brainboxes Devices */
5162 /*
5163 * Brainboxes UC-101
5164 */
5165 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1,
5166 PCI_ANY_ID, PCI_ANY_ID,
5167 0, 0,
5168 pbn_b2_2_115200 },
5169 /*
5170 * Brainboxes UC-235/246
5171 */
5172 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1,
5173 PCI_ANY_ID, PCI_ANY_ID,
5174 0, 0,
5175 pbn_b2_1_115200 },
5176 /*
5177 * Brainboxes UC-257
5178 */
5179 { PCI_VENDOR_ID_INTASHIELD, 0x0861,
5180 PCI_ANY_ID, PCI_ANY_ID,
5181 0, 0,
5182 pbn_b2_2_115200 },
5183 /*
5184 * Brainboxes UC-260/271/701/756
5185 */
5186 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
5187 PCI_ANY_ID, PCI_ANY_ID,
5188 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5189 pbn_b2_4_115200 },
5190 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
5191 PCI_ANY_ID, PCI_ANY_ID,
5192 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5193 pbn_b2_4_115200 },
5194 /*
5195 * Brainboxes UC-268
5196 */
5197 { PCI_VENDOR_ID_INTASHIELD, 0x0841,
5198 PCI_ANY_ID, PCI_ANY_ID,
5199 0, 0,
5200 pbn_b2_4_115200 },
5201 /*
5202 * Brainboxes UC-275/279
5203 */
5204 { PCI_VENDOR_ID_INTASHIELD, 0x0881,
5205 PCI_ANY_ID, PCI_ANY_ID,
5206 0, 0,
5207 pbn_b2_8_115200 },
5208 /*
5209 * Brainboxes UC-302
5210 */
5211 { PCI_VENDOR_ID_INTASHIELD, 0x08E1,
5212 PCI_ANY_ID, PCI_ANY_ID,
5213 0, 0,
5214 pbn_b2_2_115200 },
5215 /*
5216 * Brainboxes UC-310
5217 */
5218 { PCI_VENDOR_ID_INTASHIELD, 0x08C1,
5219 PCI_ANY_ID, PCI_ANY_ID,
5220 0, 0,
5221 pbn_b2_2_115200 },
5222 /*
5223 * Brainboxes UC-313
5224 */
5225 { PCI_VENDOR_ID_INTASHIELD, 0x08A3,
5226 PCI_ANY_ID, PCI_ANY_ID,
5227 0, 0,
5228 pbn_b2_2_115200 },
5229 /*
5230 * Brainboxes UC-320/324
5231 */
5232 { PCI_VENDOR_ID_INTASHIELD, 0x0A61,
5233 PCI_ANY_ID, PCI_ANY_ID,
5234 0, 0,
5235 pbn_b2_1_115200 },
5236 /*
5237 * Brainboxes UC-346
5238 */
5239 { PCI_VENDOR_ID_INTASHIELD, 0x0B02,
5240 PCI_ANY_ID, PCI_ANY_ID,
5241 0, 0,
5242 pbn_b2_4_115200 },
5243 /*
5244 * Brainboxes UC-357
5245 */
5246 { PCI_VENDOR_ID_INTASHIELD, 0x0A81,
5247 PCI_ANY_ID, PCI_ANY_ID,
5248 0, 0,
5249 pbn_b2_2_115200 },
5250 { PCI_VENDOR_ID_INTASHIELD, 0x0A83,
5251 PCI_ANY_ID, PCI_ANY_ID,
5252 0, 0,
5253 pbn_b2_2_115200 },
5254 /*
5255 * Brainboxes UC-368
5256 */
5257 { PCI_VENDOR_ID_INTASHIELD, 0x0C41,
5258 PCI_ANY_ID, PCI_ANY_ID,
5259 0, 0,
5260 pbn_b2_4_115200 },
5261 /*
5262 * Brainboxes UC-420/431
5263 */
5264 { PCI_VENDOR_ID_INTASHIELD, 0x0921,
5265 PCI_ANY_ID, PCI_ANY_ID,
5266 0, 0,
5267 pbn_b2_4_115200 },
5268 /*
5269 * Perle PCI-RAS cards
5270 */
5271 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5272 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5273 0, 0, pbn_b2_4_921600 },
5274 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5275 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5276 0, 0, pbn_b2_8_921600 },
5277
5278 /*
5279 * Mainpine series cards: Fairly standard layout but fools
5280 * parts of the autodetect in some cases and uses otherwise
5281 * unmatched communications subclasses in the PCI Express case
5282 */
5283
5284 { /* RockForceDUO */
5285 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5286 PCI_VENDOR_ID_MAINPINE, 0x0200,
5287 0, 0, pbn_b0_2_115200 },
5288 { /* RockForceQUATRO */
5289 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5290 PCI_VENDOR_ID_MAINPINE, 0x0300,
5291 0, 0, pbn_b0_4_115200 },
5292 { /* RockForceDUO+ */
5293 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5294 PCI_VENDOR_ID_MAINPINE, 0x0400,
5295 0, 0, pbn_b0_2_115200 },
5296 { /* RockForceQUATRO+ */
5297 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5298 PCI_VENDOR_ID_MAINPINE, 0x0500,
5299 0, 0, pbn_b0_4_115200 },
5300 { /* RockForce+ */
5301 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5302 PCI_VENDOR_ID_MAINPINE, 0x0600,
5303 0, 0, pbn_b0_2_115200 },
5304 { /* RockForce+ */
5305 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5306 PCI_VENDOR_ID_MAINPINE, 0x0700,
5307 0, 0, pbn_b0_4_115200 },
5308 { /* RockForceOCTO+ */
5309 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5310 PCI_VENDOR_ID_MAINPINE, 0x0800,
5311 0, 0, pbn_b0_8_115200 },
5312 { /* RockForceDUO+ */
5313 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5314 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5315 0, 0, pbn_b0_2_115200 },
5316 { /* RockForceQUARTRO+ */
5317 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5318 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5319 0, 0, pbn_b0_4_115200 },
5320 { /* RockForceOCTO+ */
5321 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5322 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5323 0, 0, pbn_b0_8_115200 },
5324 { /* RockForceD1 */
5325 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5326 PCI_VENDOR_ID_MAINPINE, 0x2000,
5327 0, 0, pbn_b0_1_115200 },
5328 { /* RockForceF1 */
5329 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5330 PCI_VENDOR_ID_MAINPINE, 0x2100,
5331 0, 0, pbn_b0_1_115200 },
5332 { /* RockForceD2 */
5333 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5334 PCI_VENDOR_ID_MAINPINE, 0x2200,
5335 0, 0, pbn_b0_2_115200 },
5336 { /* RockForceF2 */
5337 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5338 PCI_VENDOR_ID_MAINPINE, 0x2300,
5339 0, 0, pbn_b0_2_115200 },
5340 { /* RockForceD4 */
5341 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5342 PCI_VENDOR_ID_MAINPINE, 0x2400,
5343 0, 0, pbn_b0_4_115200 },
5344 { /* RockForceF4 */
5345 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5346 PCI_VENDOR_ID_MAINPINE, 0x2500,
5347 0, 0, pbn_b0_4_115200 },
5348 { /* RockForceD8 */
5349 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5350 PCI_VENDOR_ID_MAINPINE, 0x2600,
5351 0, 0, pbn_b0_8_115200 },
5352 { /* RockForceF8 */
5353 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5354 PCI_VENDOR_ID_MAINPINE, 0x2700,
5355 0, 0, pbn_b0_8_115200 },
5356 { /* IQ Express D1 */
5357 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5358 PCI_VENDOR_ID_MAINPINE, 0x3000,
5359 0, 0, pbn_b0_1_115200 },
5360 { /* IQ Express F1 */
5361 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5362 PCI_VENDOR_ID_MAINPINE, 0x3100,
5363 0, 0, pbn_b0_1_115200 },
5364 { /* IQ Express D2 */
5365 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5366 PCI_VENDOR_ID_MAINPINE, 0x3200,
5367 0, 0, pbn_b0_2_115200 },
5368 { /* IQ Express F2 */
5369 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5370 PCI_VENDOR_ID_MAINPINE, 0x3300,
5371 0, 0, pbn_b0_2_115200 },
5372 { /* IQ Express D4 */
5373 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5374 PCI_VENDOR_ID_MAINPINE, 0x3400,
5375 0, 0, pbn_b0_4_115200 },
5376 { /* IQ Express F4 */
5377 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5378 PCI_VENDOR_ID_MAINPINE, 0x3500,
5379 0, 0, pbn_b0_4_115200 },
5380 { /* IQ Express D8 */
5381 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5382 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5383 0, 0, pbn_b0_8_115200 },
5384 { /* IQ Express F8 */
5385 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5386 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5387 0, 0, pbn_b0_8_115200 },
5388
5389
5390 /*
5391 * PA Semi PA6T-1682M on-chip UART
5392 */
5393 { PCI_VENDOR_ID_PASEMI, 0xa004,
5394 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5395 pbn_pasemi_1682M },
5396
5397 /*
5398 * National Instruments
5399 */
5400 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5401 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5402 pbn_b1_16_115200 },
5403 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5404 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5405 pbn_b1_8_115200 },
5406 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5407 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5408 pbn_b1_bt_4_115200 },
5409 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5410 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5411 pbn_b1_bt_2_115200 },
5412 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5413 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5414 pbn_b1_bt_4_115200 },
5415 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5416 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5417 pbn_b1_bt_2_115200 },
5418 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5419 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5420 pbn_b1_16_115200 },
5421 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5422 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5423 pbn_b1_8_115200 },
5424 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5425 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5426 pbn_b1_bt_4_115200 },
5427 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5428 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5429 pbn_b1_bt_2_115200 },
5430 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5431 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5432 pbn_b1_bt_4_115200 },
5433 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5434 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5435 pbn_b1_bt_2_115200 },
5436 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5437 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5438 pbn_ni8430_2 },
5439 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5440 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5441 pbn_ni8430_2 },
5442 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5443 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5444 pbn_ni8430_4 },
5445 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5446 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5447 pbn_ni8430_4 },
5448 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5449 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5450 pbn_ni8430_8 },
5451 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5452 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5453 pbn_ni8430_8 },
5454 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5455 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5456 pbn_ni8430_16 },
5457 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5458 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5459 pbn_ni8430_16 },
5460 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5461 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5462 pbn_ni8430_2 },
5463 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5464 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5465 pbn_ni8430_2 },
5466 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5467 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5468 pbn_ni8430_4 },
5469 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5470 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5471 pbn_ni8430_4 },
5472
5473 /*
5474 * MOXA
5475 */
5476 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E,
5477 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5478 pbn_moxa8250_2p },
5479 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL,
5480 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5481 pbn_moxa8250_2p },
5482 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A,
5483 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5484 pbn_moxa8250_4p },
5485 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL,
5486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5487 pbn_moxa8250_4p },
5488 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A,
5489 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5490 pbn_moxa8250_8p },
5491 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B,
5492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5493 pbn_moxa8250_8p },
5494 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A,
5495 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5496 pbn_moxa8250_8p },
5497 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I,
5498 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5499 pbn_moxa8250_8p },
5500 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL,
5501 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5502 pbn_moxa8250_2p },
5503 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A,
5504 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5505 pbn_moxa8250_4p },
5506 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A,
5507 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5508 pbn_moxa8250_8p },
5509 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A,
5510 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5511 pbn_moxa8250_8p },
5512
5513 /*
5514 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5515 */
5516 { PCI_VENDOR_ID_ADDIDATA,
5517 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5518 PCI_ANY_ID,
5519 PCI_ANY_ID,
5520 0,
5521 0,
5522 pbn_b0_4_115200 },
5523
5524 { PCI_VENDOR_ID_ADDIDATA,
5525 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5526 PCI_ANY_ID,
5527 PCI_ANY_ID,
5528 0,
5529 0,
5530 pbn_b0_2_115200 },
5531
5532 { PCI_VENDOR_ID_ADDIDATA,
5533 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5534 PCI_ANY_ID,
5535 PCI_ANY_ID,
5536 0,
5537 0,
5538 pbn_b0_1_115200 },
5539
5540 { PCI_VENDOR_ID_AMCC,
5541 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5542 PCI_ANY_ID,
5543 PCI_ANY_ID,
5544 0,
5545 0,
5546 pbn_b1_8_115200 },
5547
5548 { PCI_VENDOR_ID_ADDIDATA,
5549 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5550 PCI_ANY_ID,
5551 PCI_ANY_ID,
5552 0,
5553 0,
5554 pbn_b0_4_115200 },
5555
5556 { PCI_VENDOR_ID_ADDIDATA,
5557 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5558 PCI_ANY_ID,
5559 PCI_ANY_ID,
5560 0,
5561 0,
5562 pbn_b0_2_115200 },
5563
5564 { PCI_VENDOR_ID_ADDIDATA,
5565 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5566 PCI_ANY_ID,
5567 PCI_ANY_ID,
5568 0,
5569 0,
5570 pbn_b0_1_115200 },
5571
5572 { PCI_VENDOR_ID_ADDIDATA,
5573 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5574 PCI_ANY_ID,
5575 PCI_ANY_ID,
5576 0,
5577 0,
5578 pbn_b0_4_115200 },
5579
5580 { PCI_VENDOR_ID_ADDIDATA,
5581 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5582 PCI_ANY_ID,
5583 PCI_ANY_ID,
5584 0,
5585 0,
5586 pbn_b0_2_115200 },
5587
5588 { PCI_VENDOR_ID_ADDIDATA,
5589 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5590 PCI_ANY_ID,
5591 PCI_ANY_ID,
5592 0,
5593 0,
5594 pbn_b0_1_115200 },
5595
5596 { PCI_VENDOR_ID_ADDIDATA,
5597 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5598 PCI_ANY_ID,
5599 PCI_ANY_ID,
5600 0,
5601 0,
5602 pbn_b0_8_115200 },
5603
5604 { PCI_VENDOR_ID_ADDIDATA,
5605 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5606 PCI_ANY_ID,
5607 PCI_ANY_ID,
5608 0,
5609 0,
5610 pbn_ADDIDATA_PCIe_4_3906250 },
5611
5612 { PCI_VENDOR_ID_ADDIDATA,
5613 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5614 PCI_ANY_ID,
5615 PCI_ANY_ID,
5616 0,
5617 0,
5618 pbn_ADDIDATA_PCIe_2_3906250 },
5619
5620 { PCI_VENDOR_ID_ADDIDATA,
5621 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5622 PCI_ANY_ID,
5623 PCI_ANY_ID,
5624 0,
5625 0,
5626 pbn_ADDIDATA_PCIe_1_3906250 },
5627
5628 { PCI_VENDOR_ID_ADDIDATA,
5629 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5630 PCI_ANY_ID,
5631 PCI_ANY_ID,
5632 0,
5633 0,
5634 pbn_ADDIDATA_PCIe_8_3906250 },
5635
5636 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5637 PCI_VENDOR_ID_IBM, 0x0299,
5638 0, 0, pbn_b0_bt_2_115200 },
5639
5640 /*
5641 * other NetMos 9835 devices are most likely handled by the
5642 * parport_serial driver, check drivers/parport/parport_serial.c
5643 * before adding them here.
5644 */
5645
5646 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5647 0xA000, 0x1000,
5648 0, 0, pbn_b0_1_115200 },
5649
5650 /* the 9901 is a rebranded 9912 */
5651 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5652 0xA000, 0x1000,
5653 0, 0, pbn_b0_1_115200 },
5654
5655 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5656 0xA000, 0x1000,
5657 0, 0, pbn_b0_1_115200 },
5658
5659 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5660 0xA000, 0x1000,
5661 0, 0, pbn_b0_1_115200 },
5662
5663 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5664 0xA000, 0x1000,
5665 0, 0, pbn_b0_1_115200 },
5666
5667 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5668 0xA000, 0x3002,
5669 0, 0, pbn_NETMOS9900_2s_115200 },
5670
5671 /*
5672 * Best Connectivity and Rosewill PCI Multi I/O cards
5673 */
5674
5675 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5676 0xA000, 0x1000,
5677 0, 0, pbn_b0_1_115200 },
5678
5679 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5680 0xA000, 0x3002,
5681 0, 0, pbn_b0_bt_2_115200 },
5682
5683 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5684 0xA000, 0x3004,
5685 0, 0, pbn_b0_bt_4_115200 },
5686 /* Intel CE4100 */
5687 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5688 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5689 pbn_ce4100_1_115200 },
5690
5691 /*
5692 * Cronyx Omega PCI
5693 */
5694 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5695 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5696 pbn_omegapci },
5697
5698 /*
5699 * Broadcom TruManage
5700 */
5701 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5702 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5703 pbn_brcm_trumanage },
5704
5705 /*
5706 * AgeStar as-prs2-009
5707 */
5708 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5709 PCI_ANY_ID, PCI_ANY_ID,
5710 0, 0, pbn_b0_bt_2_115200 },
5711
5712 /*
5713 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5714 * so not listed here.
5715 */
5716 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5717 PCI_ANY_ID, PCI_ANY_ID,
5718 0, 0, pbn_b0_bt_4_115200 },
5719
5720 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5721 PCI_ANY_ID, PCI_ANY_ID,
5722 0, 0, pbn_b0_bt_2_115200 },
5723
5724 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
5725 PCI_ANY_ID, PCI_ANY_ID,
5726 0, 0, pbn_b0_bt_4_115200 },
5727
5728 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5729 PCI_ANY_ID, PCI_ANY_ID,
5730 0, 0, pbn_wch382_2 },
5731
5732 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5733 PCI_ANY_ID, PCI_ANY_ID,
5734 0, 0, pbn_wch384_4 },
5735
5736 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S,
5737 PCI_ANY_ID, PCI_ANY_ID,
5738 0, 0, pbn_wch384_8 },
5739 /*
5740 * Realtek RealManage
5741 */
5742 { PCI_VENDOR_ID_REALTEK, 0x816a,
5743 PCI_ANY_ID, PCI_ANY_ID,
5744 0, 0, pbn_b0_1_115200 },
5745
5746 { PCI_VENDOR_ID_REALTEK, 0x816b,
5747 PCI_ANY_ID, PCI_ANY_ID,
5748 0, 0, pbn_b0_1_115200 },
5749
5750 /* Fintek PCI serial cards */
5751 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5752 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5753 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5754 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A },
5755 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A },
5756 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A },
5757
5758 /* MKS Tenta SCOM-080x serial cards */
5759 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
5760 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
5761
5762 /* Amazon PCI serial device */
5763 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
5764
5765 /*
5766 * These entries match devices with class COMMUNICATION_SERIAL,
5767 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5768 */
5769 { PCI_ANY_ID, PCI_ANY_ID,
5770 PCI_ANY_ID, PCI_ANY_ID,
5771 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5772 0xffff00, pbn_default },
5773 { PCI_ANY_ID, PCI_ANY_ID,
5774 PCI_ANY_ID, PCI_ANY_ID,
5775 PCI_CLASS_COMMUNICATION_MODEM << 8,
5776 0xffff00, pbn_default },
5777 { PCI_ANY_ID, PCI_ANY_ID,
5778 PCI_ANY_ID, PCI_ANY_ID,
5779 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5780 0xffff00, pbn_default },
5781 { 0, }
5782 };
5783
serial8250_io_error_detected(struct pci_dev * dev,pci_channel_state_t state)5784 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5785 pci_channel_state_t state)
5786 {
5787 struct serial_private *priv = pci_get_drvdata(dev);
5788
5789 if (state == pci_channel_io_perm_failure)
5790 return PCI_ERS_RESULT_DISCONNECT;
5791
5792 if (priv)
5793 pciserial_detach_ports(priv);
5794
5795 pci_disable_device(dev);
5796
5797 return PCI_ERS_RESULT_NEED_RESET;
5798 }
5799
serial8250_io_slot_reset(struct pci_dev * dev)5800 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5801 {
5802 int rc;
5803
5804 rc = pci_enable_device(dev);
5805
5806 if (rc)
5807 return PCI_ERS_RESULT_DISCONNECT;
5808
5809 pci_restore_state(dev);
5810 pci_save_state(dev);
5811
5812 return PCI_ERS_RESULT_RECOVERED;
5813 }
5814
serial8250_io_resume(struct pci_dev * dev)5815 static void serial8250_io_resume(struct pci_dev *dev)
5816 {
5817 struct serial_private *priv = pci_get_drvdata(dev);
5818 struct serial_private *new;
5819
5820 if (!priv)
5821 return;
5822
5823 new = pciserial_init_ports(dev, priv->board);
5824 if (!IS_ERR(new)) {
5825 pci_set_drvdata(dev, new);
5826 kfree(priv);
5827 }
5828 }
5829
5830 static const struct pci_error_handlers serial8250_err_handler = {
5831 .error_detected = serial8250_io_error_detected,
5832 .slot_reset = serial8250_io_slot_reset,
5833 .resume = serial8250_io_resume,
5834 };
5835
5836 static struct pci_driver serial_pci_driver = {
5837 .name = "serial",
5838 .probe = pciserial_init_one,
5839 .remove = pciserial_remove_one,
5840 .driver = {
5841 .pm = &pciserial_pm_ops,
5842 },
5843 .id_table = serial_pci_tbl,
5844 .err_handler = &serial8250_err_handler,
5845 };
5846
5847 module_pci_driver(serial_pci_driver);
5848
5849 MODULE_LICENSE("GPL");
5850 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5851 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
5852