1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Serial Port driver for Open Firmware platform devices
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2006 Arnd Bergmann <arnd@arndb.de>, IBM Corp.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <linux/console.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/slab.h>
10*4882a593Smuzhiyun #include <linux/serial_core.h>
11*4882a593Smuzhiyun #include <linux/serial_reg.h>
12*4882a593Smuzhiyun #include <linux/of_address.h>
13*4882a593Smuzhiyun #include <linux/of_irq.h>
14*4882a593Smuzhiyun #include <linux/of_platform.h>
15*4882a593Smuzhiyun #include <linux/pm_runtime.h>
16*4882a593Smuzhiyun #include <linux/clk.h>
17*4882a593Smuzhiyun #include <linux/reset.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include "8250.h"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun struct of_serial_info {
22*4882a593Smuzhiyun struct clk *clk;
23*4882a593Smuzhiyun struct reset_control *rst;
24*4882a593Smuzhiyun int type;
25*4882a593Smuzhiyun int line;
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /*
29*4882a593Smuzhiyun * Fill a struct uart_port for a given device node
30*4882a593Smuzhiyun */
of_platform_serial_setup(struct platform_device * ofdev,int type,struct uart_8250_port * up,struct of_serial_info * info)31*4882a593Smuzhiyun static int of_platform_serial_setup(struct platform_device *ofdev,
32*4882a593Smuzhiyun int type, struct uart_8250_port *up,
33*4882a593Smuzhiyun struct of_serial_info *info)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun struct resource resource;
36*4882a593Smuzhiyun struct device_node *np = ofdev->dev.of_node;
37*4882a593Smuzhiyun struct uart_port *port = &up->port;
38*4882a593Smuzhiyun u32 clk, spd, prop;
39*4882a593Smuzhiyun int ret, irq;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun memset(port, 0, sizeof *port);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun pm_runtime_enable(&ofdev->dev);
44*4882a593Smuzhiyun pm_runtime_get_sync(&ofdev->dev);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun if (of_property_read_u32(np, "clock-frequency", &clk)) {
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* Get clk rate through clk driver if present */
49*4882a593Smuzhiyun info->clk = devm_clk_get(&ofdev->dev, NULL);
50*4882a593Smuzhiyun if (IS_ERR(info->clk)) {
51*4882a593Smuzhiyun ret = PTR_ERR(info->clk);
52*4882a593Smuzhiyun if (ret != -EPROBE_DEFER)
53*4882a593Smuzhiyun dev_warn(&ofdev->dev,
54*4882a593Smuzhiyun "failed to get clock: %d\n", ret);
55*4882a593Smuzhiyun goto err_pmruntime;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun ret = clk_prepare_enable(info->clk);
59*4882a593Smuzhiyun if (ret < 0)
60*4882a593Smuzhiyun goto err_pmruntime;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun clk = clk_get_rate(info->clk);
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun /* If current-speed was set, then try not to change it. */
65*4882a593Smuzhiyun if (of_property_read_u32(np, "current-speed", &spd) == 0)
66*4882a593Smuzhiyun port->custom_divisor = clk / (16 * spd);
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun ret = of_address_to_resource(np, 0, &resource);
69*4882a593Smuzhiyun if (ret) {
70*4882a593Smuzhiyun dev_warn(&ofdev->dev, "invalid address\n");
71*4882a593Smuzhiyun goto err_unprepare;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT |
75*4882a593Smuzhiyun UPF_FIXED_TYPE;
76*4882a593Smuzhiyun spin_lock_init(&port->lock);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun if (resource_type(&resource) == IORESOURCE_IO) {
79*4882a593Smuzhiyun port->iotype = UPIO_PORT;
80*4882a593Smuzhiyun port->iobase = resource.start;
81*4882a593Smuzhiyun } else {
82*4882a593Smuzhiyun port->mapbase = resource.start;
83*4882a593Smuzhiyun port->mapsize = resource_size(&resource);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* Check for shifted address mapping */
86*4882a593Smuzhiyun if (of_property_read_u32(np, "reg-offset", &prop) == 0) {
87*4882a593Smuzhiyun if (prop >= port->mapsize) {
88*4882a593Smuzhiyun dev_warn(&ofdev->dev, "reg-offset %u exceeds region size %pa\n",
89*4882a593Smuzhiyun prop, &port->mapsize);
90*4882a593Smuzhiyun ret = -EINVAL;
91*4882a593Smuzhiyun goto err_unprepare;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun port->mapbase += prop;
95*4882a593Smuzhiyun port->mapsize -= prop;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun port->iotype = UPIO_MEM;
99*4882a593Smuzhiyun if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
100*4882a593Smuzhiyun switch (prop) {
101*4882a593Smuzhiyun case 1:
102*4882a593Smuzhiyun port->iotype = UPIO_MEM;
103*4882a593Smuzhiyun break;
104*4882a593Smuzhiyun case 2:
105*4882a593Smuzhiyun port->iotype = UPIO_MEM16;
106*4882a593Smuzhiyun break;
107*4882a593Smuzhiyun case 4:
108*4882a593Smuzhiyun port->iotype = of_device_is_big_endian(np) ?
109*4882a593Smuzhiyun UPIO_MEM32BE : UPIO_MEM32;
110*4882a593Smuzhiyun break;
111*4882a593Smuzhiyun default:
112*4882a593Smuzhiyun dev_warn(&ofdev->dev, "unsupported reg-io-width (%d)\n",
113*4882a593Smuzhiyun prop);
114*4882a593Smuzhiyun ret = -EINVAL;
115*4882a593Smuzhiyun goto err_unprepare;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun port->flags |= UPF_IOREMAP;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun /* Compatibility with the deprecated pxa driver and 8250_pxa drivers. */
122*4882a593Smuzhiyun if (of_device_is_compatible(np, "mrvl,mmp-uart"))
123*4882a593Smuzhiyun port->regshift = 2;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun /* Check for registers offset within the devices address range */
126*4882a593Smuzhiyun if (of_property_read_u32(np, "reg-shift", &prop) == 0)
127*4882a593Smuzhiyun port->regshift = prop;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun /* Check for fifo size */
130*4882a593Smuzhiyun if (of_property_read_u32(np, "fifo-size", &prop) == 0)
131*4882a593Smuzhiyun port->fifosize = prop;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun /* Check for a fixed line number */
134*4882a593Smuzhiyun ret = of_alias_get_id(np, "serial");
135*4882a593Smuzhiyun if (ret >= 0)
136*4882a593Smuzhiyun port->line = ret;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun irq = of_irq_get(np, 0);
139*4882a593Smuzhiyun if (irq < 0) {
140*4882a593Smuzhiyun if (irq == -EPROBE_DEFER) {
141*4882a593Smuzhiyun ret = -EPROBE_DEFER;
142*4882a593Smuzhiyun goto err_unprepare;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun /* IRQ support not mandatory */
145*4882a593Smuzhiyun irq = 0;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun port->irq = irq;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun info->rst = devm_reset_control_get_optional_shared(&ofdev->dev, NULL);
151*4882a593Smuzhiyun if (IS_ERR(info->rst)) {
152*4882a593Smuzhiyun ret = PTR_ERR(info->rst);
153*4882a593Smuzhiyun goto err_unprepare;
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun ret = reset_control_deassert(info->rst);
157*4882a593Smuzhiyun if (ret)
158*4882a593Smuzhiyun goto err_unprepare;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun port->type = type;
161*4882a593Smuzhiyun port->uartclk = clk;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun if (of_property_read_bool(np, "no-loopback-test"))
164*4882a593Smuzhiyun port->flags |= UPF_SKIP_TEST;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun port->dev = &ofdev->dev;
167*4882a593Smuzhiyun port->rs485_config = serial8250_em485_config;
168*4882a593Smuzhiyun up->rs485_start_tx = serial8250_em485_start_tx;
169*4882a593Smuzhiyun up->rs485_stop_tx = serial8250_em485_stop_tx;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun switch (type) {
172*4882a593Smuzhiyun case PORT_RT2880:
173*4882a593Smuzhiyun port->iotype = UPIO_AU;
174*4882a593Smuzhiyun break;
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_SERIAL_8250_FSL) &&
178*4882a593Smuzhiyun (of_device_is_compatible(np, "fsl,ns16550") ||
179*4882a593Smuzhiyun of_device_is_compatible(np, "fsl,16550-FIFO64"))) {
180*4882a593Smuzhiyun port->handle_irq = fsl8250_handle_irq;
181*4882a593Smuzhiyun port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun return 0;
185*4882a593Smuzhiyun err_unprepare:
186*4882a593Smuzhiyun clk_disable_unprepare(info->clk);
187*4882a593Smuzhiyun err_pmruntime:
188*4882a593Smuzhiyun pm_runtime_put_sync(&ofdev->dev);
189*4882a593Smuzhiyun pm_runtime_disable(&ofdev->dev);
190*4882a593Smuzhiyun return ret;
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun /*
194*4882a593Smuzhiyun * Try to register a serial port
195*4882a593Smuzhiyun */
of_platform_serial_probe(struct platform_device * ofdev)196*4882a593Smuzhiyun static int of_platform_serial_probe(struct platform_device *ofdev)
197*4882a593Smuzhiyun {
198*4882a593Smuzhiyun struct of_serial_info *info;
199*4882a593Smuzhiyun struct uart_8250_port port8250;
200*4882a593Smuzhiyun unsigned int port_type;
201*4882a593Smuzhiyun u32 tx_threshold;
202*4882a593Smuzhiyun int ret;
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun port_type = (unsigned long)of_device_get_match_data(&ofdev->dev);
205*4882a593Smuzhiyun if (port_type == PORT_UNKNOWN)
206*4882a593Smuzhiyun return -EINVAL;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun if (of_property_read_bool(ofdev->dev.of_node, "used-by-rtas"))
209*4882a593Smuzhiyun return -EBUSY;
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun info = kzalloc(sizeof(*info), GFP_KERNEL);
212*4882a593Smuzhiyun if (info == NULL)
213*4882a593Smuzhiyun return -ENOMEM;
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun memset(&port8250, 0, sizeof(port8250));
216*4882a593Smuzhiyun ret = of_platform_serial_setup(ofdev, port_type, &port8250, info);
217*4882a593Smuzhiyun if (ret)
218*4882a593Smuzhiyun goto err_free;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun if (port8250.port.fifosize)
221*4882a593Smuzhiyun port8250.capabilities = UART_CAP_FIFO;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun /* Check for TX FIFO threshold & set tx_loadsz */
224*4882a593Smuzhiyun if ((of_property_read_u32(ofdev->dev.of_node, "tx-threshold",
225*4882a593Smuzhiyun &tx_threshold) == 0) &&
226*4882a593Smuzhiyun (tx_threshold < port8250.port.fifosize))
227*4882a593Smuzhiyun port8250.tx_loadsz = port8250.port.fifosize - tx_threshold;
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun if (of_property_read_bool(ofdev->dev.of_node, "auto-flow-control"))
230*4882a593Smuzhiyun port8250.capabilities |= UART_CAP_AFE;
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun if (of_property_read_u32(ofdev->dev.of_node,
233*4882a593Smuzhiyun "overrun-throttle-ms",
234*4882a593Smuzhiyun &port8250.overrun_backoff_time_ms) != 0)
235*4882a593Smuzhiyun port8250.overrun_backoff_time_ms = 0;
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun ret = serial8250_register_8250_port(&port8250);
238*4882a593Smuzhiyun if (ret < 0)
239*4882a593Smuzhiyun goto err_dispose;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun info->type = port_type;
242*4882a593Smuzhiyun info->line = ret;
243*4882a593Smuzhiyun platform_set_drvdata(ofdev, info);
244*4882a593Smuzhiyun return 0;
245*4882a593Smuzhiyun err_dispose:
246*4882a593Smuzhiyun irq_dispose_mapping(port8250.port.irq);
247*4882a593Smuzhiyun pm_runtime_put_sync(&ofdev->dev);
248*4882a593Smuzhiyun pm_runtime_disable(&ofdev->dev);
249*4882a593Smuzhiyun clk_disable_unprepare(info->clk);
250*4882a593Smuzhiyun err_free:
251*4882a593Smuzhiyun kfree(info);
252*4882a593Smuzhiyun return ret;
253*4882a593Smuzhiyun }
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun /*
256*4882a593Smuzhiyun * Release a line
257*4882a593Smuzhiyun */
of_platform_serial_remove(struct platform_device * ofdev)258*4882a593Smuzhiyun static int of_platform_serial_remove(struct platform_device *ofdev)
259*4882a593Smuzhiyun {
260*4882a593Smuzhiyun struct of_serial_info *info = platform_get_drvdata(ofdev);
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun serial8250_unregister_port(info->line);
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun reset_control_assert(info->rst);
265*4882a593Smuzhiyun pm_runtime_put_sync(&ofdev->dev);
266*4882a593Smuzhiyun pm_runtime_disable(&ofdev->dev);
267*4882a593Smuzhiyun clk_disable_unprepare(info->clk);
268*4882a593Smuzhiyun kfree(info);
269*4882a593Smuzhiyun return 0;
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
of_serial_suspend(struct device * dev)273*4882a593Smuzhiyun static int of_serial_suspend(struct device *dev)
274*4882a593Smuzhiyun {
275*4882a593Smuzhiyun struct of_serial_info *info = dev_get_drvdata(dev);
276*4882a593Smuzhiyun struct uart_8250_port *port8250 = serial8250_get_port(info->line);
277*4882a593Smuzhiyun struct uart_port *port = &port8250->port;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun serial8250_suspend_port(info->line);
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun if (!uart_console(port) || console_suspend_enabled) {
282*4882a593Smuzhiyun pm_runtime_put_sync(dev);
283*4882a593Smuzhiyun clk_disable_unprepare(info->clk);
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun return 0;
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun
of_serial_resume(struct device * dev)288*4882a593Smuzhiyun static int of_serial_resume(struct device *dev)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun struct of_serial_info *info = dev_get_drvdata(dev);
291*4882a593Smuzhiyun struct uart_8250_port *port8250 = serial8250_get_port(info->line);
292*4882a593Smuzhiyun struct uart_port *port = &port8250->port;
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun if (!uart_console(port) || console_suspend_enabled) {
295*4882a593Smuzhiyun pm_runtime_get_sync(dev);
296*4882a593Smuzhiyun clk_prepare_enable(info->clk);
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun serial8250_resume_port(info->line);
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun return 0;
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun #endif
304*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(of_serial_pm_ops, of_serial_suspend, of_serial_resume);
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun /*
307*4882a593Smuzhiyun * A few common types, add more as needed.
308*4882a593Smuzhiyun */
309*4882a593Smuzhiyun static const struct of_device_id of_platform_serial_table[] = {
310*4882a593Smuzhiyun { .compatible = "ns8250", .data = (void *)PORT_8250, },
311*4882a593Smuzhiyun { .compatible = "ns16450", .data = (void *)PORT_16450, },
312*4882a593Smuzhiyun { .compatible = "ns16550a", .data = (void *)PORT_16550A, },
313*4882a593Smuzhiyun { .compatible = "ns16550", .data = (void *)PORT_16550, },
314*4882a593Smuzhiyun { .compatible = "ns16750", .data = (void *)PORT_16750, },
315*4882a593Smuzhiyun { .compatible = "ns16850", .data = (void *)PORT_16850, },
316*4882a593Smuzhiyun { .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, },
317*4882a593Smuzhiyun { .compatible = "ralink,rt2880-uart", .data = (void *)PORT_RT2880, },
318*4882a593Smuzhiyun { .compatible = "intel,xscale-uart", .data = (void *)PORT_XSCALE, },
319*4882a593Smuzhiyun { .compatible = "altr,16550-FIFO32",
320*4882a593Smuzhiyun .data = (void *)PORT_ALTR_16550_F32, },
321*4882a593Smuzhiyun { .compatible = "altr,16550-FIFO64",
322*4882a593Smuzhiyun .data = (void *)PORT_ALTR_16550_F64, },
323*4882a593Smuzhiyun { .compatible = "altr,16550-FIFO128",
324*4882a593Smuzhiyun .data = (void *)PORT_ALTR_16550_F128, },
325*4882a593Smuzhiyun { .compatible = "mediatek,mtk-btif",
326*4882a593Smuzhiyun .data = (void *)PORT_MTK_BTIF, },
327*4882a593Smuzhiyun { .compatible = "mrvl,mmp-uart",
328*4882a593Smuzhiyun .data = (void *)PORT_XSCALE, },
329*4882a593Smuzhiyun { .compatible = "ti,da830-uart", .data = (void *)PORT_DA830, },
330*4882a593Smuzhiyun { .compatible = "nuvoton,npcm750-uart", .data = (void *)PORT_NPCM, },
331*4882a593Smuzhiyun { /* end of list */ },
332*4882a593Smuzhiyun };
333*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, of_platform_serial_table);
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun static struct platform_driver of_platform_serial_driver = {
336*4882a593Smuzhiyun .driver = {
337*4882a593Smuzhiyun .name = "of_serial",
338*4882a593Smuzhiyun .of_match_table = of_platform_serial_table,
339*4882a593Smuzhiyun .pm = &of_serial_pm_ops,
340*4882a593Smuzhiyun },
341*4882a593Smuzhiyun .probe = of_platform_serial_probe,
342*4882a593Smuzhiyun .remove = of_platform_serial_remove,
343*4882a593Smuzhiyun };
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun module_platform_driver(of_platform_serial_driver);
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun MODULE_AUTHOR("Arnd Bergmann <arnd@arndb.de>");
348*4882a593Smuzhiyun MODULE_LICENSE("GPL");
349*4882a593Smuzhiyun MODULE_DESCRIPTION("Serial Port driver for Open Firmware platform devices");
350