xref: /OK3568_Linux_fs/kernel/drivers/tty/serial/8250/8250_mtk.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Mediatek 8250 driver.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2014 MundoReader S.L.
6*4882a593Smuzhiyun  * Author: Matthias Brugger <matthias.bgg@gmail.com>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun #include <linux/clk.h>
9*4882a593Smuzhiyun #include <linux/io.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/of_irq.h>
12*4882a593Smuzhiyun #include <linux/of_platform.h>
13*4882a593Smuzhiyun #include <linux/pinctrl/consumer.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/pm_runtime.h>
16*4882a593Smuzhiyun #include <linux/serial_8250.h>
17*4882a593Smuzhiyun #include <linux/serial_reg.h>
18*4882a593Smuzhiyun #include <linux/console.h>
19*4882a593Smuzhiyun #include <linux/dma-mapping.h>
20*4882a593Smuzhiyun #include <linux/tty.h>
21*4882a593Smuzhiyun #include <linux/tty_flip.h>
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #include "8250.h"
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #define MTK_UART_HIGHS		0x09	/* Highspeed register */
26*4882a593Smuzhiyun #define MTK_UART_SAMPLE_COUNT	0x0a	/* Sample count register */
27*4882a593Smuzhiyun #define MTK_UART_SAMPLE_POINT	0x0b	/* Sample point register */
28*4882a593Smuzhiyun #define MTK_UART_RATE_FIX	0x0d	/* UART Rate Fix Register */
29*4882a593Smuzhiyun #define MTK_UART_ESCAPE_DAT	0x10	/* Escape Character register */
30*4882a593Smuzhiyun #define MTK_UART_ESCAPE_EN	0x11	/* Escape Enable register */
31*4882a593Smuzhiyun #define MTK_UART_DMA_EN		0x13	/* DMA Enable register */
32*4882a593Smuzhiyun #define MTK_UART_RXTRI_AD	0x14	/* RX Trigger address */
33*4882a593Smuzhiyun #define MTK_UART_FRACDIV_L	0x15	/* Fractional divider LSB address */
34*4882a593Smuzhiyun #define MTK_UART_FRACDIV_M	0x16	/* Fractional divider MSB address */
35*4882a593Smuzhiyun #define MTK_UART_DEBUG0	0x18
36*4882a593Smuzhiyun #define MTK_UART_IER_XOFFI	0x20	/* Enable XOFF character interrupt */
37*4882a593Smuzhiyun #define MTK_UART_IER_RTSI	0x40	/* Enable RTS Modem status interrupt */
38*4882a593Smuzhiyun #define MTK_UART_IER_CTSI	0x80	/* Enable CTS Modem status interrupt */
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun #define MTK_UART_EFR		38	/* I/O: Extended Features Register */
41*4882a593Smuzhiyun #define MTK_UART_EFR_EN		0x10	/* Enable enhancement feature */
42*4882a593Smuzhiyun #define MTK_UART_EFR_RTS	0x40	/* Enable hardware rx flow control */
43*4882a593Smuzhiyun #define MTK_UART_EFR_CTS	0x80	/* Enable hardware tx flow control */
44*4882a593Smuzhiyun #define MTK_UART_EFR_NO_SW_FC	0x0	/* no sw flow control */
45*4882a593Smuzhiyun #define MTK_UART_EFR_XON1_XOFF1	0xa	/* XON1/XOFF1 as sw flow control */
46*4882a593Smuzhiyun #define MTK_UART_EFR_XON2_XOFF2	0x5	/* XON2/XOFF2 as sw flow control */
47*4882a593Smuzhiyun #define MTK_UART_EFR_SW_FC_MASK	0xf	/* Enable CTS Modem status interrupt */
48*4882a593Smuzhiyun #define MTK_UART_EFR_HW_FC	(MTK_UART_EFR_RTS | MTK_UART_EFR_CTS)
49*4882a593Smuzhiyun #define MTK_UART_DMA_EN_TX	0x2
50*4882a593Smuzhiyun #define MTK_UART_DMA_EN_RX	0x5
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun #define MTK_UART_ESCAPE_CHAR	0x77	/* Escape char added under sw fc */
53*4882a593Smuzhiyun #define MTK_UART_RX_SIZE	0x8000
54*4882a593Smuzhiyun #define MTK_UART_TX_TRIGGER	1
55*4882a593Smuzhiyun #define MTK_UART_RX_TRIGGER	MTK_UART_RX_SIZE
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun #define MTK_UART_XON1		40	/* I/O: Xon character 1 */
58*4882a593Smuzhiyun #define MTK_UART_XOFF1		42	/* I/O: Xoff character 1 */
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_8250_DMA
61*4882a593Smuzhiyun enum dma_rx_status {
62*4882a593Smuzhiyun 	DMA_RX_START = 0,
63*4882a593Smuzhiyun 	DMA_RX_RUNNING = 1,
64*4882a593Smuzhiyun 	DMA_RX_SHUTDOWN = 2,
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun #endif
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun struct mtk8250_data {
69*4882a593Smuzhiyun 	int			line;
70*4882a593Smuzhiyun 	unsigned int		rx_pos;
71*4882a593Smuzhiyun 	unsigned int		clk_count;
72*4882a593Smuzhiyun 	struct clk		*uart_clk;
73*4882a593Smuzhiyun 	struct clk		*bus_clk;
74*4882a593Smuzhiyun 	struct uart_8250_dma	*dma;
75*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_8250_DMA
76*4882a593Smuzhiyun 	enum dma_rx_status	rx_status;
77*4882a593Smuzhiyun #endif
78*4882a593Smuzhiyun 	int			rx_wakeup_irq;
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun /* flow control mode */
82*4882a593Smuzhiyun enum {
83*4882a593Smuzhiyun 	MTK_UART_FC_NONE,
84*4882a593Smuzhiyun 	MTK_UART_FC_SW,
85*4882a593Smuzhiyun 	MTK_UART_FC_HW,
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_8250_DMA
89*4882a593Smuzhiyun static void mtk8250_rx_dma(struct uart_8250_port *up);
90*4882a593Smuzhiyun 
mtk8250_dma_rx_complete(void * param)91*4882a593Smuzhiyun static void mtk8250_dma_rx_complete(void *param)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun 	struct uart_8250_port *up = param;
94*4882a593Smuzhiyun 	struct uart_8250_dma *dma = up->dma;
95*4882a593Smuzhiyun 	struct mtk8250_data *data = up->port.private_data;
96*4882a593Smuzhiyun 	struct tty_port *tty_port = &up->port.state->port;
97*4882a593Smuzhiyun 	struct dma_tx_state state;
98*4882a593Smuzhiyun 	int copied, total, cnt;
99*4882a593Smuzhiyun 	unsigned char *ptr;
100*4882a593Smuzhiyun 	unsigned long flags;
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	if (data->rx_status == DMA_RX_SHUTDOWN)
103*4882a593Smuzhiyun 		return;
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	spin_lock_irqsave(&up->port.lock, flags);
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
108*4882a593Smuzhiyun 	total = dma->rx_size - state.residue;
109*4882a593Smuzhiyun 	cnt = total;
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	if ((data->rx_pos + cnt) > dma->rx_size)
112*4882a593Smuzhiyun 		cnt = dma->rx_size - data->rx_pos;
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	ptr = (unsigned char *)(data->rx_pos + dma->rx_buf);
115*4882a593Smuzhiyun 	copied = tty_insert_flip_string(tty_port, ptr, cnt);
116*4882a593Smuzhiyun 	data->rx_pos += cnt;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	if (total > cnt) {
119*4882a593Smuzhiyun 		ptr = (unsigned char *)(dma->rx_buf);
120*4882a593Smuzhiyun 		cnt = total - cnt;
121*4882a593Smuzhiyun 		copied += tty_insert_flip_string(tty_port, ptr, cnt);
122*4882a593Smuzhiyun 		data->rx_pos = cnt;
123*4882a593Smuzhiyun 	}
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	up->port.icount.rx += copied;
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 	tty_flip_buffer_push(tty_port);
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	mtk8250_rx_dma(up);
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	spin_unlock_irqrestore(&up->port.lock, flags);
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun 
mtk8250_rx_dma(struct uart_8250_port * up)134*4882a593Smuzhiyun static void mtk8250_rx_dma(struct uart_8250_port *up)
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun 	struct uart_8250_dma *dma = up->dma;
137*4882a593Smuzhiyun 	struct dma_async_tx_descriptor	*desc;
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
140*4882a593Smuzhiyun 					   dma->rx_size, DMA_DEV_TO_MEM,
141*4882a593Smuzhiyun 					   DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
142*4882a593Smuzhiyun 	if (!desc) {
143*4882a593Smuzhiyun 		pr_err("failed to prepare rx slave single\n");
144*4882a593Smuzhiyun 		return;
145*4882a593Smuzhiyun 	}
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	desc->callback = mtk8250_dma_rx_complete;
148*4882a593Smuzhiyun 	desc->callback_param = up;
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	dma->rx_cookie = dmaengine_submit(desc);
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	dma_async_issue_pending(dma->rxchan);
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun 
mtk8250_dma_enable(struct uart_8250_port * up)155*4882a593Smuzhiyun static void mtk8250_dma_enable(struct uart_8250_port *up)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun 	struct uart_8250_dma *dma = up->dma;
158*4882a593Smuzhiyun 	struct mtk8250_data *data = up->port.private_data;
159*4882a593Smuzhiyun 	int lcr = serial_in(up, UART_LCR);
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	if (data->rx_status != DMA_RX_START)
162*4882a593Smuzhiyun 		return;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	dma->rxconf.src_port_window_size	= dma->rx_size;
165*4882a593Smuzhiyun 	dma->rxconf.src_addr				= dma->rx_addr;
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	dma->txconf.dst_port_window_size	= UART_XMIT_SIZE;
168*4882a593Smuzhiyun 	dma->txconf.dst_addr				= dma->tx_addr;
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
171*4882a593Smuzhiyun 		UART_FCR_CLEAR_XMIT);
172*4882a593Smuzhiyun 	serial_out(up, MTK_UART_DMA_EN,
173*4882a593Smuzhiyun 		   MTK_UART_DMA_EN_RX | MTK_UART_DMA_EN_TX);
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
176*4882a593Smuzhiyun 	serial_out(up, MTK_UART_EFR, UART_EFR_ECB);
177*4882a593Smuzhiyun 	serial_out(up, UART_LCR, lcr);
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 	if (dmaengine_slave_config(dma->rxchan, &dma->rxconf) != 0)
180*4882a593Smuzhiyun 		pr_err("failed to configure rx dma channel\n");
181*4882a593Smuzhiyun 	if (dmaengine_slave_config(dma->txchan, &dma->txconf) != 0)
182*4882a593Smuzhiyun 		pr_err("failed to configure tx dma channel\n");
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	data->rx_status = DMA_RX_RUNNING;
185*4882a593Smuzhiyun 	data->rx_pos = 0;
186*4882a593Smuzhiyun 	mtk8250_rx_dma(up);
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun #endif
189*4882a593Smuzhiyun 
mtk8250_startup(struct uart_port * port)190*4882a593Smuzhiyun static int mtk8250_startup(struct uart_port *port)
191*4882a593Smuzhiyun {
192*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_8250_DMA
193*4882a593Smuzhiyun 	struct uart_8250_port *up = up_to_u8250p(port);
194*4882a593Smuzhiyun 	struct mtk8250_data *data = port->private_data;
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	/* disable DMA for console */
197*4882a593Smuzhiyun 	if (uart_console(port))
198*4882a593Smuzhiyun 		up->dma = NULL;
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	if (up->dma) {
201*4882a593Smuzhiyun 		data->rx_status = DMA_RX_START;
202*4882a593Smuzhiyun 		uart_circ_clear(&port->state->xmit);
203*4882a593Smuzhiyun 	}
204*4882a593Smuzhiyun #endif
205*4882a593Smuzhiyun 	memset(&port->icount, 0, sizeof(port->icount));
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	return serial8250_do_startup(port);
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun 
mtk8250_shutdown(struct uart_port * port)210*4882a593Smuzhiyun static void mtk8250_shutdown(struct uart_port *port)
211*4882a593Smuzhiyun {
212*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_8250_DMA
213*4882a593Smuzhiyun 	struct uart_8250_port *up = up_to_u8250p(port);
214*4882a593Smuzhiyun 	struct mtk8250_data *data = port->private_data;
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	if (up->dma)
217*4882a593Smuzhiyun 		data->rx_status = DMA_RX_SHUTDOWN;
218*4882a593Smuzhiyun #endif
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 	return serial8250_do_shutdown(port);
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun 
mtk8250_disable_intrs(struct uart_8250_port * up,int mask)223*4882a593Smuzhiyun static void mtk8250_disable_intrs(struct uart_8250_port *up, int mask)
224*4882a593Smuzhiyun {
225*4882a593Smuzhiyun 	serial_out(up, UART_IER, serial_in(up, UART_IER) & (~mask));
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun 
mtk8250_enable_intrs(struct uart_8250_port * up,int mask)228*4882a593Smuzhiyun static void mtk8250_enable_intrs(struct uart_8250_port *up, int mask)
229*4882a593Smuzhiyun {
230*4882a593Smuzhiyun 	serial_out(up, UART_IER, serial_in(up, UART_IER) | mask);
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun 
mtk8250_set_flow_ctrl(struct uart_8250_port * up,int mode)233*4882a593Smuzhiyun static void mtk8250_set_flow_ctrl(struct uart_8250_port *up, int mode)
234*4882a593Smuzhiyun {
235*4882a593Smuzhiyun 	struct uart_port *port = &up->port;
236*4882a593Smuzhiyun 	int lcr = serial_in(up, UART_LCR);
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
239*4882a593Smuzhiyun 	serial_out(up, MTK_UART_EFR, UART_EFR_ECB);
240*4882a593Smuzhiyun 	serial_out(up, UART_LCR, lcr);
241*4882a593Smuzhiyun 	lcr = serial_in(up, UART_LCR);
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	switch (mode) {
244*4882a593Smuzhiyun 	case MTK_UART_FC_NONE:
245*4882a593Smuzhiyun 		serial_out(up, MTK_UART_ESCAPE_DAT, MTK_UART_ESCAPE_CHAR);
246*4882a593Smuzhiyun 		serial_out(up, MTK_UART_ESCAPE_EN, 0x00);
247*4882a593Smuzhiyun 		serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
248*4882a593Smuzhiyun 		serial_out(up, MTK_UART_EFR, serial_in(up, MTK_UART_EFR) &
249*4882a593Smuzhiyun 			(~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK)));
250*4882a593Smuzhiyun 		serial_out(up, UART_LCR, lcr);
251*4882a593Smuzhiyun 		mtk8250_disable_intrs(up, MTK_UART_IER_XOFFI |
252*4882a593Smuzhiyun 			MTK_UART_IER_RTSI | MTK_UART_IER_CTSI);
253*4882a593Smuzhiyun 		break;
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 	case MTK_UART_FC_HW:
256*4882a593Smuzhiyun 		serial_out(up, MTK_UART_ESCAPE_DAT, MTK_UART_ESCAPE_CHAR);
257*4882a593Smuzhiyun 		serial_out(up, MTK_UART_ESCAPE_EN, 0x00);
258*4882a593Smuzhiyun 		serial_out(up, UART_MCR, UART_MCR_RTS);
259*4882a593Smuzhiyun 		serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun 		/*enable hw flow control*/
262*4882a593Smuzhiyun 		serial_out(up, MTK_UART_EFR, MTK_UART_EFR_HW_FC |
263*4882a593Smuzhiyun 			(serial_in(up, MTK_UART_EFR) &
264*4882a593Smuzhiyun 			(~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK))));
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 		serial_out(up, UART_LCR, lcr);
267*4882a593Smuzhiyun 		mtk8250_disable_intrs(up, MTK_UART_IER_XOFFI);
268*4882a593Smuzhiyun 		mtk8250_enable_intrs(up, MTK_UART_IER_CTSI | MTK_UART_IER_RTSI);
269*4882a593Smuzhiyun 		break;
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	case MTK_UART_FC_SW:	/*MTK software flow control */
272*4882a593Smuzhiyun 		serial_out(up, MTK_UART_ESCAPE_DAT, MTK_UART_ESCAPE_CHAR);
273*4882a593Smuzhiyun 		serial_out(up, MTK_UART_ESCAPE_EN, 0x01);
274*4882a593Smuzhiyun 		serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 		/*enable sw flow control */
277*4882a593Smuzhiyun 		serial_out(up, MTK_UART_EFR, MTK_UART_EFR_XON1_XOFF1 |
278*4882a593Smuzhiyun 			(serial_in(up, MTK_UART_EFR) &
279*4882a593Smuzhiyun 			(~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK))));
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun 		serial_out(up, MTK_UART_XON1, START_CHAR(port->state->port.tty));
282*4882a593Smuzhiyun 		serial_out(up, MTK_UART_XOFF1, STOP_CHAR(port->state->port.tty));
283*4882a593Smuzhiyun 		serial_out(up, UART_LCR, lcr);
284*4882a593Smuzhiyun 		mtk8250_disable_intrs(up, MTK_UART_IER_CTSI|MTK_UART_IER_RTSI);
285*4882a593Smuzhiyun 		mtk8250_enable_intrs(up, MTK_UART_IER_XOFFI);
286*4882a593Smuzhiyun 		break;
287*4882a593Smuzhiyun 	default:
288*4882a593Smuzhiyun 		break;
289*4882a593Smuzhiyun 	}
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun static void
mtk8250_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)293*4882a593Smuzhiyun mtk8250_set_termios(struct uart_port *port, struct ktermios *termios,
294*4882a593Smuzhiyun 			struct ktermios *old)
295*4882a593Smuzhiyun {
296*4882a593Smuzhiyun 	unsigned short fraction_L_mapping[] = {
297*4882a593Smuzhiyun 		0, 1, 0x5, 0x15, 0x55, 0x57, 0x57, 0x77, 0x7F, 0xFF, 0xFF
298*4882a593Smuzhiyun 	};
299*4882a593Smuzhiyun 	unsigned short fraction_M_mapping[] = {
300*4882a593Smuzhiyun 		0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 3
301*4882a593Smuzhiyun 	};
302*4882a593Smuzhiyun 	struct uart_8250_port *up = up_to_u8250p(port);
303*4882a593Smuzhiyun 	unsigned int baud, quot, fraction;
304*4882a593Smuzhiyun 	unsigned long flags;
305*4882a593Smuzhiyun 	int mode;
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_8250_DMA
308*4882a593Smuzhiyun 	if (up->dma) {
309*4882a593Smuzhiyun 		if (uart_console(port)) {
310*4882a593Smuzhiyun 			devm_kfree(up->port.dev, up->dma);
311*4882a593Smuzhiyun 			up->dma = NULL;
312*4882a593Smuzhiyun 		} else {
313*4882a593Smuzhiyun 			mtk8250_dma_enable(up);
314*4882a593Smuzhiyun 		}
315*4882a593Smuzhiyun 	}
316*4882a593Smuzhiyun #endif
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 	/*
319*4882a593Smuzhiyun 	 * Store the requested baud rate before calling the generic 8250
320*4882a593Smuzhiyun 	 * set_termios method. Standard 8250 port expects bauds to be
321*4882a593Smuzhiyun 	 * no higher than (uartclk / 16) so the baud will be clamped if it
322*4882a593Smuzhiyun 	 * gets out of that bound. Mediatek 8250 port supports speed
323*4882a593Smuzhiyun 	 * higher than that, therefore we'll get original baud rate back
324*4882a593Smuzhiyun 	 * after calling the generic set_termios method and recalculate
325*4882a593Smuzhiyun 	 * the speed later in this method.
326*4882a593Smuzhiyun 	 */
327*4882a593Smuzhiyun 	baud = tty_termios_baud_rate(termios);
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 	serial8250_do_set_termios(port, termios, NULL);
330*4882a593Smuzhiyun 
331*4882a593Smuzhiyun 	tty_termios_encode_baud_rate(termios, baud, baud);
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun 	/*
334*4882a593Smuzhiyun 	 * Mediatek UARTs use an extra highspeed register (MTK_UART_HIGHS)
335*4882a593Smuzhiyun 	 *
336*4882a593Smuzhiyun 	 * We need to recalcualte the quot register, as the claculation depends
337*4882a593Smuzhiyun 	 * on the vaule in the highspeed register.
338*4882a593Smuzhiyun 	 *
339*4882a593Smuzhiyun 	 * Some baudrates are not supported by the chip, so we use the next
340*4882a593Smuzhiyun 	 * lower rate supported and update termios c_flag.
341*4882a593Smuzhiyun 	 *
342*4882a593Smuzhiyun 	 * If highspeed register is set to 3, we need to specify sample count
343*4882a593Smuzhiyun 	 * and sample point to increase accuracy. If not, we reset the
344*4882a593Smuzhiyun 	 * registers to their default values.
345*4882a593Smuzhiyun 	 */
346*4882a593Smuzhiyun 	baud = uart_get_baud_rate(port, termios, old,
347*4882a593Smuzhiyun 				  port->uartclk / 16 / UART_DIV_MAX,
348*4882a593Smuzhiyun 				  port->uartclk);
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun 	if (baud < 115200) {
351*4882a593Smuzhiyun 		serial_port_out(port, MTK_UART_HIGHS, 0x0);
352*4882a593Smuzhiyun 		quot = uart_get_divisor(port, baud);
353*4882a593Smuzhiyun 	} else {
354*4882a593Smuzhiyun 		serial_port_out(port, MTK_UART_HIGHS, 0x3);
355*4882a593Smuzhiyun 		quot = DIV_ROUND_UP(port->uartclk, 256 * baud);
356*4882a593Smuzhiyun 	}
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun 	/*
359*4882a593Smuzhiyun 	 * Ok, we're now changing the port state.  Do it with
360*4882a593Smuzhiyun 	 * interrupts disabled.
361*4882a593Smuzhiyun 	 */
362*4882a593Smuzhiyun 	spin_lock_irqsave(&port->lock, flags);
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun 	/*
365*4882a593Smuzhiyun 	 * Update the per-port timeout.
366*4882a593Smuzhiyun 	 */
367*4882a593Smuzhiyun 	uart_update_timeout(port, termios->c_cflag, baud);
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun 	/* set DLAB we have cval saved in up->lcr from the call to the core */
370*4882a593Smuzhiyun 	serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
371*4882a593Smuzhiyun 	serial_dl_write(up, quot);
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun 	/* reset DLAB */
374*4882a593Smuzhiyun 	serial_port_out(port, UART_LCR, up->lcr);
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun 	if (baud >= 115200) {
377*4882a593Smuzhiyun 		unsigned int tmp;
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun 		tmp = (port->uartclk / (baud *  quot)) - 1;
380*4882a593Smuzhiyun 		serial_port_out(port, MTK_UART_SAMPLE_COUNT, tmp);
381*4882a593Smuzhiyun 		serial_port_out(port, MTK_UART_SAMPLE_POINT,
382*4882a593Smuzhiyun 					(tmp >> 1) - 1);
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 		/*count fraction to set fractoin register */
385*4882a593Smuzhiyun 		fraction = ((port->uartclk  * 100) / baud / quot) % 100;
386*4882a593Smuzhiyun 		fraction = DIV_ROUND_CLOSEST(fraction, 10);
387*4882a593Smuzhiyun 		serial_port_out(port, MTK_UART_FRACDIV_L,
388*4882a593Smuzhiyun 						fraction_L_mapping[fraction]);
389*4882a593Smuzhiyun 		serial_port_out(port, MTK_UART_FRACDIV_M,
390*4882a593Smuzhiyun 						fraction_M_mapping[fraction]);
391*4882a593Smuzhiyun 	} else {
392*4882a593Smuzhiyun 		serial_port_out(port, MTK_UART_SAMPLE_COUNT, 0x00);
393*4882a593Smuzhiyun 		serial_port_out(port, MTK_UART_SAMPLE_POINT, 0xff);
394*4882a593Smuzhiyun 		serial_port_out(port, MTK_UART_FRACDIV_L, 0x00);
395*4882a593Smuzhiyun 		serial_port_out(port, MTK_UART_FRACDIV_M, 0x00);
396*4882a593Smuzhiyun 	}
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun 	if ((termios->c_cflag & CRTSCTS) && (!(termios->c_iflag & CRTSCTS)))
399*4882a593Smuzhiyun 		mode = MTK_UART_FC_HW;
400*4882a593Smuzhiyun 	else if (termios->c_iflag & CRTSCTS)
401*4882a593Smuzhiyun 		mode = MTK_UART_FC_SW;
402*4882a593Smuzhiyun 	else
403*4882a593Smuzhiyun 		mode = MTK_UART_FC_NONE;
404*4882a593Smuzhiyun 
405*4882a593Smuzhiyun 	mtk8250_set_flow_ctrl(up, mode);
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun 	if (uart_console(port))
408*4882a593Smuzhiyun 		up->port.cons->cflag = termios->c_cflag;
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 	spin_unlock_irqrestore(&port->lock, flags);
411*4882a593Smuzhiyun 	/* Don't rewrite B0 */
412*4882a593Smuzhiyun 	if (tty_termios_baud_rate(termios))
413*4882a593Smuzhiyun 		tty_termios_encode_baud_rate(termios, baud, baud);
414*4882a593Smuzhiyun }
415*4882a593Smuzhiyun 
mtk8250_runtime_suspend(struct device * dev)416*4882a593Smuzhiyun static int __maybe_unused mtk8250_runtime_suspend(struct device *dev)
417*4882a593Smuzhiyun {
418*4882a593Smuzhiyun 	struct mtk8250_data *data = dev_get_drvdata(dev);
419*4882a593Smuzhiyun 	struct uart_8250_port *up = serial8250_get_port(data->line);
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun 	/* wait until UART in idle status */
422*4882a593Smuzhiyun 	while
423*4882a593Smuzhiyun 		(serial_in(up, MTK_UART_DEBUG0));
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun 	if (data->clk_count == 0U) {
426*4882a593Smuzhiyun 		dev_dbg(dev, "%s clock count is 0\n", __func__);
427*4882a593Smuzhiyun 	} else {
428*4882a593Smuzhiyun 		clk_disable_unprepare(data->bus_clk);
429*4882a593Smuzhiyun 		data->clk_count--;
430*4882a593Smuzhiyun 	}
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun 	return 0;
433*4882a593Smuzhiyun }
434*4882a593Smuzhiyun 
mtk8250_runtime_resume(struct device * dev)435*4882a593Smuzhiyun static int __maybe_unused mtk8250_runtime_resume(struct device *dev)
436*4882a593Smuzhiyun {
437*4882a593Smuzhiyun 	struct mtk8250_data *data = dev_get_drvdata(dev);
438*4882a593Smuzhiyun 	int err;
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun 	if (data->clk_count > 0U) {
441*4882a593Smuzhiyun 		dev_dbg(dev, "%s clock count is %d\n", __func__,
442*4882a593Smuzhiyun 			data->clk_count);
443*4882a593Smuzhiyun 	} else {
444*4882a593Smuzhiyun 		err = clk_prepare_enable(data->bus_clk);
445*4882a593Smuzhiyun 		if (err) {
446*4882a593Smuzhiyun 			dev_warn(dev, "Can't enable bus clock\n");
447*4882a593Smuzhiyun 			return err;
448*4882a593Smuzhiyun 		}
449*4882a593Smuzhiyun 		data->clk_count++;
450*4882a593Smuzhiyun 	}
451*4882a593Smuzhiyun 
452*4882a593Smuzhiyun 	return 0;
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun static void
mtk8250_do_pm(struct uart_port * port,unsigned int state,unsigned int old)456*4882a593Smuzhiyun mtk8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
457*4882a593Smuzhiyun {
458*4882a593Smuzhiyun 	if (!state)
459*4882a593Smuzhiyun 		if (!mtk8250_runtime_resume(port->dev))
460*4882a593Smuzhiyun 			pm_runtime_get_sync(port->dev);
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun 	serial8250_do_pm(port, state, old);
463*4882a593Smuzhiyun 
464*4882a593Smuzhiyun 	if (state)
465*4882a593Smuzhiyun 		if (!pm_runtime_put_sync_suspend(port->dev))
466*4882a593Smuzhiyun 			mtk8250_runtime_suspend(port->dev);
467*4882a593Smuzhiyun }
468*4882a593Smuzhiyun 
469*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_8250_DMA
mtk8250_dma_filter(struct dma_chan * chan,void * param)470*4882a593Smuzhiyun static bool mtk8250_dma_filter(struct dma_chan *chan, void *param)
471*4882a593Smuzhiyun {
472*4882a593Smuzhiyun 	return false;
473*4882a593Smuzhiyun }
474*4882a593Smuzhiyun #endif
475*4882a593Smuzhiyun 
mtk8250_probe_of(struct platform_device * pdev,struct uart_port * p,struct mtk8250_data * data)476*4882a593Smuzhiyun static int mtk8250_probe_of(struct platform_device *pdev, struct uart_port *p,
477*4882a593Smuzhiyun 			   struct mtk8250_data *data)
478*4882a593Smuzhiyun {
479*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_8250_DMA
480*4882a593Smuzhiyun 	int dmacnt;
481*4882a593Smuzhiyun #endif
482*4882a593Smuzhiyun 
483*4882a593Smuzhiyun 	data->uart_clk = devm_clk_get(&pdev->dev, "baud");
484*4882a593Smuzhiyun 	if (IS_ERR(data->uart_clk)) {
485*4882a593Smuzhiyun 		/*
486*4882a593Smuzhiyun 		 * For compatibility with older device trees try unnamed
487*4882a593Smuzhiyun 		 * clk when no baud clk can be found.
488*4882a593Smuzhiyun 		 */
489*4882a593Smuzhiyun 		data->uart_clk = devm_clk_get(&pdev->dev, NULL);
490*4882a593Smuzhiyun 		if (IS_ERR(data->uart_clk)) {
491*4882a593Smuzhiyun 			dev_warn(&pdev->dev, "Can't get uart clock\n");
492*4882a593Smuzhiyun 			return PTR_ERR(data->uart_clk);
493*4882a593Smuzhiyun 		}
494*4882a593Smuzhiyun 
495*4882a593Smuzhiyun 		return 0;
496*4882a593Smuzhiyun 	}
497*4882a593Smuzhiyun 
498*4882a593Smuzhiyun 	data->bus_clk = devm_clk_get(&pdev->dev, "bus");
499*4882a593Smuzhiyun 	if (IS_ERR(data->bus_clk))
500*4882a593Smuzhiyun 		return PTR_ERR(data->bus_clk);
501*4882a593Smuzhiyun 
502*4882a593Smuzhiyun 	data->dma = NULL;
503*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_8250_DMA
504*4882a593Smuzhiyun 	dmacnt = of_property_count_strings(pdev->dev.of_node, "dma-names");
505*4882a593Smuzhiyun 	if (dmacnt == 2) {
506*4882a593Smuzhiyun 		data->dma = devm_kzalloc(&pdev->dev, sizeof(*data->dma),
507*4882a593Smuzhiyun 					 GFP_KERNEL);
508*4882a593Smuzhiyun 		if (!data->dma)
509*4882a593Smuzhiyun 			return -ENOMEM;
510*4882a593Smuzhiyun 
511*4882a593Smuzhiyun 		data->dma->fn = mtk8250_dma_filter;
512*4882a593Smuzhiyun 		data->dma->rx_size = MTK_UART_RX_SIZE;
513*4882a593Smuzhiyun 		data->dma->rxconf.src_maxburst = MTK_UART_RX_TRIGGER;
514*4882a593Smuzhiyun 		data->dma->txconf.dst_maxburst = MTK_UART_TX_TRIGGER;
515*4882a593Smuzhiyun 	}
516*4882a593Smuzhiyun #endif
517*4882a593Smuzhiyun 
518*4882a593Smuzhiyun 	return 0;
519*4882a593Smuzhiyun }
520*4882a593Smuzhiyun 
mtk8250_probe(struct platform_device * pdev)521*4882a593Smuzhiyun static int mtk8250_probe(struct platform_device *pdev)
522*4882a593Smuzhiyun {
523*4882a593Smuzhiyun 	struct uart_8250_port uart = {};
524*4882a593Smuzhiyun 	struct mtk8250_data *data;
525*4882a593Smuzhiyun 	struct resource *regs;
526*4882a593Smuzhiyun 	int irq, err;
527*4882a593Smuzhiyun 
528*4882a593Smuzhiyun 	irq = platform_get_irq(pdev, 0);
529*4882a593Smuzhiyun 	if (irq < 0)
530*4882a593Smuzhiyun 		return irq;
531*4882a593Smuzhiyun 
532*4882a593Smuzhiyun 	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
533*4882a593Smuzhiyun 	if (!regs) {
534*4882a593Smuzhiyun 		dev_err(&pdev->dev, "no registers defined\n");
535*4882a593Smuzhiyun 		return -EINVAL;
536*4882a593Smuzhiyun 	}
537*4882a593Smuzhiyun 
538*4882a593Smuzhiyun 	uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
539*4882a593Smuzhiyun 					 resource_size(regs));
540*4882a593Smuzhiyun 	if (!uart.port.membase)
541*4882a593Smuzhiyun 		return -ENOMEM;
542*4882a593Smuzhiyun 
543*4882a593Smuzhiyun 	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
544*4882a593Smuzhiyun 	if (!data)
545*4882a593Smuzhiyun 		return -ENOMEM;
546*4882a593Smuzhiyun 
547*4882a593Smuzhiyun 	data->clk_count = 0;
548*4882a593Smuzhiyun 
549*4882a593Smuzhiyun 	if (pdev->dev.of_node) {
550*4882a593Smuzhiyun 		err = mtk8250_probe_of(pdev, &uart.port, data);
551*4882a593Smuzhiyun 		if (err)
552*4882a593Smuzhiyun 			return err;
553*4882a593Smuzhiyun 	} else
554*4882a593Smuzhiyun 		return -ENODEV;
555*4882a593Smuzhiyun 
556*4882a593Smuzhiyun 	spin_lock_init(&uart.port.lock);
557*4882a593Smuzhiyun 	uart.port.mapbase = regs->start;
558*4882a593Smuzhiyun 	uart.port.irq = irq;
559*4882a593Smuzhiyun 	uart.port.pm = mtk8250_do_pm;
560*4882a593Smuzhiyun 	uart.port.type = PORT_16550;
561*4882a593Smuzhiyun 	uart.port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
562*4882a593Smuzhiyun 	uart.port.dev = &pdev->dev;
563*4882a593Smuzhiyun 	uart.port.iotype = UPIO_MEM32;
564*4882a593Smuzhiyun 	uart.port.regshift = 2;
565*4882a593Smuzhiyun 	uart.port.private_data = data;
566*4882a593Smuzhiyun 	uart.port.shutdown = mtk8250_shutdown;
567*4882a593Smuzhiyun 	uart.port.startup = mtk8250_startup;
568*4882a593Smuzhiyun 	uart.port.set_termios = mtk8250_set_termios;
569*4882a593Smuzhiyun 	uart.port.uartclk = clk_get_rate(data->uart_clk);
570*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_8250_DMA
571*4882a593Smuzhiyun 	if (data->dma)
572*4882a593Smuzhiyun 		uart.dma = data->dma;
573*4882a593Smuzhiyun #endif
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun 	/* Disable Rate Fix function */
576*4882a593Smuzhiyun 	writel(0x0, uart.port.membase +
577*4882a593Smuzhiyun 			(MTK_UART_RATE_FIX << uart.port.regshift));
578*4882a593Smuzhiyun 
579*4882a593Smuzhiyun 	platform_set_drvdata(pdev, data);
580*4882a593Smuzhiyun 
581*4882a593Smuzhiyun 	pm_runtime_enable(&pdev->dev);
582*4882a593Smuzhiyun 	err = mtk8250_runtime_resume(&pdev->dev);
583*4882a593Smuzhiyun 	if (err)
584*4882a593Smuzhiyun 		goto err_pm_disable;
585*4882a593Smuzhiyun 
586*4882a593Smuzhiyun 	data->line = serial8250_register_8250_port(&uart);
587*4882a593Smuzhiyun 	if (data->line < 0) {
588*4882a593Smuzhiyun 		err = data->line;
589*4882a593Smuzhiyun 		goto err_pm_disable;
590*4882a593Smuzhiyun 	}
591*4882a593Smuzhiyun 
592*4882a593Smuzhiyun 	data->rx_wakeup_irq = platform_get_irq_optional(pdev, 1);
593*4882a593Smuzhiyun 
594*4882a593Smuzhiyun 	return 0;
595*4882a593Smuzhiyun 
596*4882a593Smuzhiyun err_pm_disable:
597*4882a593Smuzhiyun 	pm_runtime_disable(&pdev->dev);
598*4882a593Smuzhiyun 
599*4882a593Smuzhiyun 	return err;
600*4882a593Smuzhiyun }
601*4882a593Smuzhiyun 
mtk8250_remove(struct platform_device * pdev)602*4882a593Smuzhiyun static int mtk8250_remove(struct platform_device *pdev)
603*4882a593Smuzhiyun {
604*4882a593Smuzhiyun 	struct mtk8250_data *data = platform_get_drvdata(pdev);
605*4882a593Smuzhiyun 
606*4882a593Smuzhiyun 	pm_runtime_get_sync(&pdev->dev);
607*4882a593Smuzhiyun 
608*4882a593Smuzhiyun 	serial8250_unregister_port(data->line);
609*4882a593Smuzhiyun 
610*4882a593Smuzhiyun 	pm_runtime_disable(&pdev->dev);
611*4882a593Smuzhiyun 	pm_runtime_put_noidle(&pdev->dev);
612*4882a593Smuzhiyun 
613*4882a593Smuzhiyun 	if (!pm_runtime_status_suspended(&pdev->dev))
614*4882a593Smuzhiyun 		mtk8250_runtime_suspend(&pdev->dev);
615*4882a593Smuzhiyun 
616*4882a593Smuzhiyun 	return 0;
617*4882a593Smuzhiyun }
618*4882a593Smuzhiyun 
mtk8250_suspend(struct device * dev)619*4882a593Smuzhiyun static int __maybe_unused mtk8250_suspend(struct device *dev)
620*4882a593Smuzhiyun {
621*4882a593Smuzhiyun 	struct mtk8250_data *data = dev_get_drvdata(dev);
622*4882a593Smuzhiyun 	int irq = data->rx_wakeup_irq;
623*4882a593Smuzhiyun 	int err;
624*4882a593Smuzhiyun 
625*4882a593Smuzhiyun 	serial8250_suspend_port(data->line);
626*4882a593Smuzhiyun 
627*4882a593Smuzhiyun 	pinctrl_pm_select_sleep_state(dev);
628*4882a593Smuzhiyun 	if (irq >= 0) {
629*4882a593Smuzhiyun 		err = enable_irq_wake(irq);
630*4882a593Smuzhiyun 		if (err) {
631*4882a593Smuzhiyun 			dev_err(dev,
632*4882a593Smuzhiyun 				"failed to enable irq wake on IRQ %d: %d\n",
633*4882a593Smuzhiyun 				irq, err);
634*4882a593Smuzhiyun 			pinctrl_pm_select_default_state(dev);
635*4882a593Smuzhiyun 			serial8250_resume_port(data->line);
636*4882a593Smuzhiyun 			return err;
637*4882a593Smuzhiyun 		}
638*4882a593Smuzhiyun 	}
639*4882a593Smuzhiyun 
640*4882a593Smuzhiyun 	return 0;
641*4882a593Smuzhiyun }
642*4882a593Smuzhiyun 
mtk8250_resume(struct device * dev)643*4882a593Smuzhiyun static int __maybe_unused mtk8250_resume(struct device *dev)
644*4882a593Smuzhiyun {
645*4882a593Smuzhiyun 	struct mtk8250_data *data = dev_get_drvdata(dev);
646*4882a593Smuzhiyun 	int irq = data->rx_wakeup_irq;
647*4882a593Smuzhiyun 
648*4882a593Smuzhiyun 	if (irq >= 0)
649*4882a593Smuzhiyun 		disable_irq_wake(irq);
650*4882a593Smuzhiyun 	pinctrl_pm_select_default_state(dev);
651*4882a593Smuzhiyun 
652*4882a593Smuzhiyun 	serial8250_resume_port(data->line);
653*4882a593Smuzhiyun 
654*4882a593Smuzhiyun 	return 0;
655*4882a593Smuzhiyun }
656*4882a593Smuzhiyun 
657*4882a593Smuzhiyun static const struct dev_pm_ops mtk8250_pm_ops = {
658*4882a593Smuzhiyun 	SET_SYSTEM_SLEEP_PM_OPS(mtk8250_suspend, mtk8250_resume)
659*4882a593Smuzhiyun 	SET_RUNTIME_PM_OPS(mtk8250_runtime_suspend, mtk8250_runtime_resume,
660*4882a593Smuzhiyun 				NULL)
661*4882a593Smuzhiyun };
662*4882a593Smuzhiyun 
663*4882a593Smuzhiyun static const struct of_device_id mtk8250_of_match[] = {
664*4882a593Smuzhiyun 	{ .compatible = "mediatek,mt6577-uart" },
665*4882a593Smuzhiyun 	{ /* Sentinel */ }
666*4882a593Smuzhiyun };
667*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, mtk8250_of_match);
668*4882a593Smuzhiyun 
669*4882a593Smuzhiyun static struct platform_driver mtk8250_platform_driver = {
670*4882a593Smuzhiyun 	.driver = {
671*4882a593Smuzhiyun 		.name		= "mt6577-uart",
672*4882a593Smuzhiyun 		.pm		= &mtk8250_pm_ops,
673*4882a593Smuzhiyun 		.of_match_table	= mtk8250_of_match,
674*4882a593Smuzhiyun 	},
675*4882a593Smuzhiyun 	.probe			= mtk8250_probe,
676*4882a593Smuzhiyun 	.remove			= mtk8250_remove,
677*4882a593Smuzhiyun };
678*4882a593Smuzhiyun module_platform_driver(mtk8250_platform_driver);
679*4882a593Smuzhiyun 
680*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_8250_CONSOLE
early_mtk8250_setup(struct earlycon_device * device,const char * options)681*4882a593Smuzhiyun static int __init early_mtk8250_setup(struct earlycon_device *device,
682*4882a593Smuzhiyun 					const char *options)
683*4882a593Smuzhiyun {
684*4882a593Smuzhiyun 	if (!device->port.membase)
685*4882a593Smuzhiyun 		return -ENODEV;
686*4882a593Smuzhiyun 
687*4882a593Smuzhiyun 	device->port.iotype = UPIO_MEM32;
688*4882a593Smuzhiyun 	device->port.regshift = 2;
689*4882a593Smuzhiyun 
690*4882a593Smuzhiyun 	return early_serial8250_setup(device, NULL);
691*4882a593Smuzhiyun }
692*4882a593Smuzhiyun 
693*4882a593Smuzhiyun OF_EARLYCON_DECLARE(mtk8250, "mediatek,mt6577-uart", early_mtk8250_setup);
694*4882a593Smuzhiyun #endif
695*4882a593Smuzhiyun 
696*4882a593Smuzhiyun MODULE_AUTHOR("Matthias Brugger");
697*4882a593Smuzhiyun MODULE_LICENSE("GPL");
698*4882a593Smuzhiyun MODULE_DESCRIPTION("Mediatek 8250 serial port driver");
699