xref: /OK3568_Linux_fs/kernel/drivers/tty/serial/8250/8250_lpss.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * 8250_lpss.c - Driver for UART on Intel Braswell and various other Intel SoCs
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2016 Intel Corporation
6*4882a593Smuzhiyun  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/bitops.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/pci.h>
12*4882a593Smuzhiyun #include <linux/rational.h>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include <linux/dmaengine.h>
15*4882a593Smuzhiyun #include <linux/dma/dw.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include "8250_dwlib.h"
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_QRK_UARTx	0x0936
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_BYT_UART1	0x0f0a
22*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_BYT_UART2	0x0f0c
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_BSW_UART1	0x228a
25*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_BSW_UART2	0x228c
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_EHL_UART0	0x4b96
28*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_EHL_UART1	0x4b97
29*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_EHL_UART2	0x4b98
30*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_EHL_UART3	0x4b99
31*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_EHL_UART4	0x4b9a
32*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_EHL_UART5	0x4b9b
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_BDW_UART1	0x9ce3
35*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_BDW_UART2	0x9ce4
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun /* Intel LPSS specific registers */
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #define BYT_PRV_CLK			0x800
40*4882a593Smuzhiyun #define BYT_PRV_CLK_EN			BIT(0)
41*4882a593Smuzhiyun #define BYT_PRV_CLK_M_VAL_SHIFT		1
42*4882a593Smuzhiyun #define BYT_PRV_CLK_N_VAL_SHIFT		16
43*4882a593Smuzhiyun #define BYT_PRV_CLK_UPDATE		BIT(31)
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun #define BYT_TX_OVF_INT			0x820
46*4882a593Smuzhiyun #define BYT_TX_OVF_INT_MASK		BIT(1)
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun struct lpss8250;
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun struct lpss8250_board {
51*4882a593Smuzhiyun 	unsigned long freq;
52*4882a593Smuzhiyun 	unsigned int base_baud;
53*4882a593Smuzhiyun 	int (*setup)(struct lpss8250 *, struct uart_port *p);
54*4882a593Smuzhiyun 	void (*exit)(struct lpss8250 *);
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun struct lpss8250 {
58*4882a593Smuzhiyun 	struct dw8250_port_data data;
59*4882a593Smuzhiyun 	struct lpss8250_board *board;
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	/* DMA parameters */
62*4882a593Smuzhiyun 	struct dw_dma_chip dma_chip;
63*4882a593Smuzhiyun 	struct dw_dma_slave dma_param;
64*4882a593Smuzhiyun 	u8 dma_maxburst;
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun 
to_lpss8250(struct dw8250_port_data * data)67*4882a593Smuzhiyun static inline struct lpss8250 *to_lpss8250(struct dw8250_port_data *data)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun 	return container_of(data, struct lpss8250, data);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun 
byt_set_termios(struct uart_port * p,struct ktermios * termios,struct ktermios * old)72*4882a593Smuzhiyun static void byt_set_termios(struct uart_port *p, struct ktermios *termios,
73*4882a593Smuzhiyun 			    struct ktermios *old)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun 	unsigned int baud = tty_termios_baud_rate(termios);
76*4882a593Smuzhiyun 	struct lpss8250 *lpss = to_lpss8250(p->private_data);
77*4882a593Smuzhiyun 	unsigned long fref = lpss->board->freq, fuart = baud * 16;
78*4882a593Smuzhiyun 	unsigned long w = BIT(15) - 1;
79*4882a593Smuzhiyun 	unsigned long m, n;
80*4882a593Smuzhiyun 	u32 reg;
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 	/* Gracefully handle the B0 case: fall back to B9600 */
83*4882a593Smuzhiyun 	fuart = fuart ? fuart : 9600 * 16;
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	/* Get Fuart closer to Fref */
86*4882a593Smuzhiyun 	fuart *= rounddown_pow_of_two(fref / fuart);
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	/*
89*4882a593Smuzhiyun 	 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
90*4882a593Smuzhiyun 	 * dividers must be adjusted.
91*4882a593Smuzhiyun 	 *
92*4882a593Smuzhiyun 	 * uartclk = (m / n) * 100 MHz, where m <= n
93*4882a593Smuzhiyun 	 */
94*4882a593Smuzhiyun 	rational_best_approximation(fuart, fref, w, w, &m, &n);
95*4882a593Smuzhiyun 	p->uartclk = fuart;
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	/* Reset the clock */
98*4882a593Smuzhiyun 	reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
99*4882a593Smuzhiyun 	writel(reg, p->membase + BYT_PRV_CLK);
100*4882a593Smuzhiyun 	reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
101*4882a593Smuzhiyun 	writel(reg, p->membase + BYT_PRV_CLK);
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	p->status &= ~UPSTAT_AUTOCTS;
104*4882a593Smuzhiyun 	if (termios->c_cflag & CRTSCTS)
105*4882a593Smuzhiyun 		p->status |= UPSTAT_AUTOCTS;
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	serial8250_do_set_termios(p, termios, old);
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun 
byt_get_mctrl(struct uart_port * port)110*4882a593Smuzhiyun static unsigned int byt_get_mctrl(struct uart_port *port)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun 	unsigned int ret = serial8250_do_get_mctrl(port);
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	/* Force DCD and DSR signals to permanently be reported as active */
115*4882a593Smuzhiyun 	ret |= TIOCM_CAR | TIOCM_DSR;
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	return ret;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun 
byt_serial_setup(struct lpss8250 * lpss,struct uart_port * port)120*4882a593Smuzhiyun static int byt_serial_setup(struct lpss8250 *lpss, struct uart_port *port)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun 	struct dw_dma_slave *param = &lpss->dma_param;
123*4882a593Smuzhiyun 	struct pci_dev *pdev = to_pci_dev(port->dev);
124*4882a593Smuzhiyun 	struct pci_dev *dma_dev;
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	switch (pdev->device) {
127*4882a593Smuzhiyun 	case PCI_DEVICE_ID_INTEL_BYT_UART1:
128*4882a593Smuzhiyun 	case PCI_DEVICE_ID_INTEL_BSW_UART1:
129*4882a593Smuzhiyun 	case PCI_DEVICE_ID_INTEL_BDW_UART1:
130*4882a593Smuzhiyun 		param->src_id = 3;
131*4882a593Smuzhiyun 		param->dst_id = 2;
132*4882a593Smuzhiyun 		break;
133*4882a593Smuzhiyun 	case PCI_DEVICE_ID_INTEL_BYT_UART2:
134*4882a593Smuzhiyun 	case PCI_DEVICE_ID_INTEL_BSW_UART2:
135*4882a593Smuzhiyun 	case PCI_DEVICE_ID_INTEL_BDW_UART2:
136*4882a593Smuzhiyun 		param->src_id = 5;
137*4882a593Smuzhiyun 		param->dst_id = 4;
138*4882a593Smuzhiyun 		break;
139*4882a593Smuzhiyun 	default:
140*4882a593Smuzhiyun 		return -EINVAL;
141*4882a593Smuzhiyun 	}
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	param->dma_dev = &dma_dev->dev;
146*4882a593Smuzhiyun 	param->m_master = 0;
147*4882a593Smuzhiyun 	param->p_master = 1;
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	lpss->dma_maxburst = 16;
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	port->set_termios = byt_set_termios;
152*4882a593Smuzhiyun 	port->get_mctrl = byt_get_mctrl;
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	/* Disable TX counter interrupts */
155*4882a593Smuzhiyun 	writel(BYT_TX_OVF_INT_MASK, port->membase + BYT_TX_OVF_INT);
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	return 0;
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun 
byt_serial_exit(struct lpss8250 * lpss)160*4882a593Smuzhiyun static void byt_serial_exit(struct lpss8250 *lpss)
161*4882a593Smuzhiyun {
162*4882a593Smuzhiyun 	struct dw_dma_slave *param = &lpss->dma_param;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	/* Paired with pci_get_slot() in the byt_serial_setup() above */
165*4882a593Smuzhiyun 	put_device(param->dma_dev);
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun 
ehl_serial_setup(struct lpss8250 * lpss,struct uart_port * port)168*4882a593Smuzhiyun static int ehl_serial_setup(struct lpss8250 *lpss, struct uart_port *port)
169*4882a593Smuzhiyun {
170*4882a593Smuzhiyun 	return 0;
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun 
ehl_serial_exit(struct lpss8250 * lpss)173*4882a593Smuzhiyun static void ehl_serial_exit(struct lpss8250 *lpss)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun 	struct uart_8250_port *up = serial8250_get_port(lpss->data.line);
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	up->dma = NULL;
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_8250_DMA
181*4882a593Smuzhiyun static const struct dw_dma_platform_data qrk_serial_dma_pdata = {
182*4882a593Smuzhiyun 	.nr_channels = 2,
183*4882a593Smuzhiyun 	.chan_allocation_order = CHAN_ALLOCATION_ASCENDING,
184*4882a593Smuzhiyun 	.chan_priority = CHAN_PRIORITY_ASCENDING,
185*4882a593Smuzhiyun 	.block_size = 4095,
186*4882a593Smuzhiyun 	.nr_masters = 1,
187*4882a593Smuzhiyun 	.data_width = {4},
188*4882a593Smuzhiyun 	.multi_block = {0},
189*4882a593Smuzhiyun };
190*4882a593Smuzhiyun 
qrk_serial_setup_dma(struct lpss8250 * lpss,struct uart_port * port)191*4882a593Smuzhiyun static void qrk_serial_setup_dma(struct lpss8250 *lpss, struct uart_port *port)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun 	struct uart_8250_dma *dma = &lpss->data.dma;
194*4882a593Smuzhiyun 	struct dw_dma_chip *chip = &lpss->dma_chip;
195*4882a593Smuzhiyun 	struct dw_dma_slave *param = &lpss->dma_param;
196*4882a593Smuzhiyun 	struct pci_dev *pdev = to_pci_dev(port->dev);
197*4882a593Smuzhiyun 	int ret;
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	chip->pdata = &qrk_serial_dma_pdata;
200*4882a593Smuzhiyun 	chip->dev = &pdev->dev;
201*4882a593Smuzhiyun 	chip->id = pdev->devfn;
202*4882a593Smuzhiyun 	chip->irq = pci_irq_vector(pdev, 0);
203*4882a593Smuzhiyun 	chip->regs = pci_ioremap_bar(pdev, 1);
204*4882a593Smuzhiyun 	if (!chip->regs)
205*4882a593Smuzhiyun 		return;
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	/* Falling back to PIO mode if DMA probing fails */
208*4882a593Smuzhiyun 	ret = dw_dma_probe(chip);
209*4882a593Smuzhiyun 	if (ret)
210*4882a593Smuzhiyun 		return;
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	pci_try_set_mwi(pdev);
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	/* Special DMA address for UART */
215*4882a593Smuzhiyun 	dma->rx_dma_addr = 0xfffff000;
216*4882a593Smuzhiyun 	dma->tx_dma_addr = 0xfffff000;
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 	param->dma_dev = &pdev->dev;
219*4882a593Smuzhiyun 	param->src_id = 0;
220*4882a593Smuzhiyun 	param->dst_id = 1;
221*4882a593Smuzhiyun 	param->hs_polarity = true;
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	lpss->dma_maxburst = 8;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun 
qrk_serial_exit_dma(struct lpss8250 * lpss)226*4882a593Smuzhiyun static void qrk_serial_exit_dma(struct lpss8250 *lpss)
227*4882a593Smuzhiyun {
228*4882a593Smuzhiyun 	struct dw_dma_chip *chip = &lpss->dma_chip;
229*4882a593Smuzhiyun 	struct dw_dma_slave *param = &lpss->dma_param;
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 	if (!param->dma_dev)
232*4882a593Smuzhiyun 		return;
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	dw_dma_remove(chip);
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun 	pci_iounmap(to_pci_dev(chip->dev), chip->regs);
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun #else	/* CONFIG_SERIAL_8250_DMA */
qrk_serial_setup_dma(struct lpss8250 * lpss,struct uart_port * port)239*4882a593Smuzhiyun static void qrk_serial_setup_dma(struct lpss8250 *lpss, struct uart_port *port) {}
qrk_serial_exit_dma(struct lpss8250 * lpss)240*4882a593Smuzhiyun static void qrk_serial_exit_dma(struct lpss8250 *lpss) {}
241*4882a593Smuzhiyun #endif	/* !CONFIG_SERIAL_8250_DMA */
242*4882a593Smuzhiyun 
qrk_serial_setup(struct lpss8250 * lpss,struct uart_port * port)243*4882a593Smuzhiyun static int qrk_serial_setup(struct lpss8250 *lpss, struct uart_port *port)
244*4882a593Smuzhiyun {
245*4882a593Smuzhiyun 	qrk_serial_setup_dma(lpss, port);
246*4882a593Smuzhiyun 	return 0;
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun 
qrk_serial_exit(struct lpss8250 * lpss)249*4882a593Smuzhiyun static void qrk_serial_exit(struct lpss8250 *lpss)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun 	qrk_serial_exit_dma(lpss);
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun 
lpss8250_dma_filter(struct dma_chan * chan,void * param)254*4882a593Smuzhiyun static bool lpss8250_dma_filter(struct dma_chan *chan, void *param)
255*4882a593Smuzhiyun {
256*4882a593Smuzhiyun 	struct dw_dma_slave *dws = param;
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun 	if (dws->dma_dev != chan->device->dev)
259*4882a593Smuzhiyun 		return false;
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun 	chan->private = dws;
262*4882a593Smuzhiyun 	return true;
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun 
lpss8250_dma_setup(struct lpss8250 * lpss,struct uart_8250_port * port)265*4882a593Smuzhiyun static int lpss8250_dma_setup(struct lpss8250 *lpss, struct uart_8250_port *port)
266*4882a593Smuzhiyun {
267*4882a593Smuzhiyun 	struct uart_8250_dma *dma = &lpss->data.dma;
268*4882a593Smuzhiyun 	struct dw_dma_slave *rx_param, *tx_param;
269*4882a593Smuzhiyun 	struct device *dev = port->port.dev;
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	if (!lpss->dma_param.dma_dev) {
272*4882a593Smuzhiyun 		dma = port->dma;
273*4882a593Smuzhiyun 		if (dma)
274*4882a593Smuzhiyun 			goto out_configuration_only;
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 		return 0;
277*4882a593Smuzhiyun 	}
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
280*4882a593Smuzhiyun 	if (!rx_param)
281*4882a593Smuzhiyun 		return -ENOMEM;
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun 	tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
284*4882a593Smuzhiyun 	if (!tx_param)
285*4882a593Smuzhiyun 		return -ENOMEM;
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun 	*rx_param = lpss->dma_param;
288*4882a593Smuzhiyun 	*tx_param = lpss->dma_param;
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 	dma->fn = lpss8250_dma_filter;
291*4882a593Smuzhiyun 	dma->rx_param = rx_param;
292*4882a593Smuzhiyun 	dma->tx_param = tx_param;
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun 	port->dma = dma;
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun out_configuration_only:
297*4882a593Smuzhiyun 	dma->rxconf.src_maxburst = lpss->dma_maxburst;
298*4882a593Smuzhiyun 	dma->txconf.dst_maxburst = lpss->dma_maxburst;
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 	return 0;
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun 
lpss8250_probe(struct pci_dev * pdev,const struct pci_device_id * id)303*4882a593Smuzhiyun static int lpss8250_probe(struct pci_dev *pdev, const struct pci_device_id *id)
304*4882a593Smuzhiyun {
305*4882a593Smuzhiyun 	struct uart_8250_port uart;
306*4882a593Smuzhiyun 	struct lpss8250 *lpss;
307*4882a593Smuzhiyun 	int ret;
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 	ret = pcim_enable_device(pdev);
310*4882a593Smuzhiyun 	if (ret)
311*4882a593Smuzhiyun 		return ret;
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 	pci_set_master(pdev);
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 	lpss = devm_kzalloc(&pdev->dev, sizeof(*lpss), GFP_KERNEL);
316*4882a593Smuzhiyun 	if (!lpss)
317*4882a593Smuzhiyun 		return -ENOMEM;
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun 	ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
320*4882a593Smuzhiyun 	if (ret < 0)
321*4882a593Smuzhiyun 		return ret;
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun 	lpss->board = (struct lpss8250_board *)id->driver_data;
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun 	memset(&uart, 0, sizeof(struct uart_8250_port));
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun 	uart.port.dev = &pdev->dev;
328*4882a593Smuzhiyun 	uart.port.irq = pci_irq_vector(pdev, 0);
329*4882a593Smuzhiyun 	uart.port.private_data = &lpss->data;
330*4882a593Smuzhiyun 	uart.port.type = PORT_16550A;
331*4882a593Smuzhiyun 	uart.port.iotype = UPIO_MEM;
332*4882a593Smuzhiyun 	uart.port.regshift = 2;
333*4882a593Smuzhiyun 	uart.port.uartclk = lpss->board->base_baud * 16;
334*4882a593Smuzhiyun 	uart.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT | UPF_FIXED_TYPE;
335*4882a593Smuzhiyun 	uart.capabilities = UART_CAP_FIFO | UART_CAP_AFE;
336*4882a593Smuzhiyun 	uart.port.mapbase = pci_resource_start(pdev, 0);
337*4882a593Smuzhiyun 	uart.port.membase = pcim_iomap(pdev, 0, 0);
338*4882a593Smuzhiyun 	if (!uart.port.membase)
339*4882a593Smuzhiyun 		return -ENOMEM;
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun 	ret = lpss->board->setup(lpss, &uart.port);
342*4882a593Smuzhiyun 	if (ret)
343*4882a593Smuzhiyun 		return ret;
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun 	dw8250_setup_port(&uart.port);
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun 	ret = lpss8250_dma_setup(lpss, &uart);
348*4882a593Smuzhiyun 	if (ret)
349*4882a593Smuzhiyun 		goto err_exit;
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun 	ret = serial8250_register_8250_port(&uart);
352*4882a593Smuzhiyun 	if (ret < 0)
353*4882a593Smuzhiyun 		goto err_exit;
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 	lpss->data.line = ret;
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun 	pci_set_drvdata(pdev, lpss);
358*4882a593Smuzhiyun 	return 0;
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun err_exit:
361*4882a593Smuzhiyun 	lpss->board->exit(lpss);
362*4882a593Smuzhiyun 	pci_free_irq_vectors(pdev);
363*4882a593Smuzhiyun 	return ret;
364*4882a593Smuzhiyun }
365*4882a593Smuzhiyun 
lpss8250_remove(struct pci_dev * pdev)366*4882a593Smuzhiyun static void lpss8250_remove(struct pci_dev *pdev)
367*4882a593Smuzhiyun {
368*4882a593Smuzhiyun 	struct lpss8250 *lpss = pci_get_drvdata(pdev);
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun 	serial8250_unregister_port(lpss->data.line);
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun 	lpss->board->exit(lpss);
373*4882a593Smuzhiyun 	pci_free_irq_vectors(pdev);
374*4882a593Smuzhiyun }
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun static const struct lpss8250_board byt_board = {
377*4882a593Smuzhiyun 	.freq = 100000000,
378*4882a593Smuzhiyun 	.base_baud = 2764800,
379*4882a593Smuzhiyun 	.setup = byt_serial_setup,
380*4882a593Smuzhiyun 	.exit = byt_serial_exit,
381*4882a593Smuzhiyun };
382*4882a593Smuzhiyun 
383*4882a593Smuzhiyun static const struct lpss8250_board ehl_board = {
384*4882a593Smuzhiyun 	.freq = 200000000,
385*4882a593Smuzhiyun 	.base_baud = 12500000,
386*4882a593Smuzhiyun 	.setup = ehl_serial_setup,
387*4882a593Smuzhiyun 	.exit = ehl_serial_exit,
388*4882a593Smuzhiyun };
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun static const struct lpss8250_board qrk_board = {
391*4882a593Smuzhiyun 	.freq = 44236800,
392*4882a593Smuzhiyun 	.base_baud = 2764800,
393*4882a593Smuzhiyun 	.setup = qrk_serial_setup,
394*4882a593Smuzhiyun 	.exit = qrk_serial_exit,
395*4882a593Smuzhiyun };
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun static const struct pci_device_id pci_ids[] = {
398*4882a593Smuzhiyun 	{ PCI_DEVICE_DATA(INTEL, QRK_UARTx, &qrk_board) },
399*4882a593Smuzhiyun 	{ PCI_DEVICE_DATA(INTEL, EHL_UART0, &ehl_board) },
400*4882a593Smuzhiyun 	{ PCI_DEVICE_DATA(INTEL, EHL_UART1, &ehl_board) },
401*4882a593Smuzhiyun 	{ PCI_DEVICE_DATA(INTEL, EHL_UART2, &ehl_board) },
402*4882a593Smuzhiyun 	{ PCI_DEVICE_DATA(INTEL, EHL_UART3, &ehl_board) },
403*4882a593Smuzhiyun 	{ PCI_DEVICE_DATA(INTEL, EHL_UART4, &ehl_board) },
404*4882a593Smuzhiyun 	{ PCI_DEVICE_DATA(INTEL, EHL_UART5, &ehl_board) },
405*4882a593Smuzhiyun 	{ PCI_DEVICE_DATA(INTEL, BYT_UART1, &byt_board) },
406*4882a593Smuzhiyun 	{ PCI_DEVICE_DATA(INTEL, BYT_UART2, &byt_board) },
407*4882a593Smuzhiyun 	{ PCI_DEVICE_DATA(INTEL, BSW_UART1, &byt_board) },
408*4882a593Smuzhiyun 	{ PCI_DEVICE_DATA(INTEL, BSW_UART2, &byt_board) },
409*4882a593Smuzhiyun 	{ PCI_DEVICE_DATA(INTEL, BDW_UART1, &byt_board) },
410*4882a593Smuzhiyun 	{ PCI_DEVICE_DATA(INTEL, BDW_UART2, &byt_board) },
411*4882a593Smuzhiyun 	{ }
412*4882a593Smuzhiyun };
413*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, pci_ids);
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun static struct pci_driver lpss8250_pci_driver = {
416*4882a593Smuzhiyun 	.name           = "8250_lpss",
417*4882a593Smuzhiyun 	.id_table       = pci_ids,
418*4882a593Smuzhiyun 	.probe          = lpss8250_probe,
419*4882a593Smuzhiyun 	.remove         = lpss8250_remove,
420*4882a593Smuzhiyun };
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun module_pci_driver(lpss8250_pci_driver);
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun MODULE_AUTHOR("Intel Corporation");
425*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
426*4882a593Smuzhiyun MODULE_DESCRIPTION("Intel LPSS UART driver");
427