xref: /OK3568_Linux_fs/kernel/drivers/tty/serial/8250/8250_early.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Early serial console for 8250/16550 devices
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * (c) Copyright 2004 Hewlett-Packard Development Company, L.P.
6*4882a593Smuzhiyun  *	Bjorn Helgaas <bjorn.helgaas@hp.com>
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Based on the 8250.c serial driver, Copyright (C) 2001 Russell King,
9*4882a593Smuzhiyun  * and on early_printk.c by Andi Kleen.
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * This is for use before the serial driver has initialized, in
12*4882a593Smuzhiyun  * particular, before the UARTs have been discovered and named.
13*4882a593Smuzhiyun  * Instead of specifying the console device as, e.g., "ttyS0",
14*4882a593Smuzhiyun  * we locate the device directly by its MMIO or I/O port address.
15*4882a593Smuzhiyun  *
16*4882a593Smuzhiyun  * The user can specify the device directly, e.g.,
17*4882a593Smuzhiyun  *	earlycon=uart8250,io,0x3f8,9600n8
18*4882a593Smuzhiyun  *	earlycon=uart8250,mmio,0xff5e0000,115200n8
19*4882a593Smuzhiyun  *	earlycon=uart8250,mmio32,0xff5e0000,115200n8
20*4882a593Smuzhiyun  * or
21*4882a593Smuzhiyun  *	console=uart8250,io,0x3f8,9600n8
22*4882a593Smuzhiyun  *	console=uart8250,mmio,0xff5e0000,115200n8
23*4882a593Smuzhiyun  *	console=uart8250,mmio32,0xff5e0000,115200n8
24*4882a593Smuzhiyun  */
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #include <linux/tty.h>
27*4882a593Smuzhiyun #include <linux/init.h>
28*4882a593Smuzhiyun #include <linux/console.h>
29*4882a593Smuzhiyun #include <linux/of.h>
30*4882a593Smuzhiyun #include <linux/of_device.h>
31*4882a593Smuzhiyun #include <linux/serial_reg.h>
32*4882a593Smuzhiyun #include <linux/serial.h>
33*4882a593Smuzhiyun #include <linux/serial_8250.h>
34*4882a593Smuzhiyun #include <asm/io.h>
35*4882a593Smuzhiyun #include <asm/serial.h>
36*4882a593Smuzhiyun 
serial8250_early_in(struct uart_port * port,int offset)37*4882a593Smuzhiyun static unsigned int serial8250_early_in(struct uart_port *port, int offset)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun 	int reg_offset = offset;
40*4882a593Smuzhiyun 	offset <<= port->regshift;
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun 	switch (port->iotype) {
43*4882a593Smuzhiyun 	case UPIO_MEM:
44*4882a593Smuzhiyun 		return readb(port->membase + offset);
45*4882a593Smuzhiyun 	case UPIO_MEM16:
46*4882a593Smuzhiyun 		return readw(port->membase + offset);
47*4882a593Smuzhiyun 	case UPIO_MEM32:
48*4882a593Smuzhiyun 		return readl(port->membase + offset);
49*4882a593Smuzhiyun 	case UPIO_MEM32BE:
50*4882a593Smuzhiyun 		return ioread32be(port->membase + offset);
51*4882a593Smuzhiyun 	case UPIO_PORT:
52*4882a593Smuzhiyun 		return inb(port->iobase + offset);
53*4882a593Smuzhiyun 	case UPIO_AU:
54*4882a593Smuzhiyun 		return port->serial_in(port, reg_offset);
55*4882a593Smuzhiyun 	default:
56*4882a593Smuzhiyun 		return 0;
57*4882a593Smuzhiyun 	}
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun 
serial8250_early_out(struct uart_port * port,int offset,int value)60*4882a593Smuzhiyun static void serial8250_early_out(struct uart_port *port, int offset, int value)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun 	int reg_offset = offset;
63*4882a593Smuzhiyun 	offset <<= port->regshift;
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 	switch (port->iotype) {
66*4882a593Smuzhiyun 	case UPIO_MEM:
67*4882a593Smuzhiyun 		writeb(value, port->membase + offset);
68*4882a593Smuzhiyun 		break;
69*4882a593Smuzhiyun 	case UPIO_MEM16:
70*4882a593Smuzhiyun 		writew(value, port->membase + offset);
71*4882a593Smuzhiyun 		break;
72*4882a593Smuzhiyun 	case UPIO_MEM32:
73*4882a593Smuzhiyun 		writel(value, port->membase + offset);
74*4882a593Smuzhiyun 		break;
75*4882a593Smuzhiyun 	case UPIO_MEM32BE:
76*4882a593Smuzhiyun 		iowrite32be(value, port->membase + offset);
77*4882a593Smuzhiyun 		break;
78*4882a593Smuzhiyun 	case UPIO_PORT:
79*4882a593Smuzhiyun 		outb(value, port->iobase + offset);
80*4882a593Smuzhiyun 		break;
81*4882a593Smuzhiyun 	case UPIO_AU:
82*4882a593Smuzhiyun 		port->serial_out(port, reg_offset, value);
83*4882a593Smuzhiyun 		break;
84*4882a593Smuzhiyun 	}
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
88*4882a593Smuzhiyun 
serial_putc(struct uart_port * port,int c)89*4882a593Smuzhiyun static void serial_putc(struct uart_port *port, int c)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun 	unsigned int status;
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	serial8250_early_out(port, UART_TX, c);
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	for (;;) {
96*4882a593Smuzhiyun 		status = serial8250_early_in(port, UART_LSR);
97*4882a593Smuzhiyun 		if ((status & BOTH_EMPTY) == BOTH_EMPTY)
98*4882a593Smuzhiyun 			break;
99*4882a593Smuzhiyun 		cpu_relax();
100*4882a593Smuzhiyun 	}
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun 
early_serial8250_write(struct console * console,const char * s,unsigned int count)103*4882a593Smuzhiyun static void early_serial8250_write(struct console *console,
104*4882a593Smuzhiyun 					const char *s, unsigned int count)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun 	struct earlycon_device *device = console->data;
107*4882a593Smuzhiyun 	struct uart_port *port = &device->port;
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	uart_console_write(port, s, count, serial_putc);
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun #ifdef CONFIG_CONSOLE_POLL
early_serial8250_read(struct console * console,char * s,unsigned int count)113*4882a593Smuzhiyun static int early_serial8250_read(struct console *console,
114*4882a593Smuzhiyun 				 char *s, unsigned int count)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun 	struct earlycon_device *device = console->data;
117*4882a593Smuzhiyun 	struct uart_port *port = &device->port;
118*4882a593Smuzhiyun 	unsigned int status;
119*4882a593Smuzhiyun 	int num_read = 0;
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	while (num_read < count) {
122*4882a593Smuzhiyun 		status = serial8250_early_in(port, UART_LSR);
123*4882a593Smuzhiyun 		if (!(status & UART_LSR_DR))
124*4882a593Smuzhiyun 			break;
125*4882a593Smuzhiyun 		s[num_read++] = serial8250_early_in(port, UART_RX);
126*4882a593Smuzhiyun 	}
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	return num_read;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun #else
131*4882a593Smuzhiyun #define early_serial8250_read NULL
132*4882a593Smuzhiyun #endif
133*4882a593Smuzhiyun 
init_port(struct earlycon_device * device)134*4882a593Smuzhiyun static void __init init_port(struct earlycon_device *device)
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun 	struct uart_port *port = &device->port;
137*4882a593Smuzhiyun 	unsigned int divisor;
138*4882a593Smuzhiyun 	unsigned char c;
139*4882a593Smuzhiyun 	unsigned int ier;
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	serial8250_early_out(port, UART_LCR, 0x3);	/* 8n1 */
142*4882a593Smuzhiyun 	ier = serial8250_early_in(port, UART_IER);
143*4882a593Smuzhiyun 	serial8250_early_out(port, UART_IER, ier & UART_IER_UUE); /* no interrupt */
144*4882a593Smuzhiyun 	serial8250_early_out(port, UART_FCR, 0);	/* no fifo */
145*4882a593Smuzhiyun 	serial8250_early_out(port, UART_MCR, 0x3);	/* DTR + RTS */
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	if (port->uartclk) {
148*4882a593Smuzhiyun 		divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * device->baud);
149*4882a593Smuzhiyun 		c = serial8250_early_in(port, UART_LCR);
150*4882a593Smuzhiyun 		serial8250_early_out(port, UART_LCR, c | UART_LCR_DLAB);
151*4882a593Smuzhiyun 		serial8250_early_out(port, UART_DLL, divisor & 0xff);
152*4882a593Smuzhiyun 		serial8250_early_out(port, UART_DLM, (divisor >> 8) & 0xff);
153*4882a593Smuzhiyun 		serial8250_early_out(port, UART_LCR, c & ~UART_LCR_DLAB);
154*4882a593Smuzhiyun 	}
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun 
early_serial8250_setup(struct earlycon_device * device,const char * options)157*4882a593Smuzhiyun int __init early_serial8250_setup(struct earlycon_device *device,
158*4882a593Smuzhiyun 					 const char *options)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun 	if (!(device->port.membase || device->port.iobase))
161*4882a593Smuzhiyun 		return -ENODEV;
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	if (!device->baud) {
164*4882a593Smuzhiyun 		struct uart_port *port = &device->port;
165*4882a593Smuzhiyun 		unsigned int ier;
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 		/* assume the device was initialized, only mask interrupts */
168*4882a593Smuzhiyun 		ier = serial8250_early_in(port, UART_IER);
169*4882a593Smuzhiyun 		serial8250_early_out(port, UART_IER, ier & UART_IER_UUE);
170*4882a593Smuzhiyun 	} else
171*4882a593Smuzhiyun 		init_port(device);
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	device->con->write = early_serial8250_write;
174*4882a593Smuzhiyun 	device->con->read = early_serial8250_read;
175*4882a593Smuzhiyun 	return 0;
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun EARLYCON_DECLARE(uart8250, early_serial8250_setup);
178*4882a593Smuzhiyun EARLYCON_DECLARE(uart, early_serial8250_setup);
179*4882a593Smuzhiyun OF_EARLYCON_DECLARE(ns16550, "ns16550", early_serial8250_setup);
180*4882a593Smuzhiyun OF_EARLYCON_DECLARE(ns16550a, "ns16550a", early_serial8250_setup);
181*4882a593Smuzhiyun OF_EARLYCON_DECLARE(uart, "nvidia,tegra20-uart", early_serial8250_setup);
182*4882a593Smuzhiyun OF_EARLYCON_DECLARE(uart, "snps,dw-apb-uart", early_serial8250_setup);
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_8250_OMAP
185*4882a593Smuzhiyun 
early_omap8250_setup(struct earlycon_device * device,const char * options)186*4882a593Smuzhiyun static int __init early_omap8250_setup(struct earlycon_device *device,
187*4882a593Smuzhiyun 				       const char *options)
188*4882a593Smuzhiyun {
189*4882a593Smuzhiyun 	struct uart_port *port = &device->port;
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	if (!(device->port.membase || device->port.iobase))
192*4882a593Smuzhiyun 		return -ENODEV;
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	port->regshift = 2;
195*4882a593Smuzhiyun 	device->con->write = early_serial8250_write;
196*4882a593Smuzhiyun 	return 0;
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun OF_EARLYCON_DECLARE(omap8250, "ti,omap2-uart", early_omap8250_setup);
200*4882a593Smuzhiyun OF_EARLYCON_DECLARE(omap8250, "ti,omap3-uart", early_omap8250_setup);
201*4882a593Smuzhiyun OF_EARLYCON_DECLARE(omap8250, "ti,omap4-uart", early_omap8250_setup);
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun #endif
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_8250_RT288X
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun unsigned int au_serial_in(struct uart_port *p, int offset);
208*4882a593Smuzhiyun void au_serial_out(struct uart_port *p, int offset, int value);
209*4882a593Smuzhiyun 
early_au_setup(struct earlycon_device * dev,const char * opt)210*4882a593Smuzhiyun static int __init early_au_setup(struct earlycon_device *dev, const char *opt)
211*4882a593Smuzhiyun {
212*4882a593Smuzhiyun 	dev->port.serial_in = au_serial_in;
213*4882a593Smuzhiyun 	dev->port.serial_out = au_serial_out;
214*4882a593Smuzhiyun 	dev->port.iotype = UPIO_AU;
215*4882a593Smuzhiyun 	dev->con->write = early_serial8250_write;
216*4882a593Smuzhiyun 	return 0;
217*4882a593Smuzhiyun }
218*4882a593Smuzhiyun OF_EARLYCON_DECLARE(palmchip, "ralink,rt2880-uart", early_au_setup);
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun #endif
221