xref: /OK3568_Linux_fs/kernel/drivers/tty/mxser.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *          mxser.c  -- MOXA Smartio/Industio family multiport serial driver.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *      Copyright (C) 1999-2006  Moxa Technologies (support@moxa.com).
6*4882a593Smuzhiyun  *	Copyright (C) 2006-2008  Jiri Slaby <jirislaby@gmail.com>
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  *      This code is loosely based on the 1.8 moxa driver which is based on
9*4882a593Smuzhiyun  *	Linux serial driver, written by Linus Torvalds, Theodore T'so and
10*4882a593Smuzhiyun  *	others.
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  *	Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox
13*4882a593Smuzhiyun  *	<alan@lxorguk.ukuu.org.uk>. The original 1.8 code is available on
14*4882a593Smuzhiyun  *	www.moxa.com.
15*4882a593Smuzhiyun  *	- Fixed x86_64 cleanness
16*4882a593Smuzhiyun  */
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include <linux/module.h>
19*4882a593Smuzhiyun #include <linux/errno.h>
20*4882a593Smuzhiyun #include <linux/signal.h>
21*4882a593Smuzhiyun #include <linux/sched.h>
22*4882a593Smuzhiyun #include <linux/timer.h>
23*4882a593Smuzhiyun #include <linux/interrupt.h>
24*4882a593Smuzhiyun #include <linux/tty.h>
25*4882a593Smuzhiyun #include <linux/tty_flip.h>
26*4882a593Smuzhiyun #include <linux/serial.h>
27*4882a593Smuzhiyun #include <linux/serial_reg.h>
28*4882a593Smuzhiyun #include <linux/major.h>
29*4882a593Smuzhiyun #include <linux/string.h>
30*4882a593Smuzhiyun #include <linux/fcntl.h>
31*4882a593Smuzhiyun #include <linux/ptrace.h>
32*4882a593Smuzhiyun #include <linux/ioport.h>
33*4882a593Smuzhiyun #include <linux/mm.h>
34*4882a593Smuzhiyun #include <linux/delay.h>
35*4882a593Smuzhiyun #include <linux/pci.h>
36*4882a593Smuzhiyun #include <linux/bitops.h>
37*4882a593Smuzhiyun #include <linux/slab.h>
38*4882a593Smuzhiyun #include <linux/ratelimit.h>
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun #include <asm/io.h>
41*4882a593Smuzhiyun #include <asm/irq.h>
42*4882a593Smuzhiyun #include <linux/uaccess.h>
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun #include "mxser.h"
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun #define	MXSER_VERSION	"2.0.5"		/* 1.14 */
47*4882a593Smuzhiyun #define	MXSERMAJOR	 174
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun #define MXSER_BOARDS		4	/* Max. boards */
50*4882a593Smuzhiyun #define MXSER_PORTS_PER_BOARD	8	/* Max. ports per board */
51*4882a593Smuzhiyun #define MXSER_PORTS		(MXSER_BOARDS * MXSER_PORTS_PER_BOARD)
52*4882a593Smuzhiyun #define MXSER_ISR_PASS_LIMIT	100
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun /*CheckIsMoxaMust return value*/
55*4882a593Smuzhiyun #define MOXA_OTHER_UART		0x00
56*4882a593Smuzhiyun #define MOXA_MUST_MU150_HWID	0x01
57*4882a593Smuzhiyun #define MOXA_MUST_MU860_HWID	0x02
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun #define WAKEUP_CHARS		256
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun #define UART_MCR_AFE		0x20
62*4882a593Smuzhiyun #define UART_LSR_SPECIAL	0x1E
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun #define PCI_DEVICE_ID_POS104UL	0x1044
65*4882a593Smuzhiyun #define PCI_DEVICE_ID_CB108	0x1080
66*4882a593Smuzhiyun #define PCI_DEVICE_ID_CP102UF	0x1023
67*4882a593Smuzhiyun #define PCI_DEVICE_ID_CP112UL	0x1120
68*4882a593Smuzhiyun #define PCI_DEVICE_ID_CB114	0x1142
69*4882a593Smuzhiyun #define PCI_DEVICE_ID_CP114UL	0x1143
70*4882a593Smuzhiyun #define PCI_DEVICE_ID_CB134I	0x1341
71*4882a593Smuzhiyun #define PCI_DEVICE_ID_CP138U	0x1380
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun #define C168_ASIC_ID    1
75*4882a593Smuzhiyun #define C104_ASIC_ID    2
76*4882a593Smuzhiyun #define C102_ASIC_ID	0xB
77*4882a593Smuzhiyun #define CI132_ASIC_ID	4
78*4882a593Smuzhiyun #define CI134_ASIC_ID	3
79*4882a593Smuzhiyun #define CI104J_ASIC_ID  5
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun #define MXSER_HIGHBAUD	1
82*4882a593Smuzhiyun #define MXSER_HAS2	2
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun /* This is only for PCI */
85*4882a593Smuzhiyun static const struct {
86*4882a593Smuzhiyun 	int type;
87*4882a593Smuzhiyun 	int tx_fifo;
88*4882a593Smuzhiyun 	int rx_fifo;
89*4882a593Smuzhiyun 	int xmit_fifo_size;
90*4882a593Smuzhiyun 	int rx_high_water;
91*4882a593Smuzhiyun 	int rx_trigger;
92*4882a593Smuzhiyun 	int rx_low_water;
93*4882a593Smuzhiyun 	long max_baud;
94*4882a593Smuzhiyun } Gpci_uart_info[] = {
95*4882a593Smuzhiyun 	{MOXA_OTHER_UART, 16, 16, 16, 14, 14, 1, 921600L},
96*4882a593Smuzhiyun 	{MOXA_MUST_MU150_HWID, 64, 64, 64, 48, 48, 16, 230400L},
97*4882a593Smuzhiyun 	{MOXA_MUST_MU860_HWID, 128, 128, 128, 96, 96, 32, 921600L}
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun #define UART_INFO_NUM	ARRAY_SIZE(Gpci_uart_info)
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun struct mxser_cardinfo {
102*4882a593Smuzhiyun 	char *name;
103*4882a593Smuzhiyun 	unsigned int nports;
104*4882a593Smuzhiyun 	unsigned int flags;
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun static const struct mxser_cardinfo mxser_cards[] = {
108*4882a593Smuzhiyun /* 0*/	{ "C168 series",	8, },
109*4882a593Smuzhiyun 	{ "C104 series",	4, },
110*4882a593Smuzhiyun 	{ "CI-104J series",	4, },
111*4882a593Smuzhiyun 	{ "C168H/PCI series",	8, },
112*4882a593Smuzhiyun 	{ "C104H/PCI series",	4, },
113*4882a593Smuzhiyun /* 5*/	{ "C102 series",	4, MXSER_HAS2 },	/* C102-ISA */
114*4882a593Smuzhiyun 	{ "CI-132 series",	4, MXSER_HAS2 },
115*4882a593Smuzhiyun 	{ "CI-134 series",	4, },
116*4882a593Smuzhiyun 	{ "CP-132 series",	2, },
117*4882a593Smuzhiyun 	{ "CP-114 series",	4, },
118*4882a593Smuzhiyun /*10*/	{ "CT-114 series",	4, },
119*4882a593Smuzhiyun 	{ "CP-102 series",	2, MXSER_HIGHBAUD },
120*4882a593Smuzhiyun 	{ "CP-104U series",	4, },
121*4882a593Smuzhiyun 	{ "CP-168U series",	8, },
122*4882a593Smuzhiyun 	{ "CP-132U series",	2, },
123*4882a593Smuzhiyun /*15*/	{ "CP-134U series",	4, },
124*4882a593Smuzhiyun 	{ "CP-104JU series",	4, },
125*4882a593Smuzhiyun 	{ "Moxa UC7000 Serial",	8, },		/* RC7000 */
126*4882a593Smuzhiyun 	{ "CP-118U series",	8, },
127*4882a593Smuzhiyun 	{ "CP-102UL series",	2, },
128*4882a593Smuzhiyun /*20*/	{ "CP-102U series",	2, },
129*4882a593Smuzhiyun 	{ "CP-118EL series",	8, },
130*4882a593Smuzhiyun 	{ "CP-168EL series",	8, },
131*4882a593Smuzhiyun 	{ "CP-104EL series",	4, },
132*4882a593Smuzhiyun 	{ "CB-108 series",	8, },
133*4882a593Smuzhiyun /*25*/	{ "CB-114 series",	4, },
134*4882a593Smuzhiyun 	{ "CB-134I series",	4, },
135*4882a593Smuzhiyun 	{ "CP-138U series",	8, },
136*4882a593Smuzhiyun 	{ "POS-104UL series",	4, },
137*4882a593Smuzhiyun 	{ "CP-114UL series",	4, },
138*4882a593Smuzhiyun /*30*/	{ "CP-102UF series",	2, },
139*4882a593Smuzhiyun 	{ "CP-112UL series",	2, },
140*4882a593Smuzhiyun };
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun /* driver_data correspond to the lines in the structure above
143*4882a593Smuzhiyun    see also ISA probe function before you change something */
144*4882a593Smuzhiyun static const struct pci_device_id mxser_pcibrds[] = {
145*4882a593Smuzhiyun 	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C168),	.driver_data = 3 },
146*4882a593Smuzhiyun 	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C104),	.driver_data = 4 },
147*4882a593Smuzhiyun 	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132),	.driver_data = 8 },
148*4882a593Smuzhiyun 	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114),	.driver_data = 9 },
149*4882a593Smuzhiyun 	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CT114),	.driver_data = 10 },
150*4882a593Smuzhiyun 	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102),	.driver_data = 11 },
151*4882a593Smuzhiyun 	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104U),	.driver_data = 12 },
152*4882a593Smuzhiyun 	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168U),	.driver_data = 13 },
153*4882a593Smuzhiyun 	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132U),	.driver_data = 14 },
154*4882a593Smuzhiyun 	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134U),	.driver_data = 15 },
155*4882a593Smuzhiyun 	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104JU),.driver_data = 16 },
156*4882a593Smuzhiyun 	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_RC7000),	.driver_data = 17 },
157*4882a593Smuzhiyun 	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118U),	.driver_data = 18 },
158*4882a593Smuzhiyun 	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102UL),.driver_data = 19 },
159*4882a593Smuzhiyun 	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102U),	.driver_data = 20 },
160*4882a593Smuzhiyun 	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL),.driver_data = 21 },
161*4882a593Smuzhiyun 	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL),.driver_data = 22 },
162*4882a593Smuzhiyun 	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL),.driver_data = 23 },
163*4882a593Smuzhiyun 	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB108),	.driver_data = 24 },
164*4882a593Smuzhiyun 	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB114),	.driver_data = 25 },
165*4882a593Smuzhiyun 	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB134I),	.driver_data = 26 },
166*4882a593Smuzhiyun 	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP138U),	.driver_data = 27 },
167*4882a593Smuzhiyun 	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_POS104UL),	.driver_data = 28 },
168*4882a593Smuzhiyun 	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP114UL),	.driver_data = 29 },
169*4882a593Smuzhiyun 	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP102UF),	.driver_data = 30 },
170*4882a593Smuzhiyun 	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP112UL),	.driver_data = 31 },
171*4882a593Smuzhiyun 	{ }
172*4882a593Smuzhiyun };
173*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, mxser_pcibrds);
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun static unsigned long ioaddr[MXSER_BOARDS];
176*4882a593Smuzhiyun static int ttymajor = MXSERMAJOR;
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun /* Variables for insmod */
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun MODULE_AUTHOR("Casper Yang");
181*4882a593Smuzhiyun MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver");
182*4882a593Smuzhiyun module_param_hw_array(ioaddr, ulong, ioport, NULL, 0);
183*4882a593Smuzhiyun MODULE_PARM_DESC(ioaddr, "ISA io addresses to look for a moxa board");
184*4882a593Smuzhiyun module_param(ttymajor, int, 0);
185*4882a593Smuzhiyun MODULE_LICENSE("GPL");
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun struct mxser_log {
188*4882a593Smuzhiyun 	int tick;
189*4882a593Smuzhiyun 	unsigned long rxcnt[MXSER_PORTS];
190*4882a593Smuzhiyun 	unsigned long txcnt[MXSER_PORTS];
191*4882a593Smuzhiyun };
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun struct mxser_mon {
194*4882a593Smuzhiyun 	unsigned long rxcnt;
195*4882a593Smuzhiyun 	unsigned long txcnt;
196*4882a593Smuzhiyun 	unsigned long up_rxcnt;
197*4882a593Smuzhiyun 	unsigned long up_txcnt;
198*4882a593Smuzhiyun 	int modem_status;
199*4882a593Smuzhiyun 	unsigned char hold_reason;
200*4882a593Smuzhiyun };
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun struct mxser_mon_ext {
203*4882a593Smuzhiyun 	unsigned long rx_cnt[32];
204*4882a593Smuzhiyun 	unsigned long tx_cnt[32];
205*4882a593Smuzhiyun 	unsigned long up_rxcnt[32];
206*4882a593Smuzhiyun 	unsigned long up_txcnt[32];
207*4882a593Smuzhiyun 	int modem_status[32];
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	long baudrate[32];
210*4882a593Smuzhiyun 	int databits[32];
211*4882a593Smuzhiyun 	int stopbits[32];
212*4882a593Smuzhiyun 	int parity[32];
213*4882a593Smuzhiyun 	int flowctrl[32];
214*4882a593Smuzhiyun 	int fifo[32];
215*4882a593Smuzhiyun 	int iftype[32];
216*4882a593Smuzhiyun };
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun struct mxser_board;
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun struct mxser_port {
221*4882a593Smuzhiyun 	struct tty_port port;
222*4882a593Smuzhiyun 	struct mxser_board *board;
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 	unsigned long ioaddr;
225*4882a593Smuzhiyun 	unsigned long opmode_ioaddr;
226*4882a593Smuzhiyun 	int max_baud;
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 	int rx_high_water;
229*4882a593Smuzhiyun 	int rx_trigger;		/* Rx fifo trigger level */
230*4882a593Smuzhiyun 	int rx_low_water;
231*4882a593Smuzhiyun 	int baud_base;		/* max. speed */
232*4882a593Smuzhiyun 	int type;		/* UART type */
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	int x_char;		/* xon/xoff character */
235*4882a593Smuzhiyun 	int IER;		/* Interrupt Enable Register */
236*4882a593Smuzhiyun 	int MCR;		/* Modem control register */
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 	unsigned char stop_rx;
239*4882a593Smuzhiyun 	unsigned char ldisc_stop_rx;
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun 	int custom_divisor;
242*4882a593Smuzhiyun 	unsigned char err_shadow;
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	struct async_icount icount; /* kernel counters for 4 input interrupts */
245*4882a593Smuzhiyun 	unsigned int timeout;
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun 	int read_status_mask;
248*4882a593Smuzhiyun 	int ignore_status_mask;
249*4882a593Smuzhiyun 	unsigned int xmit_fifo_size;
250*4882a593Smuzhiyun 	int xmit_head;
251*4882a593Smuzhiyun 	int xmit_tail;
252*4882a593Smuzhiyun 	int xmit_cnt;
253*4882a593Smuzhiyun 	int closing;
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 	struct ktermios normal_termios;
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	struct mxser_mon mon_data;
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 	spinlock_t slock;
260*4882a593Smuzhiyun };
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun struct mxser_board {
263*4882a593Smuzhiyun 	unsigned int idx;
264*4882a593Smuzhiyun 	int irq;
265*4882a593Smuzhiyun 	const struct mxser_cardinfo *info;
266*4882a593Smuzhiyun 	unsigned long vector;
267*4882a593Smuzhiyun 	unsigned long vector_mask;
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	int chip_flag;
270*4882a593Smuzhiyun 	int uart_type;
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	struct mxser_port ports[MXSER_PORTS_PER_BOARD];
273*4882a593Smuzhiyun };
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun struct mxser_mstatus {
276*4882a593Smuzhiyun 	tcflag_t cflag;
277*4882a593Smuzhiyun 	int cts;
278*4882a593Smuzhiyun 	int dsr;
279*4882a593Smuzhiyun 	int ri;
280*4882a593Smuzhiyun 	int dcd;
281*4882a593Smuzhiyun };
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun static struct mxser_board mxser_boards[MXSER_BOARDS];
284*4882a593Smuzhiyun static struct tty_driver *mxvar_sdriver;
285*4882a593Smuzhiyun static struct mxser_log mxvar_log;
286*4882a593Smuzhiyun static int mxser_set_baud_method[MXSER_PORTS + 1];
287*4882a593Smuzhiyun 
mxser_enable_must_enchance_mode(unsigned long baseio)288*4882a593Smuzhiyun static void mxser_enable_must_enchance_mode(unsigned long baseio)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun 	u8 oldlcr;
291*4882a593Smuzhiyun 	u8 efr;
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 	oldlcr = inb(baseio + UART_LCR);
294*4882a593Smuzhiyun 	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun 	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
297*4882a593Smuzhiyun 	efr |= MOXA_MUST_EFR_EFRB_ENABLE;
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
300*4882a593Smuzhiyun 	outb(oldlcr, baseio + UART_LCR);
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun #ifdef	CONFIG_PCI
mxser_disable_must_enchance_mode(unsigned long baseio)304*4882a593Smuzhiyun static void mxser_disable_must_enchance_mode(unsigned long baseio)
305*4882a593Smuzhiyun {
306*4882a593Smuzhiyun 	u8 oldlcr;
307*4882a593Smuzhiyun 	u8 efr;
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 	oldlcr = inb(baseio + UART_LCR);
310*4882a593Smuzhiyun 	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
313*4882a593Smuzhiyun 	efr &= ~MOXA_MUST_EFR_EFRB_ENABLE;
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
316*4882a593Smuzhiyun 	outb(oldlcr, baseio + UART_LCR);
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun #endif
319*4882a593Smuzhiyun 
mxser_set_must_xon1_value(unsigned long baseio,u8 value)320*4882a593Smuzhiyun static void mxser_set_must_xon1_value(unsigned long baseio, u8 value)
321*4882a593Smuzhiyun {
322*4882a593Smuzhiyun 	u8 oldlcr;
323*4882a593Smuzhiyun 	u8 efr;
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun 	oldlcr = inb(baseio + UART_LCR);
326*4882a593Smuzhiyun 	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun 	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
329*4882a593Smuzhiyun 	efr &= ~MOXA_MUST_EFR_BANK_MASK;
330*4882a593Smuzhiyun 	efr |= MOXA_MUST_EFR_BANK0;
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
333*4882a593Smuzhiyun 	outb(value, baseio + MOXA_MUST_XON1_REGISTER);
334*4882a593Smuzhiyun 	outb(oldlcr, baseio + UART_LCR);
335*4882a593Smuzhiyun }
336*4882a593Smuzhiyun 
mxser_set_must_xoff1_value(unsigned long baseio,u8 value)337*4882a593Smuzhiyun static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value)
338*4882a593Smuzhiyun {
339*4882a593Smuzhiyun 	u8 oldlcr;
340*4882a593Smuzhiyun 	u8 efr;
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun 	oldlcr = inb(baseio + UART_LCR);
343*4882a593Smuzhiyun 	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun 	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
346*4882a593Smuzhiyun 	efr &= ~MOXA_MUST_EFR_BANK_MASK;
347*4882a593Smuzhiyun 	efr |= MOXA_MUST_EFR_BANK0;
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
350*4882a593Smuzhiyun 	outb(value, baseio + MOXA_MUST_XOFF1_REGISTER);
351*4882a593Smuzhiyun 	outb(oldlcr, baseio + UART_LCR);
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun 
mxser_set_must_fifo_value(struct mxser_port * info)354*4882a593Smuzhiyun static void mxser_set_must_fifo_value(struct mxser_port *info)
355*4882a593Smuzhiyun {
356*4882a593Smuzhiyun 	u8 oldlcr;
357*4882a593Smuzhiyun 	u8 efr;
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun 	oldlcr = inb(info->ioaddr + UART_LCR);
360*4882a593Smuzhiyun 	outb(MOXA_MUST_ENTER_ENCHANCE, info->ioaddr + UART_LCR);
361*4882a593Smuzhiyun 
362*4882a593Smuzhiyun 	efr = inb(info->ioaddr + MOXA_MUST_EFR_REGISTER);
363*4882a593Smuzhiyun 	efr &= ~MOXA_MUST_EFR_BANK_MASK;
364*4882a593Smuzhiyun 	efr |= MOXA_MUST_EFR_BANK1;
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun 	outb(efr, info->ioaddr + MOXA_MUST_EFR_REGISTER);
367*4882a593Smuzhiyun 	outb((u8)info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER);
368*4882a593Smuzhiyun 	outb((u8)info->rx_trigger, info->ioaddr + MOXA_MUST_RBRTI_REGISTER);
369*4882a593Smuzhiyun 	outb((u8)info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER);
370*4882a593Smuzhiyun 	outb(oldlcr, info->ioaddr + UART_LCR);
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun 
mxser_set_must_enum_value(unsigned long baseio,u8 value)373*4882a593Smuzhiyun static void mxser_set_must_enum_value(unsigned long baseio, u8 value)
374*4882a593Smuzhiyun {
375*4882a593Smuzhiyun 	u8 oldlcr;
376*4882a593Smuzhiyun 	u8 efr;
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun 	oldlcr = inb(baseio + UART_LCR);
379*4882a593Smuzhiyun 	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun 	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
382*4882a593Smuzhiyun 	efr &= ~MOXA_MUST_EFR_BANK_MASK;
383*4882a593Smuzhiyun 	efr |= MOXA_MUST_EFR_BANK2;
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
386*4882a593Smuzhiyun 	outb(value, baseio + MOXA_MUST_ENUM_REGISTER);
387*4882a593Smuzhiyun 	outb(oldlcr, baseio + UART_LCR);
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun #ifdef CONFIG_PCI
mxser_get_must_hardware_id(unsigned long baseio,u8 * pId)391*4882a593Smuzhiyun static void mxser_get_must_hardware_id(unsigned long baseio, u8 *pId)
392*4882a593Smuzhiyun {
393*4882a593Smuzhiyun 	u8 oldlcr;
394*4882a593Smuzhiyun 	u8 efr;
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun 	oldlcr = inb(baseio + UART_LCR);
397*4882a593Smuzhiyun 	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
398*4882a593Smuzhiyun 
399*4882a593Smuzhiyun 	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
400*4882a593Smuzhiyun 	efr &= ~MOXA_MUST_EFR_BANK_MASK;
401*4882a593Smuzhiyun 	efr |= MOXA_MUST_EFR_BANK2;
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
404*4882a593Smuzhiyun 	*pId = inb(baseio + MOXA_MUST_HWID_REGISTER);
405*4882a593Smuzhiyun 	outb(oldlcr, baseio + UART_LCR);
406*4882a593Smuzhiyun }
407*4882a593Smuzhiyun #endif
408*4882a593Smuzhiyun 
SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(unsigned long baseio)409*4882a593Smuzhiyun static void SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(unsigned long baseio)
410*4882a593Smuzhiyun {
411*4882a593Smuzhiyun 	u8 oldlcr;
412*4882a593Smuzhiyun 	u8 efr;
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun 	oldlcr = inb(baseio + UART_LCR);
415*4882a593Smuzhiyun 	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun 	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
418*4882a593Smuzhiyun 	efr &= ~MOXA_MUST_EFR_SF_MASK;
419*4882a593Smuzhiyun 
420*4882a593Smuzhiyun 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
421*4882a593Smuzhiyun 	outb(oldlcr, baseio + UART_LCR);
422*4882a593Smuzhiyun }
423*4882a593Smuzhiyun 
mxser_enable_must_tx_software_flow_control(unsigned long baseio)424*4882a593Smuzhiyun static void mxser_enable_must_tx_software_flow_control(unsigned long baseio)
425*4882a593Smuzhiyun {
426*4882a593Smuzhiyun 	u8 oldlcr;
427*4882a593Smuzhiyun 	u8 efr;
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun 	oldlcr = inb(baseio + UART_LCR);
430*4882a593Smuzhiyun 	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun 	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
433*4882a593Smuzhiyun 	efr &= ~MOXA_MUST_EFR_SF_TX_MASK;
434*4882a593Smuzhiyun 	efr |= MOXA_MUST_EFR_SF_TX1;
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
437*4882a593Smuzhiyun 	outb(oldlcr, baseio + UART_LCR);
438*4882a593Smuzhiyun }
439*4882a593Smuzhiyun 
mxser_disable_must_tx_software_flow_control(unsigned long baseio)440*4882a593Smuzhiyun static void mxser_disable_must_tx_software_flow_control(unsigned long baseio)
441*4882a593Smuzhiyun {
442*4882a593Smuzhiyun 	u8 oldlcr;
443*4882a593Smuzhiyun 	u8 efr;
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun 	oldlcr = inb(baseio + UART_LCR);
446*4882a593Smuzhiyun 	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
447*4882a593Smuzhiyun 
448*4882a593Smuzhiyun 	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
449*4882a593Smuzhiyun 	efr &= ~MOXA_MUST_EFR_SF_TX_MASK;
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
452*4882a593Smuzhiyun 	outb(oldlcr, baseio + UART_LCR);
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun 
mxser_enable_must_rx_software_flow_control(unsigned long baseio)455*4882a593Smuzhiyun static void mxser_enable_must_rx_software_flow_control(unsigned long baseio)
456*4882a593Smuzhiyun {
457*4882a593Smuzhiyun 	u8 oldlcr;
458*4882a593Smuzhiyun 	u8 efr;
459*4882a593Smuzhiyun 
460*4882a593Smuzhiyun 	oldlcr = inb(baseio + UART_LCR);
461*4882a593Smuzhiyun 	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun 	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
464*4882a593Smuzhiyun 	efr &= ~MOXA_MUST_EFR_SF_RX_MASK;
465*4882a593Smuzhiyun 	efr |= MOXA_MUST_EFR_SF_RX1;
466*4882a593Smuzhiyun 
467*4882a593Smuzhiyun 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
468*4882a593Smuzhiyun 	outb(oldlcr, baseio + UART_LCR);
469*4882a593Smuzhiyun }
470*4882a593Smuzhiyun 
mxser_disable_must_rx_software_flow_control(unsigned long baseio)471*4882a593Smuzhiyun static void mxser_disable_must_rx_software_flow_control(unsigned long baseio)
472*4882a593Smuzhiyun {
473*4882a593Smuzhiyun 	u8 oldlcr;
474*4882a593Smuzhiyun 	u8 efr;
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun 	oldlcr = inb(baseio + UART_LCR);
477*4882a593Smuzhiyun 	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
478*4882a593Smuzhiyun 
479*4882a593Smuzhiyun 	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
480*4882a593Smuzhiyun 	efr &= ~MOXA_MUST_EFR_SF_RX_MASK;
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
483*4882a593Smuzhiyun 	outb(oldlcr, baseio + UART_LCR);
484*4882a593Smuzhiyun }
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun #ifdef CONFIG_PCI
CheckIsMoxaMust(unsigned long io)487*4882a593Smuzhiyun static int CheckIsMoxaMust(unsigned long io)
488*4882a593Smuzhiyun {
489*4882a593Smuzhiyun 	u8 oldmcr, hwid;
490*4882a593Smuzhiyun 	int i;
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun 	outb(0, io + UART_LCR);
493*4882a593Smuzhiyun 	mxser_disable_must_enchance_mode(io);
494*4882a593Smuzhiyun 	oldmcr = inb(io + UART_MCR);
495*4882a593Smuzhiyun 	outb(0, io + UART_MCR);
496*4882a593Smuzhiyun 	mxser_set_must_xon1_value(io, 0x11);
497*4882a593Smuzhiyun 	if ((hwid = inb(io + UART_MCR)) != 0) {
498*4882a593Smuzhiyun 		outb(oldmcr, io + UART_MCR);
499*4882a593Smuzhiyun 		return MOXA_OTHER_UART;
500*4882a593Smuzhiyun 	}
501*4882a593Smuzhiyun 
502*4882a593Smuzhiyun 	mxser_get_must_hardware_id(io, &hwid);
503*4882a593Smuzhiyun 	for (i = 1; i < UART_INFO_NUM; i++) { /* 0 = OTHER_UART */
504*4882a593Smuzhiyun 		if (hwid == Gpci_uart_info[i].type)
505*4882a593Smuzhiyun 			return (int)hwid;
506*4882a593Smuzhiyun 	}
507*4882a593Smuzhiyun 	return MOXA_OTHER_UART;
508*4882a593Smuzhiyun }
509*4882a593Smuzhiyun #endif
510*4882a593Smuzhiyun 
process_txrx_fifo(struct mxser_port * info)511*4882a593Smuzhiyun static void process_txrx_fifo(struct mxser_port *info)
512*4882a593Smuzhiyun {
513*4882a593Smuzhiyun 	int i;
514*4882a593Smuzhiyun 
515*4882a593Smuzhiyun 	if ((info->type == PORT_16450) || (info->type == PORT_8250)) {
516*4882a593Smuzhiyun 		info->rx_trigger = 1;
517*4882a593Smuzhiyun 		info->rx_high_water = 1;
518*4882a593Smuzhiyun 		info->rx_low_water = 1;
519*4882a593Smuzhiyun 		info->xmit_fifo_size = 1;
520*4882a593Smuzhiyun 	} else
521*4882a593Smuzhiyun 		for (i = 0; i < UART_INFO_NUM; i++)
522*4882a593Smuzhiyun 			if (info->board->chip_flag == Gpci_uart_info[i].type) {
523*4882a593Smuzhiyun 				info->rx_trigger = Gpci_uart_info[i].rx_trigger;
524*4882a593Smuzhiyun 				info->rx_low_water = Gpci_uart_info[i].rx_low_water;
525*4882a593Smuzhiyun 				info->rx_high_water = Gpci_uart_info[i].rx_high_water;
526*4882a593Smuzhiyun 				info->xmit_fifo_size = Gpci_uart_info[i].xmit_fifo_size;
527*4882a593Smuzhiyun 				break;
528*4882a593Smuzhiyun 			}
529*4882a593Smuzhiyun }
530*4882a593Smuzhiyun 
mxser_get_msr(int baseaddr,int mode,int port)531*4882a593Smuzhiyun static unsigned char mxser_get_msr(int baseaddr, int mode, int port)
532*4882a593Smuzhiyun {
533*4882a593Smuzhiyun 	static unsigned char mxser_msr[MXSER_PORTS + 1];
534*4882a593Smuzhiyun 	unsigned char status = 0;
535*4882a593Smuzhiyun 
536*4882a593Smuzhiyun 	status = inb(baseaddr + UART_MSR);
537*4882a593Smuzhiyun 
538*4882a593Smuzhiyun 	mxser_msr[port] &= 0x0F;
539*4882a593Smuzhiyun 	mxser_msr[port] |= status;
540*4882a593Smuzhiyun 	status = mxser_msr[port];
541*4882a593Smuzhiyun 	if (mode)
542*4882a593Smuzhiyun 		mxser_msr[port] = 0;
543*4882a593Smuzhiyun 
544*4882a593Smuzhiyun 	return status;
545*4882a593Smuzhiyun }
546*4882a593Smuzhiyun 
mxser_carrier_raised(struct tty_port * port)547*4882a593Smuzhiyun static int mxser_carrier_raised(struct tty_port *port)
548*4882a593Smuzhiyun {
549*4882a593Smuzhiyun 	struct mxser_port *mp = container_of(port, struct mxser_port, port);
550*4882a593Smuzhiyun 	return (inb(mp->ioaddr + UART_MSR) & UART_MSR_DCD)?1:0;
551*4882a593Smuzhiyun }
552*4882a593Smuzhiyun 
mxser_dtr_rts(struct tty_port * port,int on)553*4882a593Smuzhiyun static void mxser_dtr_rts(struct tty_port *port, int on)
554*4882a593Smuzhiyun {
555*4882a593Smuzhiyun 	struct mxser_port *mp = container_of(port, struct mxser_port, port);
556*4882a593Smuzhiyun 	unsigned long flags;
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun 	spin_lock_irqsave(&mp->slock, flags);
559*4882a593Smuzhiyun 	if (on)
560*4882a593Smuzhiyun 		outb(inb(mp->ioaddr + UART_MCR) |
561*4882a593Smuzhiyun 			UART_MCR_DTR | UART_MCR_RTS, mp->ioaddr + UART_MCR);
562*4882a593Smuzhiyun 	else
563*4882a593Smuzhiyun 		outb(inb(mp->ioaddr + UART_MCR)&~(UART_MCR_DTR | UART_MCR_RTS),
564*4882a593Smuzhiyun 			mp->ioaddr + UART_MCR);
565*4882a593Smuzhiyun 	spin_unlock_irqrestore(&mp->slock, flags);
566*4882a593Smuzhiyun }
567*4882a593Smuzhiyun 
mxser_set_baud(struct tty_struct * tty,long newspd)568*4882a593Smuzhiyun static int mxser_set_baud(struct tty_struct *tty, long newspd)
569*4882a593Smuzhiyun {
570*4882a593Smuzhiyun 	struct mxser_port *info = tty->driver_data;
571*4882a593Smuzhiyun 	unsigned int quot = 0, baud;
572*4882a593Smuzhiyun 	unsigned char cval;
573*4882a593Smuzhiyun 	u64 timeout;
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun 	if (!info->ioaddr)
576*4882a593Smuzhiyun 		return -1;
577*4882a593Smuzhiyun 
578*4882a593Smuzhiyun 	if (newspd > info->max_baud)
579*4882a593Smuzhiyun 		return -1;
580*4882a593Smuzhiyun 
581*4882a593Smuzhiyun 	if (newspd == 134) {
582*4882a593Smuzhiyun 		quot = 2 * info->baud_base / 269;
583*4882a593Smuzhiyun 		tty_encode_baud_rate(tty, 134, 134);
584*4882a593Smuzhiyun 	} else if (newspd) {
585*4882a593Smuzhiyun 		quot = info->baud_base / newspd;
586*4882a593Smuzhiyun 		if (quot == 0)
587*4882a593Smuzhiyun 			quot = 1;
588*4882a593Smuzhiyun 		baud = info->baud_base/quot;
589*4882a593Smuzhiyun 		tty_encode_baud_rate(tty, baud, baud);
590*4882a593Smuzhiyun 	} else {
591*4882a593Smuzhiyun 		quot = 0;
592*4882a593Smuzhiyun 	}
593*4882a593Smuzhiyun 
594*4882a593Smuzhiyun 	/*
595*4882a593Smuzhiyun 	 * worst case (128 * 1000 * 10 * 18432) needs 35 bits, so divide in the
596*4882a593Smuzhiyun 	 * u64 domain
597*4882a593Smuzhiyun 	 */
598*4882a593Smuzhiyun 	timeout = (u64)info->xmit_fifo_size * HZ * 10 * quot;
599*4882a593Smuzhiyun 	do_div(timeout, info->baud_base);
600*4882a593Smuzhiyun 	info->timeout = timeout + HZ / 50; /* Add .02 seconds of slop */
601*4882a593Smuzhiyun 
602*4882a593Smuzhiyun 	if (quot) {
603*4882a593Smuzhiyun 		info->MCR |= UART_MCR_DTR;
604*4882a593Smuzhiyun 		outb(info->MCR, info->ioaddr + UART_MCR);
605*4882a593Smuzhiyun 	} else {
606*4882a593Smuzhiyun 		info->MCR &= ~UART_MCR_DTR;
607*4882a593Smuzhiyun 		outb(info->MCR, info->ioaddr + UART_MCR);
608*4882a593Smuzhiyun 		return 0;
609*4882a593Smuzhiyun 	}
610*4882a593Smuzhiyun 
611*4882a593Smuzhiyun 	cval = inb(info->ioaddr + UART_LCR);
612*4882a593Smuzhiyun 
613*4882a593Smuzhiyun 	outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR);	/* set DLAB */
614*4882a593Smuzhiyun 
615*4882a593Smuzhiyun 	outb(quot & 0xff, info->ioaddr + UART_DLL);	/* LS of divisor */
616*4882a593Smuzhiyun 	outb(quot >> 8, info->ioaddr + UART_DLM);	/* MS of divisor */
617*4882a593Smuzhiyun 	outb(cval, info->ioaddr + UART_LCR);	/* reset DLAB */
618*4882a593Smuzhiyun 
619*4882a593Smuzhiyun #ifdef BOTHER
620*4882a593Smuzhiyun 	if (C_BAUD(tty) == BOTHER) {
621*4882a593Smuzhiyun 		quot = info->baud_base % newspd;
622*4882a593Smuzhiyun 		quot *= 8;
623*4882a593Smuzhiyun 		if (quot % newspd > newspd / 2) {
624*4882a593Smuzhiyun 			quot /= newspd;
625*4882a593Smuzhiyun 			quot++;
626*4882a593Smuzhiyun 		} else
627*4882a593Smuzhiyun 			quot /= newspd;
628*4882a593Smuzhiyun 
629*4882a593Smuzhiyun 		mxser_set_must_enum_value(info->ioaddr, quot);
630*4882a593Smuzhiyun 	} else
631*4882a593Smuzhiyun #endif
632*4882a593Smuzhiyun 		mxser_set_must_enum_value(info->ioaddr, 0);
633*4882a593Smuzhiyun 
634*4882a593Smuzhiyun 	return 0;
635*4882a593Smuzhiyun }
636*4882a593Smuzhiyun 
637*4882a593Smuzhiyun /*
638*4882a593Smuzhiyun  * This routine is called to set the UART divisor registers to match
639*4882a593Smuzhiyun  * the specified baud rate for a serial port.
640*4882a593Smuzhiyun  */
mxser_change_speed(struct tty_struct * tty)641*4882a593Smuzhiyun static void mxser_change_speed(struct tty_struct *tty)
642*4882a593Smuzhiyun {
643*4882a593Smuzhiyun 	struct mxser_port *info = tty->driver_data;
644*4882a593Smuzhiyun 	unsigned cflag, cval, fcr;
645*4882a593Smuzhiyun 	unsigned char status;
646*4882a593Smuzhiyun 
647*4882a593Smuzhiyun 	cflag = tty->termios.c_cflag;
648*4882a593Smuzhiyun 	if (!info->ioaddr)
649*4882a593Smuzhiyun 		return;
650*4882a593Smuzhiyun 
651*4882a593Smuzhiyun 	if (mxser_set_baud_method[tty->index] == 0)
652*4882a593Smuzhiyun 		mxser_set_baud(tty, tty_get_baud_rate(tty));
653*4882a593Smuzhiyun 
654*4882a593Smuzhiyun 	/* byte size and parity */
655*4882a593Smuzhiyun 	switch (cflag & CSIZE) {
656*4882a593Smuzhiyun 	case CS5:
657*4882a593Smuzhiyun 		cval = 0x00;
658*4882a593Smuzhiyun 		break;
659*4882a593Smuzhiyun 	case CS6:
660*4882a593Smuzhiyun 		cval = 0x01;
661*4882a593Smuzhiyun 		break;
662*4882a593Smuzhiyun 	case CS7:
663*4882a593Smuzhiyun 		cval = 0x02;
664*4882a593Smuzhiyun 		break;
665*4882a593Smuzhiyun 	case CS8:
666*4882a593Smuzhiyun 		cval = 0x03;
667*4882a593Smuzhiyun 		break;
668*4882a593Smuzhiyun 	default:
669*4882a593Smuzhiyun 		cval = 0x00;
670*4882a593Smuzhiyun 		break;		/* too keep GCC shut... */
671*4882a593Smuzhiyun 	}
672*4882a593Smuzhiyun 	if (cflag & CSTOPB)
673*4882a593Smuzhiyun 		cval |= 0x04;
674*4882a593Smuzhiyun 	if (cflag & PARENB)
675*4882a593Smuzhiyun 		cval |= UART_LCR_PARITY;
676*4882a593Smuzhiyun 	if (!(cflag & PARODD))
677*4882a593Smuzhiyun 		cval |= UART_LCR_EPAR;
678*4882a593Smuzhiyun 	if (cflag & CMSPAR)
679*4882a593Smuzhiyun 		cval |= UART_LCR_SPAR;
680*4882a593Smuzhiyun 
681*4882a593Smuzhiyun 	if ((info->type == PORT_8250) || (info->type == PORT_16450)) {
682*4882a593Smuzhiyun 		if (info->board->chip_flag) {
683*4882a593Smuzhiyun 			fcr = UART_FCR_ENABLE_FIFO;
684*4882a593Smuzhiyun 			fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
685*4882a593Smuzhiyun 			mxser_set_must_fifo_value(info);
686*4882a593Smuzhiyun 		} else
687*4882a593Smuzhiyun 			fcr = 0;
688*4882a593Smuzhiyun 	} else {
689*4882a593Smuzhiyun 		fcr = UART_FCR_ENABLE_FIFO;
690*4882a593Smuzhiyun 		if (info->board->chip_flag) {
691*4882a593Smuzhiyun 			fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
692*4882a593Smuzhiyun 			mxser_set_must_fifo_value(info);
693*4882a593Smuzhiyun 		} else {
694*4882a593Smuzhiyun 			switch (info->rx_trigger) {
695*4882a593Smuzhiyun 			case 1:
696*4882a593Smuzhiyun 				fcr |= UART_FCR_TRIGGER_1;
697*4882a593Smuzhiyun 				break;
698*4882a593Smuzhiyun 			case 4:
699*4882a593Smuzhiyun 				fcr |= UART_FCR_TRIGGER_4;
700*4882a593Smuzhiyun 				break;
701*4882a593Smuzhiyun 			case 8:
702*4882a593Smuzhiyun 				fcr |= UART_FCR_TRIGGER_8;
703*4882a593Smuzhiyun 				break;
704*4882a593Smuzhiyun 			default:
705*4882a593Smuzhiyun 				fcr |= UART_FCR_TRIGGER_14;
706*4882a593Smuzhiyun 				break;
707*4882a593Smuzhiyun 			}
708*4882a593Smuzhiyun 		}
709*4882a593Smuzhiyun 	}
710*4882a593Smuzhiyun 
711*4882a593Smuzhiyun 	/* CTS flow control flag and modem status interrupts */
712*4882a593Smuzhiyun 	info->IER &= ~UART_IER_MSI;
713*4882a593Smuzhiyun 	info->MCR &= ~UART_MCR_AFE;
714*4882a593Smuzhiyun 	tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
715*4882a593Smuzhiyun 	if (cflag & CRTSCTS) {
716*4882a593Smuzhiyun 		info->IER |= UART_IER_MSI;
717*4882a593Smuzhiyun 		if ((info->type == PORT_16550A) || (info->board->chip_flag)) {
718*4882a593Smuzhiyun 			info->MCR |= UART_MCR_AFE;
719*4882a593Smuzhiyun 		} else {
720*4882a593Smuzhiyun 			status = inb(info->ioaddr + UART_MSR);
721*4882a593Smuzhiyun 			if (tty->hw_stopped) {
722*4882a593Smuzhiyun 				if (status & UART_MSR_CTS) {
723*4882a593Smuzhiyun 					tty->hw_stopped = 0;
724*4882a593Smuzhiyun 					if (info->type != PORT_16550A &&
725*4882a593Smuzhiyun 							!info->board->chip_flag) {
726*4882a593Smuzhiyun 						outb(info->IER & ~UART_IER_THRI,
727*4882a593Smuzhiyun 							info->ioaddr +
728*4882a593Smuzhiyun 							UART_IER);
729*4882a593Smuzhiyun 						info->IER |= UART_IER_THRI;
730*4882a593Smuzhiyun 						outb(info->IER, info->ioaddr +
731*4882a593Smuzhiyun 								UART_IER);
732*4882a593Smuzhiyun 					}
733*4882a593Smuzhiyun 					tty_wakeup(tty);
734*4882a593Smuzhiyun 				}
735*4882a593Smuzhiyun 			} else {
736*4882a593Smuzhiyun 				if (!(status & UART_MSR_CTS)) {
737*4882a593Smuzhiyun 					tty->hw_stopped = 1;
738*4882a593Smuzhiyun 					if ((info->type != PORT_16550A) &&
739*4882a593Smuzhiyun 							(!info->board->chip_flag)) {
740*4882a593Smuzhiyun 						info->IER &= ~UART_IER_THRI;
741*4882a593Smuzhiyun 						outb(info->IER, info->ioaddr +
742*4882a593Smuzhiyun 								UART_IER);
743*4882a593Smuzhiyun 					}
744*4882a593Smuzhiyun 				}
745*4882a593Smuzhiyun 			}
746*4882a593Smuzhiyun 		}
747*4882a593Smuzhiyun 	}
748*4882a593Smuzhiyun 	outb(info->MCR, info->ioaddr + UART_MCR);
749*4882a593Smuzhiyun 	tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
750*4882a593Smuzhiyun 	if (~cflag & CLOCAL)
751*4882a593Smuzhiyun 		info->IER |= UART_IER_MSI;
752*4882a593Smuzhiyun 	outb(info->IER, info->ioaddr + UART_IER);
753*4882a593Smuzhiyun 
754*4882a593Smuzhiyun 	/*
755*4882a593Smuzhiyun 	 * Set up parity check flag
756*4882a593Smuzhiyun 	 */
757*4882a593Smuzhiyun 	info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
758*4882a593Smuzhiyun 	if (I_INPCK(tty))
759*4882a593Smuzhiyun 		info->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
760*4882a593Smuzhiyun 	if (I_BRKINT(tty) || I_PARMRK(tty))
761*4882a593Smuzhiyun 		info->read_status_mask |= UART_LSR_BI;
762*4882a593Smuzhiyun 
763*4882a593Smuzhiyun 	info->ignore_status_mask = 0;
764*4882a593Smuzhiyun 
765*4882a593Smuzhiyun 	if (I_IGNBRK(tty)) {
766*4882a593Smuzhiyun 		info->ignore_status_mask |= UART_LSR_BI;
767*4882a593Smuzhiyun 		info->read_status_mask |= UART_LSR_BI;
768*4882a593Smuzhiyun 		/*
769*4882a593Smuzhiyun 		 * If we're ignore parity and break indicators, ignore
770*4882a593Smuzhiyun 		 * overruns too.  (For real raw support).
771*4882a593Smuzhiyun 		 */
772*4882a593Smuzhiyun 		if (I_IGNPAR(tty)) {
773*4882a593Smuzhiyun 			info->ignore_status_mask |=
774*4882a593Smuzhiyun 						UART_LSR_OE |
775*4882a593Smuzhiyun 						UART_LSR_PE |
776*4882a593Smuzhiyun 						UART_LSR_FE;
777*4882a593Smuzhiyun 			info->read_status_mask |=
778*4882a593Smuzhiyun 						UART_LSR_OE |
779*4882a593Smuzhiyun 						UART_LSR_PE |
780*4882a593Smuzhiyun 						UART_LSR_FE;
781*4882a593Smuzhiyun 		}
782*4882a593Smuzhiyun 	}
783*4882a593Smuzhiyun 	if (info->board->chip_flag) {
784*4882a593Smuzhiyun 		mxser_set_must_xon1_value(info->ioaddr, START_CHAR(tty));
785*4882a593Smuzhiyun 		mxser_set_must_xoff1_value(info->ioaddr, STOP_CHAR(tty));
786*4882a593Smuzhiyun 		if (I_IXON(tty)) {
787*4882a593Smuzhiyun 			mxser_enable_must_rx_software_flow_control(
788*4882a593Smuzhiyun 					info->ioaddr);
789*4882a593Smuzhiyun 		} else {
790*4882a593Smuzhiyun 			mxser_disable_must_rx_software_flow_control(
791*4882a593Smuzhiyun 					info->ioaddr);
792*4882a593Smuzhiyun 		}
793*4882a593Smuzhiyun 		if (I_IXOFF(tty)) {
794*4882a593Smuzhiyun 			mxser_enable_must_tx_software_flow_control(
795*4882a593Smuzhiyun 					info->ioaddr);
796*4882a593Smuzhiyun 		} else {
797*4882a593Smuzhiyun 			mxser_disable_must_tx_software_flow_control(
798*4882a593Smuzhiyun 					info->ioaddr);
799*4882a593Smuzhiyun 		}
800*4882a593Smuzhiyun 	}
801*4882a593Smuzhiyun 
802*4882a593Smuzhiyun 
803*4882a593Smuzhiyun 	outb(fcr, info->ioaddr + UART_FCR);	/* set fcr */
804*4882a593Smuzhiyun 	outb(cval, info->ioaddr + UART_LCR);
805*4882a593Smuzhiyun }
806*4882a593Smuzhiyun 
mxser_check_modem_status(struct tty_struct * tty,struct mxser_port * port,int status)807*4882a593Smuzhiyun static void mxser_check_modem_status(struct tty_struct *tty,
808*4882a593Smuzhiyun 				struct mxser_port *port, int status)
809*4882a593Smuzhiyun {
810*4882a593Smuzhiyun 	/* update input line counters */
811*4882a593Smuzhiyun 	if (status & UART_MSR_TERI)
812*4882a593Smuzhiyun 		port->icount.rng++;
813*4882a593Smuzhiyun 	if (status & UART_MSR_DDSR)
814*4882a593Smuzhiyun 		port->icount.dsr++;
815*4882a593Smuzhiyun 	if (status & UART_MSR_DDCD)
816*4882a593Smuzhiyun 		port->icount.dcd++;
817*4882a593Smuzhiyun 	if (status & UART_MSR_DCTS)
818*4882a593Smuzhiyun 		port->icount.cts++;
819*4882a593Smuzhiyun 	port->mon_data.modem_status = status;
820*4882a593Smuzhiyun 	wake_up_interruptible(&port->port.delta_msr_wait);
821*4882a593Smuzhiyun 
822*4882a593Smuzhiyun 	if (tty_port_check_carrier(&port->port) && (status & UART_MSR_DDCD)) {
823*4882a593Smuzhiyun 		if (status & UART_MSR_DCD)
824*4882a593Smuzhiyun 			wake_up_interruptible(&port->port.open_wait);
825*4882a593Smuzhiyun 	}
826*4882a593Smuzhiyun 
827*4882a593Smuzhiyun 	if (tty_port_cts_enabled(&port->port)) {
828*4882a593Smuzhiyun 		if (tty->hw_stopped) {
829*4882a593Smuzhiyun 			if (status & UART_MSR_CTS) {
830*4882a593Smuzhiyun 				tty->hw_stopped = 0;
831*4882a593Smuzhiyun 
832*4882a593Smuzhiyun 				if ((port->type != PORT_16550A) &&
833*4882a593Smuzhiyun 						(!port->board->chip_flag)) {
834*4882a593Smuzhiyun 					outb(port->IER & ~UART_IER_THRI,
835*4882a593Smuzhiyun 						port->ioaddr + UART_IER);
836*4882a593Smuzhiyun 					port->IER |= UART_IER_THRI;
837*4882a593Smuzhiyun 					outb(port->IER, port->ioaddr +
838*4882a593Smuzhiyun 							UART_IER);
839*4882a593Smuzhiyun 				}
840*4882a593Smuzhiyun 				tty_wakeup(tty);
841*4882a593Smuzhiyun 			}
842*4882a593Smuzhiyun 		} else {
843*4882a593Smuzhiyun 			if (!(status & UART_MSR_CTS)) {
844*4882a593Smuzhiyun 				tty->hw_stopped = 1;
845*4882a593Smuzhiyun 				if (port->type != PORT_16550A &&
846*4882a593Smuzhiyun 						!port->board->chip_flag) {
847*4882a593Smuzhiyun 					port->IER &= ~UART_IER_THRI;
848*4882a593Smuzhiyun 					outb(port->IER, port->ioaddr +
849*4882a593Smuzhiyun 							UART_IER);
850*4882a593Smuzhiyun 				}
851*4882a593Smuzhiyun 			}
852*4882a593Smuzhiyun 		}
853*4882a593Smuzhiyun 	}
854*4882a593Smuzhiyun }
855*4882a593Smuzhiyun 
mxser_activate(struct tty_port * port,struct tty_struct * tty)856*4882a593Smuzhiyun static int mxser_activate(struct tty_port *port, struct tty_struct *tty)
857*4882a593Smuzhiyun {
858*4882a593Smuzhiyun 	struct mxser_port *info = container_of(port, struct mxser_port, port);
859*4882a593Smuzhiyun 	unsigned long page;
860*4882a593Smuzhiyun 	unsigned long flags;
861*4882a593Smuzhiyun 	int ret;
862*4882a593Smuzhiyun 
863*4882a593Smuzhiyun 	page = __get_free_page(GFP_KERNEL);
864*4882a593Smuzhiyun 	if (!page)
865*4882a593Smuzhiyun 		return -ENOMEM;
866*4882a593Smuzhiyun 
867*4882a593Smuzhiyun 	spin_lock_irqsave(&info->slock, flags);
868*4882a593Smuzhiyun 
869*4882a593Smuzhiyun 	if (!info->ioaddr || !info->type) {
870*4882a593Smuzhiyun 		set_bit(TTY_IO_ERROR, &tty->flags);
871*4882a593Smuzhiyun 		spin_unlock_irqrestore(&info->slock, flags);
872*4882a593Smuzhiyun 		ret = 0;
873*4882a593Smuzhiyun 		goto err_free_xmit;
874*4882a593Smuzhiyun 	}
875*4882a593Smuzhiyun 	info->port.xmit_buf = (unsigned char *) page;
876*4882a593Smuzhiyun 
877*4882a593Smuzhiyun 	/*
878*4882a593Smuzhiyun 	 * Clear the FIFO buffers and disable them
879*4882a593Smuzhiyun 	 * (they will be reenabled in mxser_change_speed())
880*4882a593Smuzhiyun 	 */
881*4882a593Smuzhiyun 	if (info->board->chip_flag)
882*4882a593Smuzhiyun 		outb((UART_FCR_CLEAR_RCVR |
883*4882a593Smuzhiyun 			UART_FCR_CLEAR_XMIT |
884*4882a593Smuzhiyun 			MOXA_MUST_FCR_GDA_MODE_ENABLE), info->ioaddr + UART_FCR);
885*4882a593Smuzhiyun 	else
886*4882a593Smuzhiyun 		outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
887*4882a593Smuzhiyun 			info->ioaddr + UART_FCR);
888*4882a593Smuzhiyun 
889*4882a593Smuzhiyun 	/*
890*4882a593Smuzhiyun 	 * At this point there's no way the LSR could still be 0xFF;
891*4882a593Smuzhiyun 	 * if it is, then bail out, because there's likely no UART
892*4882a593Smuzhiyun 	 * here.
893*4882a593Smuzhiyun 	 */
894*4882a593Smuzhiyun 	if (inb(info->ioaddr + UART_LSR) == 0xff) {
895*4882a593Smuzhiyun 		spin_unlock_irqrestore(&info->slock, flags);
896*4882a593Smuzhiyun 		if (capable(CAP_SYS_ADMIN)) {
897*4882a593Smuzhiyun 			set_bit(TTY_IO_ERROR, &tty->flags);
898*4882a593Smuzhiyun 			return 0;
899*4882a593Smuzhiyun 		}
900*4882a593Smuzhiyun 
901*4882a593Smuzhiyun 		ret = -ENODEV;
902*4882a593Smuzhiyun 		goto err_free_xmit;
903*4882a593Smuzhiyun 	}
904*4882a593Smuzhiyun 
905*4882a593Smuzhiyun 	/*
906*4882a593Smuzhiyun 	 * Clear the interrupt registers.
907*4882a593Smuzhiyun 	 */
908*4882a593Smuzhiyun 	(void) inb(info->ioaddr + UART_LSR);
909*4882a593Smuzhiyun 	(void) inb(info->ioaddr + UART_RX);
910*4882a593Smuzhiyun 	(void) inb(info->ioaddr + UART_IIR);
911*4882a593Smuzhiyun 	(void) inb(info->ioaddr + UART_MSR);
912*4882a593Smuzhiyun 
913*4882a593Smuzhiyun 	/*
914*4882a593Smuzhiyun 	 * Now, initialize the UART
915*4882a593Smuzhiyun 	 */
916*4882a593Smuzhiyun 	outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR);	/* reset DLAB */
917*4882a593Smuzhiyun 	info->MCR = UART_MCR_DTR | UART_MCR_RTS;
918*4882a593Smuzhiyun 	outb(info->MCR, info->ioaddr + UART_MCR);
919*4882a593Smuzhiyun 
920*4882a593Smuzhiyun 	/*
921*4882a593Smuzhiyun 	 * Finally, enable interrupts
922*4882a593Smuzhiyun 	 */
923*4882a593Smuzhiyun 	info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
924*4882a593Smuzhiyun 
925*4882a593Smuzhiyun 	if (info->board->chip_flag)
926*4882a593Smuzhiyun 		info->IER |= MOXA_MUST_IER_EGDAI;
927*4882a593Smuzhiyun 	outb(info->IER, info->ioaddr + UART_IER);	/* enable interrupts */
928*4882a593Smuzhiyun 
929*4882a593Smuzhiyun 	/*
930*4882a593Smuzhiyun 	 * And clear the interrupt registers again for luck.
931*4882a593Smuzhiyun 	 */
932*4882a593Smuzhiyun 	(void) inb(info->ioaddr + UART_LSR);
933*4882a593Smuzhiyun 	(void) inb(info->ioaddr + UART_RX);
934*4882a593Smuzhiyun 	(void) inb(info->ioaddr + UART_IIR);
935*4882a593Smuzhiyun 	(void) inb(info->ioaddr + UART_MSR);
936*4882a593Smuzhiyun 
937*4882a593Smuzhiyun 	clear_bit(TTY_IO_ERROR, &tty->flags);
938*4882a593Smuzhiyun 	info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
939*4882a593Smuzhiyun 
940*4882a593Smuzhiyun 	/*
941*4882a593Smuzhiyun 	 * and set the speed of the serial port
942*4882a593Smuzhiyun 	 */
943*4882a593Smuzhiyun 	mxser_change_speed(tty);
944*4882a593Smuzhiyun 	spin_unlock_irqrestore(&info->slock, flags);
945*4882a593Smuzhiyun 
946*4882a593Smuzhiyun 	return 0;
947*4882a593Smuzhiyun err_free_xmit:
948*4882a593Smuzhiyun 	free_page(page);
949*4882a593Smuzhiyun 	info->port.xmit_buf = NULL;
950*4882a593Smuzhiyun 	return ret;
951*4882a593Smuzhiyun }
952*4882a593Smuzhiyun 
953*4882a593Smuzhiyun /*
954*4882a593Smuzhiyun  * This routine will shutdown a serial port
955*4882a593Smuzhiyun  */
mxser_shutdown_port(struct tty_port * port)956*4882a593Smuzhiyun static void mxser_shutdown_port(struct tty_port *port)
957*4882a593Smuzhiyun {
958*4882a593Smuzhiyun 	struct mxser_port *info = container_of(port, struct mxser_port, port);
959*4882a593Smuzhiyun 	unsigned long flags;
960*4882a593Smuzhiyun 
961*4882a593Smuzhiyun 	spin_lock_irqsave(&info->slock, flags);
962*4882a593Smuzhiyun 
963*4882a593Smuzhiyun 	/*
964*4882a593Smuzhiyun 	 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
965*4882a593Smuzhiyun 	 * here so the queue might never be waken up
966*4882a593Smuzhiyun 	 */
967*4882a593Smuzhiyun 	wake_up_interruptible(&info->port.delta_msr_wait);
968*4882a593Smuzhiyun 
969*4882a593Smuzhiyun 	/*
970*4882a593Smuzhiyun 	 * Free the xmit buffer, if necessary
971*4882a593Smuzhiyun 	 */
972*4882a593Smuzhiyun 	if (info->port.xmit_buf) {
973*4882a593Smuzhiyun 		free_page((unsigned long) info->port.xmit_buf);
974*4882a593Smuzhiyun 		info->port.xmit_buf = NULL;
975*4882a593Smuzhiyun 	}
976*4882a593Smuzhiyun 
977*4882a593Smuzhiyun 	info->IER = 0;
978*4882a593Smuzhiyun 	outb(0x00, info->ioaddr + UART_IER);
979*4882a593Smuzhiyun 
980*4882a593Smuzhiyun 	/* clear Rx/Tx FIFO's */
981*4882a593Smuzhiyun 	if (info->board->chip_flag)
982*4882a593Smuzhiyun 		outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT |
983*4882a593Smuzhiyun 				MOXA_MUST_FCR_GDA_MODE_ENABLE,
984*4882a593Smuzhiyun 				info->ioaddr + UART_FCR);
985*4882a593Smuzhiyun 	else
986*4882a593Smuzhiyun 		outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
987*4882a593Smuzhiyun 			info->ioaddr + UART_FCR);
988*4882a593Smuzhiyun 
989*4882a593Smuzhiyun 	/* read data port to reset things */
990*4882a593Smuzhiyun 	(void) inb(info->ioaddr + UART_RX);
991*4882a593Smuzhiyun 
992*4882a593Smuzhiyun 
993*4882a593Smuzhiyun 	if (info->board->chip_flag)
994*4882a593Smuzhiyun 		SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(info->ioaddr);
995*4882a593Smuzhiyun 
996*4882a593Smuzhiyun 	spin_unlock_irqrestore(&info->slock, flags);
997*4882a593Smuzhiyun }
998*4882a593Smuzhiyun 
999*4882a593Smuzhiyun /*
1000*4882a593Smuzhiyun  * This routine is called whenever a serial port is opened.  It
1001*4882a593Smuzhiyun  * enables interrupts for a serial port, linking in its async structure into
1002*4882a593Smuzhiyun  * the IRQ chain.   It also performs the serial-specific
1003*4882a593Smuzhiyun  * initialization for the tty structure.
1004*4882a593Smuzhiyun  */
mxser_open(struct tty_struct * tty,struct file * filp)1005*4882a593Smuzhiyun static int mxser_open(struct tty_struct *tty, struct file *filp)
1006*4882a593Smuzhiyun {
1007*4882a593Smuzhiyun 	struct mxser_port *info;
1008*4882a593Smuzhiyun 	int line;
1009*4882a593Smuzhiyun 
1010*4882a593Smuzhiyun 	line = tty->index;
1011*4882a593Smuzhiyun 	if (line == MXSER_PORTS)
1012*4882a593Smuzhiyun 		return 0;
1013*4882a593Smuzhiyun 	info = &mxser_boards[line / MXSER_PORTS_PER_BOARD].ports[line % MXSER_PORTS_PER_BOARD];
1014*4882a593Smuzhiyun 	if (!info->ioaddr)
1015*4882a593Smuzhiyun 		return -ENODEV;
1016*4882a593Smuzhiyun 
1017*4882a593Smuzhiyun 	tty->driver_data = info;
1018*4882a593Smuzhiyun 	return tty_port_open(&info->port, tty, filp);
1019*4882a593Smuzhiyun }
1020*4882a593Smuzhiyun 
mxser_flush_buffer(struct tty_struct * tty)1021*4882a593Smuzhiyun static void mxser_flush_buffer(struct tty_struct *tty)
1022*4882a593Smuzhiyun {
1023*4882a593Smuzhiyun 	struct mxser_port *info = tty->driver_data;
1024*4882a593Smuzhiyun 	char fcr;
1025*4882a593Smuzhiyun 	unsigned long flags;
1026*4882a593Smuzhiyun 
1027*4882a593Smuzhiyun 
1028*4882a593Smuzhiyun 	spin_lock_irqsave(&info->slock, flags);
1029*4882a593Smuzhiyun 	info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1030*4882a593Smuzhiyun 
1031*4882a593Smuzhiyun 	fcr = inb(info->ioaddr + UART_FCR);
1032*4882a593Smuzhiyun 	outb((fcr | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
1033*4882a593Smuzhiyun 		info->ioaddr + UART_FCR);
1034*4882a593Smuzhiyun 	outb(fcr, info->ioaddr + UART_FCR);
1035*4882a593Smuzhiyun 
1036*4882a593Smuzhiyun 	spin_unlock_irqrestore(&info->slock, flags);
1037*4882a593Smuzhiyun 
1038*4882a593Smuzhiyun 	tty_wakeup(tty);
1039*4882a593Smuzhiyun }
1040*4882a593Smuzhiyun 
1041*4882a593Smuzhiyun 
mxser_close_port(struct tty_port * port)1042*4882a593Smuzhiyun static void mxser_close_port(struct tty_port *port)
1043*4882a593Smuzhiyun {
1044*4882a593Smuzhiyun 	struct mxser_port *info = container_of(port, struct mxser_port, port);
1045*4882a593Smuzhiyun 	unsigned long timeout;
1046*4882a593Smuzhiyun 	/*
1047*4882a593Smuzhiyun 	 * At this point we stop accepting input.  To do this, we
1048*4882a593Smuzhiyun 	 * disable the receive line status interrupts, and tell the
1049*4882a593Smuzhiyun 	 * interrupt driver to stop checking the data ready bit in the
1050*4882a593Smuzhiyun 	 * line status register.
1051*4882a593Smuzhiyun 	 */
1052*4882a593Smuzhiyun 	info->IER &= ~UART_IER_RLSI;
1053*4882a593Smuzhiyun 	if (info->board->chip_flag)
1054*4882a593Smuzhiyun 		info->IER &= ~MOXA_MUST_RECV_ISR;
1055*4882a593Smuzhiyun 
1056*4882a593Smuzhiyun 	outb(info->IER, info->ioaddr + UART_IER);
1057*4882a593Smuzhiyun 	/*
1058*4882a593Smuzhiyun 	 * Before we drop DTR, make sure the UART transmitter
1059*4882a593Smuzhiyun 	 * has completely drained; this is especially
1060*4882a593Smuzhiyun 	 * important if there is a transmit FIFO!
1061*4882a593Smuzhiyun 	 */
1062*4882a593Smuzhiyun 	timeout = jiffies + HZ;
1063*4882a593Smuzhiyun 	while (!(inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT)) {
1064*4882a593Smuzhiyun 		schedule_timeout_interruptible(5);
1065*4882a593Smuzhiyun 		if (time_after(jiffies, timeout))
1066*4882a593Smuzhiyun 			break;
1067*4882a593Smuzhiyun 	}
1068*4882a593Smuzhiyun }
1069*4882a593Smuzhiyun 
1070*4882a593Smuzhiyun /*
1071*4882a593Smuzhiyun  * This routine is called when the serial port gets closed.  First, we
1072*4882a593Smuzhiyun  * wait for the last remaining data to be sent.  Then, we unlink its
1073*4882a593Smuzhiyun  * async structure from the interrupt chain if necessary, and we free
1074*4882a593Smuzhiyun  * that IRQ if nothing is left in the chain.
1075*4882a593Smuzhiyun  */
mxser_close(struct tty_struct * tty,struct file * filp)1076*4882a593Smuzhiyun static void mxser_close(struct tty_struct *tty, struct file *filp)
1077*4882a593Smuzhiyun {
1078*4882a593Smuzhiyun 	struct mxser_port *info = tty->driver_data;
1079*4882a593Smuzhiyun 	struct tty_port *port = &info->port;
1080*4882a593Smuzhiyun 
1081*4882a593Smuzhiyun 	if (tty->index == MXSER_PORTS || info == NULL)
1082*4882a593Smuzhiyun 		return;
1083*4882a593Smuzhiyun 	if (tty_port_close_start(port, tty, filp) == 0)
1084*4882a593Smuzhiyun 		return;
1085*4882a593Smuzhiyun 	info->closing = 1;
1086*4882a593Smuzhiyun 	mutex_lock(&port->mutex);
1087*4882a593Smuzhiyun 	mxser_close_port(port);
1088*4882a593Smuzhiyun 	mxser_flush_buffer(tty);
1089*4882a593Smuzhiyun 	if (tty_port_initialized(port) && C_HUPCL(tty))
1090*4882a593Smuzhiyun 		tty_port_lower_dtr_rts(port);
1091*4882a593Smuzhiyun 	mxser_shutdown_port(port);
1092*4882a593Smuzhiyun 	tty_port_set_initialized(port, 0);
1093*4882a593Smuzhiyun 	mutex_unlock(&port->mutex);
1094*4882a593Smuzhiyun 	info->closing = 0;
1095*4882a593Smuzhiyun 	/* Right now the tty_port set is done outside of the close_end helper
1096*4882a593Smuzhiyun 	   as we don't yet have everyone using refcounts */
1097*4882a593Smuzhiyun 	tty_port_close_end(port, tty);
1098*4882a593Smuzhiyun 	tty_port_tty_set(port, NULL);
1099*4882a593Smuzhiyun }
1100*4882a593Smuzhiyun 
mxser_write(struct tty_struct * tty,const unsigned char * buf,int count)1101*4882a593Smuzhiyun static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count)
1102*4882a593Smuzhiyun {
1103*4882a593Smuzhiyun 	int c, total = 0;
1104*4882a593Smuzhiyun 	struct mxser_port *info = tty->driver_data;
1105*4882a593Smuzhiyun 	unsigned long flags;
1106*4882a593Smuzhiyun 
1107*4882a593Smuzhiyun 	if (!info->port.xmit_buf)
1108*4882a593Smuzhiyun 		return 0;
1109*4882a593Smuzhiyun 
1110*4882a593Smuzhiyun 	while (1) {
1111*4882a593Smuzhiyun 		c = min_t(int, count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
1112*4882a593Smuzhiyun 					  SERIAL_XMIT_SIZE - info->xmit_head));
1113*4882a593Smuzhiyun 		if (c <= 0)
1114*4882a593Smuzhiyun 			break;
1115*4882a593Smuzhiyun 
1116*4882a593Smuzhiyun 		memcpy(info->port.xmit_buf + info->xmit_head, buf, c);
1117*4882a593Smuzhiyun 		spin_lock_irqsave(&info->slock, flags);
1118*4882a593Smuzhiyun 		info->xmit_head = (info->xmit_head + c) &
1119*4882a593Smuzhiyun 				  (SERIAL_XMIT_SIZE - 1);
1120*4882a593Smuzhiyun 		info->xmit_cnt += c;
1121*4882a593Smuzhiyun 		spin_unlock_irqrestore(&info->slock, flags);
1122*4882a593Smuzhiyun 
1123*4882a593Smuzhiyun 		buf += c;
1124*4882a593Smuzhiyun 		count -= c;
1125*4882a593Smuzhiyun 		total += c;
1126*4882a593Smuzhiyun 	}
1127*4882a593Smuzhiyun 
1128*4882a593Smuzhiyun 	if (info->xmit_cnt && !tty->stopped) {
1129*4882a593Smuzhiyun 		if (!tty->hw_stopped ||
1130*4882a593Smuzhiyun 				(info->type == PORT_16550A) ||
1131*4882a593Smuzhiyun 				(info->board->chip_flag)) {
1132*4882a593Smuzhiyun 			spin_lock_irqsave(&info->slock, flags);
1133*4882a593Smuzhiyun 			outb(info->IER & ~UART_IER_THRI, info->ioaddr +
1134*4882a593Smuzhiyun 					UART_IER);
1135*4882a593Smuzhiyun 			info->IER |= UART_IER_THRI;
1136*4882a593Smuzhiyun 			outb(info->IER, info->ioaddr + UART_IER);
1137*4882a593Smuzhiyun 			spin_unlock_irqrestore(&info->slock, flags);
1138*4882a593Smuzhiyun 		}
1139*4882a593Smuzhiyun 	}
1140*4882a593Smuzhiyun 	return total;
1141*4882a593Smuzhiyun }
1142*4882a593Smuzhiyun 
mxser_put_char(struct tty_struct * tty,unsigned char ch)1143*4882a593Smuzhiyun static int mxser_put_char(struct tty_struct *tty, unsigned char ch)
1144*4882a593Smuzhiyun {
1145*4882a593Smuzhiyun 	struct mxser_port *info = tty->driver_data;
1146*4882a593Smuzhiyun 	unsigned long flags;
1147*4882a593Smuzhiyun 
1148*4882a593Smuzhiyun 	if (!info->port.xmit_buf)
1149*4882a593Smuzhiyun 		return 0;
1150*4882a593Smuzhiyun 
1151*4882a593Smuzhiyun 	if (info->xmit_cnt >= SERIAL_XMIT_SIZE - 1)
1152*4882a593Smuzhiyun 		return 0;
1153*4882a593Smuzhiyun 
1154*4882a593Smuzhiyun 	spin_lock_irqsave(&info->slock, flags);
1155*4882a593Smuzhiyun 	info->port.xmit_buf[info->xmit_head++] = ch;
1156*4882a593Smuzhiyun 	info->xmit_head &= SERIAL_XMIT_SIZE - 1;
1157*4882a593Smuzhiyun 	info->xmit_cnt++;
1158*4882a593Smuzhiyun 	spin_unlock_irqrestore(&info->slock, flags);
1159*4882a593Smuzhiyun 	if (!tty->stopped) {
1160*4882a593Smuzhiyun 		if (!tty->hw_stopped ||
1161*4882a593Smuzhiyun 				(info->type == PORT_16550A) ||
1162*4882a593Smuzhiyun 				info->board->chip_flag) {
1163*4882a593Smuzhiyun 			spin_lock_irqsave(&info->slock, flags);
1164*4882a593Smuzhiyun 			outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1165*4882a593Smuzhiyun 			info->IER |= UART_IER_THRI;
1166*4882a593Smuzhiyun 			outb(info->IER, info->ioaddr + UART_IER);
1167*4882a593Smuzhiyun 			spin_unlock_irqrestore(&info->slock, flags);
1168*4882a593Smuzhiyun 		}
1169*4882a593Smuzhiyun 	}
1170*4882a593Smuzhiyun 	return 1;
1171*4882a593Smuzhiyun }
1172*4882a593Smuzhiyun 
1173*4882a593Smuzhiyun 
mxser_flush_chars(struct tty_struct * tty)1174*4882a593Smuzhiyun static void mxser_flush_chars(struct tty_struct *tty)
1175*4882a593Smuzhiyun {
1176*4882a593Smuzhiyun 	struct mxser_port *info = tty->driver_data;
1177*4882a593Smuzhiyun 	unsigned long flags;
1178*4882a593Smuzhiyun 
1179*4882a593Smuzhiyun 	if (info->xmit_cnt <= 0 || tty->stopped || !info->port.xmit_buf ||
1180*4882a593Smuzhiyun 			(tty->hw_stopped && info->type != PORT_16550A &&
1181*4882a593Smuzhiyun 			 !info->board->chip_flag))
1182*4882a593Smuzhiyun 		return;
1183*4882a593Smuzhiyun 
1184*4882a593Smuzhiyun 	spin_lock_irqsave(&info->slock, flags);
1185*4882a593Smuzhiyun 
1186*4882a593Smuzhiyun 	outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1187*4882a593Smuzhiyun 	info->IER |= UART_IER_THRI;
1188*4882a593Smuzhiyun 	outb(info->IER, info->ioaddr + UART_IER);
1189*4882a593Smuzhiyun 
1190*4882a593Smuzhiyun 	spin_unlock_irqrestore(&info->slock, flags);
1191*4882a593Smuzhiyun }
1192*4882a593Smuzhiyun 
mxser_write_room(struct tty_struct * tty)1193*4882a593Smuzhiyun static int mxser_write_room(struct tty_struct *tty)
1194*4882a593Smuzhiyun {
1195*4882a593Smuzhiyun 	struct mxser_port *info = tty->driver_data;
1196*4882a593Smuzhiyun 	int ret;
1197*4882a593Smuzhiyun 
1198*4882a593Smuzhiyun 	ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
1199*4882a593Smuzhiyun 	return ret < 0 ? 0 : ret;
1200*4882a593Smuzhiyun }
1201*4882a593Smuzhiyun 
mxser_chars_in_buffer(struct tty_struct * tty)1202*4882a593Smuzhiyun static int mxser_chars_in_buffer(struct tty_struct *tty)
1203*4882a593Smuzhiyun {
1204*4882a593Smuzhiyun 	struct mxser_port *info = tty->driver_data;
1205*4882a593Smuzhiyun 	return info->xmit_cnt;
1206*4882a593Smuzhiyun }
1207*4882a593Smuzhiyun 
1208*4882a593Smuzhiyun /*
1209*4882a593Smuzhiyun  * ------------------------------------------------------------
1210*4882a593Smuzhiyun  * friends of mxser_ioctl()
1211*4882a593Smuzhiyun  * ------------------------------------------------------------
1212*4882a593Smuzhiyun  */
mxser_get_serial_info(struct tty_struct * tty,struct serial_struct * ss)1213*4882a593Smuzhiyun static int mxser_get_serial_info(struct tty_struct *tty,
1214*4882a593Smuzhiyun 		struct serial_struct *ss)
1215*4882a593Smuzhiyun {
1216*4882a593Smuzhiyun 	struct mxser_port *info = tty->driver_data;
1217*4882a593Smuzhiyun 	struct tty_port *port = &info->port;
1218*4882a593Smuzhiyun 
1219*4882a593Smuzhiyun 	if (tty->index == MXSER_PORTS)
1220*4882a593Smuzhiyun 		return -ENOTTY;
1221*4882a593Smuzhiyun 
1222*4882a593Smuzhiyun 	mutex_lock(&port->mutex);
1223*4882a593Smuzhiyun 	ss->type = info->type,
1224*4882a593Smuzhiyun 	ss->line = tty->index,
1225*4882a593Smuzhiyun 	ss->port = info->ioaddr,
1226*4882a593Smuzhiyun 	ss->irq = info->board->irq,
1227*4882a593Smuzhiyun 	ss->flags = info->port.flags,
1228*4882a593Smuzhiyun 	ss->baud_base = info->baud_base,
1229*4882a593Smuzhiyun 	ss->close_delay = info->port.close_delay,
1230*4882a593Smuzhiyun 	ss->closing_wait = info->port.closing_wait,
1231*4882a593Smuzhiyun 	ss->custom_divisor = info->custom_divisor,
1232*4882a593Smuzhiyun 	mutex_unlock(&port->mutex);
1233*4882a593Smuzhiyun 	return 0;
1234*4882a593Smuzhiyun }
1235*4882a593Smuzhiyun 
mxser_set_serial_info(struct tty_struct * tty,struct serial_struct * ss)1236*4882a593Smuzhiyun static int mxser_set_serial_info(struct tty_struct *tty,
1237*4882a593Smuzhiyun 		struct serial_struct *ss)
1238*4882a593Smuzhiyun {
1239*4882a593Smuzhiyun 	struct mxser_port *info = tty->driver_data;
1240*4882a593Smuzhiyun 	struct tty_port *port = &info->port;
1241*4882a593Smuzhiyun 	speed_t baud;
1242*4882a593Smuzhiyun 	unsigned long sl_flags;
1243*4882a593Smuzhiyun 	unsigned int flags;
1244*4882a593Smuzhiyun 	int retval = 0;
1245*4882a593Smuzhiyun 
1246*4882a593Smuzhiyun 	if (tty->index == MXSER_PORTS)
1247*4882a593Smuzhiyun 		return -ENOTTY;
1248*4882a593Smuzhiyun 	if (tty_io_error(tty))
1249*4882a593Smuzhiyun 		return -EIO;
1250*4882a593Smuzhiyun 
1251*4882a593Smuzhiyun 	mutex_lock(&port->mutex);
1252*4882a593Smuzhiyun 	if (!info->ioaddr) {
1253*4882a593Smuzhiyun 		mutex_unlock(&port->mutex);
1254*4882a593Smuzhiyun 		return -ENODEV;
1255*4882a593Smuzhiyun 	}
1256*4882a593Smuzhiyun 
1257*4882a593Smuzhiyun 	if (ss->irq != info->board->irq ||
1258*4882a593Smuzhiyun 			ss->port != info->ioaddr) {
1259*4882a593Smuzhiyun 		mutex_unlock(&port->mutex);
1260*4882a593Smuzhiyun 		return -EINVAL;
1261*4882a593Smuzhiyun 	}
1262*4882a593Smuzhiyun 
1263*4882a593Smuzhiyun 	flags = port->flags & ASYNC_SPD_MASK;
1264*4882a593Smuzhiyun 
1265*4882a593Smuzhiyun 	if (!capable(CAP_SYS_ADMIN)) {
1266*4882a593Smuzhiyun 		if ((ss->baud_base != info->baud_base) ||
1267*4882a593Smuzhiyun 				(ss->close_delay != info->port.close_delay) ||
1268*4882a593Smuzhiyun 				((ss->flags & ~ASYNC_USR_MASK) != (info->port.flags & ~ASYNC_USR_MASK))) {
1269*4882a593Smuzhiyun 			mutex_unlock(&port->mutex);
1270*4882a593Smuzhiyun 			return -EPERM;
1271*4882a593Smuzhiyun 		}
1272*4882a593Smuzhiyun 		info->port.flags = ((info->port.flags & ~ASYNC_USR_MASK) |
1273*4882a593Smuzhiyun 				(ss->flags & ASYNC_USR_MASK));
1274*4882a593Smuzhiyun 	} else {
1275*4882a593Smuzhiyun 		/*
1276*4882a593Smuzhiyun 		 * OK, past this point, all the error checking has been done.
1277*4882a593Smuzhiyun 		 * At this point, we start making changes.....
1278*4882a593Smuzhiyun 		 */
1279*4882a593Smuzhiyun 		port->flags = ((port->flags & ~ASYNC_FLAGS) |
1280*4882a593Smuzhiyun 				(ss->flags & ASYNC_FLAGS));
1281*4882a593Smuzhiyun 		port->close_delay = ss->close_delay * HZ / 100;
1282*4882a593Smuzhiyun 		port->closing_wait = ss->closing_wait * HZ / 100;
1283*4882a593Smuzhiyun 		port->low_latency = (port->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
1284*4882a593Smuzhiyun 		if ((port->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST &&
1285*4882a593Smuzhiyun 				(ss->baud_base != info->baud_base ||
1286*4882a593Smuzhiyun 				ss->custom_divisor !=
1287*4882a593Smuzhiyun 				info->custom_divisor)) {
1288*4882a593Smuzhiyun 			if (ss->custom_divisor == 0) {
1289*4882a593Smuzhiyun 				mutex_unlock(&port->mutex);
1290*4882a593Smuzhiyun 				return -EINVAL;
1291*4882a593Smuzhiyun 			}
1292*4882a593Smuzhiyun 			baud = ss->baud_base / ss->custom_divisor;
1293*4882a593Smuzhiyun 			tty_encode_baud_rate(tty, baud, baud);
1294*4882a593Smuzhiyun 		}
1295*4882a593Smuzhiyun 	}
1296*4882a593Smuzhiyun 
1297*4882a593Smuzhiyun 	info->type = ss->type;
1298*4882a593Smuzhiyun 
1299*4882a593Smuzhiyun 	process_txrx_fifo(info);
1300*4882a593Smuzhiyun 
1301*4882a593Smuzhiyun 	if (tty_port_initialized(port)) {
1302*4882a593Smuzhiyun 		if (flags != (port->flags & ASYNC_SPD_MASK)) {
1303*4882a593Smuzhiyun 			spin_lock_irqsave(&info->slock, sl_flags);
1304*4882a593Smuzhiyun 			mxser_change_speed(tty);
1305*4882a593Smuzhiyun 			spin_unlock_irqrestore(&info->slock, sl_flags);
1306*4882a593Smuzhiyun 		}
1307*4882a593Smuzhiyun 	} else {
1308*4882a593Smuzhiyun 		retval = mxser_activate(port, tty);
1309*4882a593Smuzhiyun 		if (retval == 0)
1310*4882a593Smuzhiyun 			tty_port_set_initialized(port, 1);
1311*4882a593Smuzhiyun 	}
1312*4882a593Smuzhiyun 	mutex_unlock(&port->mutex);
1313*4882a593Smuzhiyun 	return retval;
1314*4882a593Smuzhiyun }
1315*4882a593Smuzhiyun 
1316*4882a593Smuzhiyun /*
1317*4882a593Smuzhiyun  * mxser_get_lsr_info - get line status register info
1318*4882a593Smuzhiyun  *
1319*4882a593Smuzhiyun  * Purpose: Let user call ioctl() to get info when the UART physically
1320*4882a593Smuzhiyun  *	    is emptied.  On bus types like RS485, the transmitter must
1321*4882a593Smuzhiyun  *	    release the bus after transmitting. This must be done when
1322*4882a593Smuzhiyun  *	    the transmit shift register is empty, not be done when the
1323*4882a593Smuzhiyun  *	    transmit holding register is empty.  This functionality
1324*4882a593Smuzhiyun  *	    allows an RS485 driver to be written in user space.
1325*4882a593Smuzhiyun  */
mxser_get_lsr_info(struct mxser_port * info,unsigned int __user * value)1326*4882a593Smuzhiyun static int mxser_get_lsr_info(struct mxser_port *info,
1327*4882a593Smuzhiyun 		unsigned int __user *value)
1328*4882a593Smuzhiyun {
1329*4882a593Smuzhiyun 	unsigned char status;
1330*4882a593Smuzhiyun 	unsigned int result;
1331*4882a593Smuzhiyun 	unsigned long flags;
1332*4882a593Smuzhiyun 
1333*4882a593Smuzhiyun 	spin_lock_irqsave(&info->slock, flags);
1334*4882a593Smuzhiyun 	status = inb(info->ioaddr + UART_LSR);
1335*4882a593Smuzhiyun 	spin_unlock_irqrestore(&info->slock, flags);
1336*4882a593Smuzhiyun 	result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
1337*4882a593Smuzhiyun 	return put_user(result, value);
1338*4882a593Smuzhiyun }
1339*4882a593Smuzhiyun 
mxser_tiocmget(struct tty_struct * tty)1340*4882a593Smuzhiyun static int mxser_tiocmget(struct tty_struct *tty)
1341*4882a593Smuzhiyun {
1342*4882a593Smuzhiyun 	struct mxser_port *info = tty->driver_data;
1343*4882a593Smuzhiyun 	unsigned char control, status;
1344*4882a593Smuzhiyun 	unsigned long flags;
1345*4882a593Smuzhiyun 
1346*4882a593Smuzhiyun 
1347*4882a593Smuzhiyun 	if (tty->index == MXSER_PORTS)
1348*4882a593Smuzhiyun 		return -ENOIOCTLCMD;
1349*4882a593Smuzhiyun 	if (tty_io_error(tty))
1350*4882a593Smuzhiyun 		return -EIO;
1351*4882a593Smuzhiyun 
1352*4882a593Smuzhiyun 	control = info->MCR;
1353*4882a593Smuzhiyun 
1354*4882a593Smuzhiyun 	spin_lock_irqsave(&info->slock, flags);
1355*4882a593Smuzhiyun 	status = inb(info->ioaddr + UART_MSR);
1356*4882a593Smuzhiyun 	if (status & UART_MSR_ANY_DELTA)
1357*4882a593Smuzhiyun 		mxser_check_modem_status(tty, info, status);
1358*4882a593Smuzhiyun 	spin_unlock_irqrestore(&info->slock, flags);
1359*4882a593Smuzhiyun 	return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) |
1360*4882a593Smuzhiyun 		    ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) |
1361*4882a593Smuzhiyun 		    ((status & UART_MSR_DCD) ? TIOCM_CAR : 0) |
1362*4882a593Smuzhiyun 		    ((status & UART_MSR_RI) ? TIOCM_RNG : 0) |
1363*4882a593Smuzhiyun 		    ((status & UART_MSR_DSR) ? TIOCM_DSR : 0) |
1364*4882a593Smuzhiyun 		    ((status & UART_MSR_CTS) ? TIOCM_CTS : 0);
1365*4882a593Smuzhiyun }
1366*4882a593Smuzhiyun 
mxser_tiocmset(struct tty_struct * tty,unsigned int set,unsigned int clear)1367*4882a593Smuzhiyun static int mxser_tiocmset(struct tty_struct *tty,
1368*4882a593Smuzhiyun 		unsigned int set, unsigned int clear)
1369*4882a593Smuzhiyun {
1370*4882a593Smuzhiyun 	struct mxser_port *info = tty->driver_data;
1371*4882a593Smuzhiyun 	unsigned long flags;
1372*4882a593Smuzhiyun 
1373*4882a593Smuzhiyun 
1374*4882a593Smuzhiyun 	if (tty->index == MXSER_PORTS)
1375*4882a593Smuzhiyun 		return -ENOIOCTLCMD;
1376*4882a593Smuzhiyun 	if (tty_io_error(tty))
1377*4882a593Smuzhiyun 		return -EIO;
1378*4882a593Smuzhiyun 
1379*4882a593Smuzhiyun 	spin_lock_irqsave(&info->slock, flags);
1380*4882a593Smuzhiyun 
1381*4882a593Smuzhiyun 	if (set & TIOCM_RTS)
1382*4882a593Smuzhiyun 		info->MCR |= UART_MCR_RTS;
1383*4882a593Smuzhiyun 	if (set & TIOCM_DTR)
1384*4882a593Smuzhiyun 		info->MCR |= UART_MCR_DTR;
1385*4882a593Smuzhiyun 
1386*4882a593Smuzhiyun 	if (clear & TIOCM_RTS)
1387*4882a593Smuzhiyun 		info->MCR &= ~UART_MCR_RTS;
1388*4882a593Smuzhiyun 	if (clear & TIOCM_DTR)
1389*4882a593Smuzhiyun 		info->MCR &= ~UART_MCR_DTR;
1390*4882a593Smuzhiyun 
1391*4882a593Smuzhiyun 	outb(info->MCR, info->ioaddr + UART_MCR);
1392*4882a593Smuzhiyun 	spin_unlock_irqrestore(&info->slock, flags);
1393*4882a593Smuzhiyun 	return 0;
1394*4882a593Smuzhiyun }
1395*4882a593Smuzhiyun 
mxser_program_mode(int port)1396*4882a593Smuzhiyun static int __init mxser_program_mode(int port)
1397*4882a593Smuzhiyun {
1398*4882a593Smuzhiyun 	int id, i, j, n;
1399*4882a593Smuzhiyun 
1400*4882a593Smuzhiyun 	outb(0, port);
1401*4882a593Smuzhiyun 	outb(0, port);
1402*4882a593Smuzhiyun 	outb(0, port);
1403*4882a593Smuzhiyun 	(void)inb(port);
1404*4882a593Smuzhiyun 	(void)inb(port);
1405*4882a593Smuzhiyun 	outb(0, port);
1406*4882a593Smuzhiyun 	(void)inb(port);
1407*4882a593Smuzhiyun 
1408*4882a593Smuzhiyun 	id = inb(port + 1) & 0x1F;
1409*4882a593Smuzhiyun 	if ((id != C168_ASIC_ID) &&
1410*4882a593Smuzhiyun 			(id != C104_ASIC_ID) &&
1411*4882a593Smuzhiyun 			(id != C102_ASIC_ID) &&
1412*4882a593Smuzhiyun 			(id != CI132_ASIC_ID) &&
1413*4882a593Smuzhiyun 			(id != CI134_ASIC_ID) &&
1414*4882a593Smuzhiyun 			(id != CI104J_ASIC_ID))
1415*4882a593Smuzhiyun 		return -1;
1416*4882a593Smuzhiyun 	for (i = 0, j = 0; i < 4; i++) {
1417*4882a593Smuzhiyun 		n = inb(port + 2);
1418*4882a593Smuzhiyun 		if (n == 'M') {
1419*4882a593Smuzhiyun 			j = 1;
1420*4882a593Smuzhiyun 		} else if ((j == 1) && (n == 1)) {
1421*4882a593Smuzhiyun 			j = 2;
1422*4882a593Smuzhiyun 			break;
1423*4882a593Smuzhiyun 		} else
1424*4882a593Smuzhiyun 			j = 0;
1425*4882a593Smuzhiyun 	}
1426*4882a593Smuzhiyun 	if (j != 2)
1427*4882a593Smuzhiyun 		id = -2;
1428*4882a593Smuzhiyun 	return id;
1429*4882a593Smuzhiyun }
1430*4882a593Smuzhiyun 
mxser_normal_mode(int port)1431*4882a593Smuzhiyun static void __init mxser_normal_mode(int port)
1432*4882a593Smuzhiyun {
1433*4882a593Smuzhiyun 	int i, n;
1434*4882a593Smuzhiyun 
1435*4882a593Smuzhiyun 	outb(0xA5, port + 1);
1436*4882a593Smuzhiyun 	outb(0x80, port + 3);
1437*4882a593Smuzhiyun 	outb(12, port + 0);	/* 9600 bps */
1438*4882a593Smuzhiyun 	outb(0, port + 1);
1439*4882a593Smuzhiyun 	outb(0x03, port + 3);	/* 8 data bits */
1440*4882a593Smuzhiyun 	outb(0x13, port + 4);	/* loop back mode */
1441*4882a593Smuzhiyun 	for (i = 0; i < 16; i++) {
1442*4882a593Smuzhiyun 		n = inb(port + 5);
1443*4882a593Smuzhiyun 		if ((n & 0x61) == 0x60)
1444*4882a593Smuzhiyun 			break;
1445*4882a593Smuzhiyun 		if ((n & 1) == 1)
1446*4882a593Smuzhiyun 			(void)inb(port);
1447*4882a593Smuzhiyun 	}
1448*4882a593Smuzhiyun 	outb(0x00, port + 4);
1449*4882a593Smuzhiyun }
1450*4882a593Smuzhiyun 
1451*4882a593Smuzhiyun #define CHIP_SK 	0x01	/* Serial Data Clock  in Eprom */
1452*4882a593Smuzhiyun #define CHIP_DO 	0x02	/* Serial Data Output in Eprom */
1453*4882a593Smuzhiyun #define CHIP_CS 	0x04	/* Serial Chip Select in Eprom */
1454*4882a593Smuzhiyun #define CHIP_DI 	0x08	/* Serial Data Input  in Eprom */
1455*4882a593Smuzhiyun #define EN_CCMD 	0x000	/* Chip's command register     */
1456*4882a593Smuzhiyun #define EN0_RSARLO	0x008	/* Remote start address reg 0  */
1457*4882a593Smuzhiyun #define EN0_RSARHI	0x009	/* Remote start address reg 1  */
1458*4882a593Smuzhiyun #define EN0_RCNTLO	0x00A	/* Remote byte count reg WR    */
1459*4882a593Smuzhiyun #define EN0_RCNTHI	0x00B	/* Remote byte count reg WR    */
1460*4882a593Smuzhiyun #define EN0_DCFG	0x00E	/* Data configuration reg WR   */
1461*4882a593Smuzhiyun #define EN0_PORT	0x010	/* Rcv missed frame error counter RD */
1462*4882a593Smuzhiyun #define ENC_PAGE0	0x000	/* Select page 0 of chip registers   */
1463*4882a593Smuzhiyun #define ENC_PAGE3	0x0C0	/* Select page 3 of chip registers   */
mxser_read_register(int port,unsigned short * regs)1464*4882a593Smuzhiyun static int __init mxser_read_register(int port, unsigned short *regs)
1465*4882a593Smuzhiyun {
1466*4882a593Smuzhiyun 	int i, k, value, id;
1467*4882a593Smuzhiyun 	unsigned int j;
1468*4882a593Smuzhiyun 
1469*4882a593Smuzhiyun 	id = mxser_program_mode(port);
1470*4882a593Smuzhiyun 	if (id < 0)
1471*4882a593Smuzhiyun 		return id;
1472*4882a593Smuzhiyun 	for (i = 0; i < 14; i++) {
1473*4882a593Smuzhiyun 		k = (i & 0x3F) | 0x180;
1474*4882a593Smuzhiyun 		for (j = 0x100; j > 0; j >>= 1) {
1475*4882a593Smuzhiyun 			outb(CHIP_CS, port);
1476*4882a593Smuzhiyun 			if (k & j) {
1477*4882a593Smuzhiyun 				outb(CHIP_CS | CHIP_DO, port);
1478*4882a593Smuzhiyun 				outb(CHIP_CS | CHIP_DO | CHIP_SK, port);	/* A? bit of read */
1479*4882a593Smuzhiyun 			} else {
1480*4882a593Smuzhiyun 				outb(CHIP_CS, port);
1481*4882a593Smuzhiyun 				outb(CHIP_CS | CHIP_SK, port);	/* A? bit of read */
1482*4882a593Smuzhiyun 			}
1483*4882a593Smuzhiyun 		}
1484*4882a593Smuzhiyun 		(void)inb(port);
1485*4882a593Smuzhiyun 		value = 0;
1486*4882a593Smuzhiyun 		for (k = 0, j = 0x8000; k < 16; k++, j >>= 1) {
1487*4882a593Smuzhiyun 			outb(CHIP_CS, port);
1488*4882a593Smuzhiyun 			outb(CHIP_CS | CHIP_SK, port);
1489*4882a593Smuzhiyun 			if (inb(port) & CHIP_DI)
1490*4882a593Smuzhiyun 				value |= j;
1491*4882a593Smuzhiyun 		}
1492*4882a593Smuzhiyun 		regs[i] = value;
1493*4882a593Smuzhiyun 		outb(0, port);
1494*4882a593Smuzhiyun 	}
1495*4882a593Smuzhiyun 	mxser_normal_mode(port);
1496*4882a593Smuzhiyun 	return id;
1497*4882a593Smuzhiyun }
1498*4882a593Smuzhiyun 
mxser_ioctl_special(unsigned int cmd,void __user * argp)1499*4882a593Smuzhiyun static int mxser_ioctl_special(unsigned int cmd, void __user *argp)
1500*4882a593Smuzhiyun {
1501*4882a593Smuzhiyun 	struct mxser_port *ip;
1502*4882a593Smuzhiyun 	struct tty_port *port;
1503*4882a593Smuzhiyun 	struct tty_struct *tty;
1504*4882a593Smuzhiyun 	int result, status;
1505*4882a593Smuzhiyun 	unsigned int i, j;
1506*4882a593Smuzhiyun 	int ret = 0;
1507*4882a593Smuzhiyun 
1508*4882a593Smuzhiyun 	switch (cmd) {
1509*4882a593Smuzhiyun 	case MOXA_GET_MAJOR:
1510*4882a593Smuzhiyun 		printk_ratelimited(KERN_WARNING "mxser: '%s' uses deprecated ioctl "
1511*4882a593Smuzhiyun 					"%x (GET_MAJOR), fix your userspace\n",
1512*4882a593Smuzhiyun 					current->comm, cmd);
1513*4882a593Smuzhiyun 		return put_user(ttymajor, (int __user *)argp);
1514*4882a593Smuzhiyun 
1515*4882a593Smuzhiyun 	case MOXA_CHKPORTENABLE:
1516*4882a593Smuzhiyun 		result = 0;
1517*4882a593Smuzhiyun 		for (i = 0; i < MXSER_BOARDS; i++)
1518*4882a593Smuzhiyun 			for (j = 0; j < MXSER_PORTS_PER_BOARD; j++)
1519*4882a593Smuzhiyun 				if (mxser_boards[i].ports[j].ioaddr)
1520*4882a593Smuzhiyun 					result |= (1 << i);
1521*4882a593Smuzhiyun 		return put_user(result, (unsigned long __user *)argp);
1522*4882a593Smuzhiyun 	case MOXA_GETDATACOUNT:
1523*4882a593Smuzhiyun 		/* The receive side is locked by port->slock but it isn't
1524*4882a593Smuzhiyun 		   clear that an exact snapshot is worth copying here */
1525*4882a593Smuzhiyun 		if (copy_to_user(argp, &mxvar_log, sizeof(mxvar_log)))
1526*4882a593Smuzhiyun 			ret = -EFAULT;
1527*4882a593Smuzhiyun 		return ret;
1528*4882a593Smuzhiyun 	case MOXA_GETMSTATUS: {
1529*4882a593Smuzhiyun 		struct mxser_mstatus ms, __user *msu = argp;
1530*4882a593Smuzhiyun 		for (i = 0; i < MXSER_BOARDS; i++)
1531*4882a593Smuzhiyun 			for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) {
1532*4882a593Smuzhiyun 				ip = &mxser_boards[i].ports[j];
1533*4882a593Smuzhiyun 				port = &ip->port;
1534*4882a593Smuzhiyun 				memset(&ms, 0, sizeof(ms));
1535*4882a593Smuzhiyun 
1536*4882a593Smuzhiyun 				mutex_lock(&port->mutex);
1537*4882a593Smuzhiyun 				if (!ip->ioaddr)
1538*4882a593Smuzhiyun 					goto copy;
1539*4882a593Smuzhiyun 
1540*4882a593Smuzhiyun 				tty = tty_port_tty_get(port);
1541*4882a593Smuzhiyun 
1542*4882a593Smuzhiyun 				if (!tty)
1543*4882a593Smuzhiyun 					ms.cflag = ip->normal_termios.c_cflag;
1544*4882a593Smuzhiyun 				else
1545*4882a593Smuzhiyun 					ms.cflag = tty->termios.c_cflag;
1546*4882a593Smuzhiyun 				tty_kref_put(tty);
1547*4882a593Smuzhiyun 				spin_lock_irq(&ip->slock);
1548*4882a593Smuzhiyun 				status = inb(ip->ioaddr + UART_MSR);
1549*4882a593Smuzhiyun 				spin_unlock_irq(&ip->slock);
1550*4882a593Smuzhiyun 				if (status & UART_MSR_DCD)
1551*4882a593Smuzhiyun 					ms.dcd = 1;
1552*4882a593Smuzhiyun 				if (status & UART_MSR_DSR)
1553*4882a593Smuzhiyun 					ms.dsr = 1;
1554*4882a593Smuzhiyun 				if (status & UART_MSR_CTS)
1555*4882a593Smuzhiyun 					ms.cts = 1;
1556*4882a593Smuzhiyun 			copy:
1557*4882a593Smuzhiyun 				mutex_unlock(&port->mutex);
1558*4882a593Smuzhiyun 				if (copy_to_user(msu, &ms, sizeof(ms)))
1559*4882a593Smuzhiyun 					return -EFAULT;
1560*4882a593Smuzhiyun 				msu++;
1561*4882a593Smuzhiyun 			}
1562*4882a593Smuzhiyun 		return 0;
1563*4882a593Smuzhiyun 	}
1564*4882a593Smuzhiyun 	case MOXA_ASPP_MON_EXT: {
1565*4882a593Smuzhiyun 		struct mxser_mon_ext *me; /* it's 2k, stack unfriendly */
1566*4882a593Smuzhiyun 		unsigned int cflag, iflag, p;
1567*4882a593Smuzhiyun 		u8 opmode;
1568*4882a593Smuzhiyun 
1569*4882a593Smuzhiyun 		me = kzalloc(sizeof(*me), GFP_KERNEL);
1570*4882a593Smuzhiyun 		if (!me)
1571*4882a593Smuzhiyun 			return -ENOMEM;
1572*4882a593Smuzhiyun 
1573*4882a593Smuzhiyun 		for (i = 0, p = 0; i < MXSER_BOARDS; i++) {
1574*4882a593Smuzhiyun 			for (j = 0; j < MXSER_PORTS_PER_BOARD; j++, p++) {
1575*4882a593Smuzhiyun 				if (p >= ARRAY_SIZE(me->rx_cnt)) {
1576*4882a593Smuzhiyun 					i = MXSER_BOARDS;
1577*4882a593Smuzhiyun 					break;
1578*4882a593Smuzhiyun 				}
1579*4882a593Smuzhiyun 				ip = &mxser_boards[i].ports[j];
1580*4882a593Smuzhiyun 				port = &ip->port;
1581*4882a593Smuzhiyun 
1582*4882a593Smuzhiyun 				mutex_lock(&port->mutex);
1583*4882a593Smuzhiyun 				if (!ip->ioaddr) {
1584*4882a593Smuzhiyun 					mutex_unlock(&port->mutex);
1585*4882a593Smuzhiyun 					continue;
1586*4882a593Smuzhiyun 				}
1587*4882a593Smuzhiyun 
1588*4882a593Smuzhiyun 				spin_lock_irq(&ip->slock);
1589*4882a593Smuzhiyun 				status = mxser_get_msr(ip->ioaddr, 0, p);
1590*4882a593Smuzhiyun 
1591*4882a593Smuzhiyun 				if (status & UART_MSR_TERI)
1592*4882a593Smuzhiyun 					ip->icount.rng++;
1593*4882a593Smuzhiyun 				if (status & UART_MSR_DDSR)
1594*4882a593Smuzhiyun 					ip->icount.dsr++;
1595*4882a593Smuzhiyun 				if (status & UART_MSR_DDCD)
1596*4882a593Smuzhiyun 					ip->icount.dcd++;
1597*4882a593Smuzhiyun 				if (status & UART_MSR_DCTS)
1598*4882a593Smuzhiyun 					ip->icount.cts++;
1599*4882a593Smuzhiyun 
1600*4882a593Smuzhiyun 				ip->mon_data.modem_status = status;
1601*4882a593Smuzhiyun 				me->rx_cnt[p] = ip->mon_data.rxcnt;
1602*4882a593Smuzhiyun 				me->tx_cnt[p] = ip->mon_data.txcnt;
1603*4882a593Smuzhiyun 				me->up_rxcnt[p] = ip->mon_data.up_rxcnt;
1604*4882a593Smuzhiyun 				me->up_txcnt[p] = ip->mon_data.up_txcnt;
1605*4882a593Smuzhiyun 				me->modem_status[p] =
1606*4882a593Smuzhiyun 					ip->mon_data.modem_status;
1607*4882a593Smuzhiyun 				spin_unlock_irq(&ip->slock);
1608*4882a593Smuzhiyun 
1609*4882a593Smuzhiyun 				tty = tty_port_tty_get(&ip->port);
1610*4882a593Smuzhiyun 
1611*4882a593Smuzhiyun 				if (!tty) {
1612*4882a593Smuzhiyun 					cflag = ip->normal_termios.c_cflag;
1613*4882a593Smuzhiyun 					iflag = ip->normal_termios.c_iflag;
1614*4882a593Smuzhiyun 					me->baudrate[p] = tty_termios_baud_rate(&ip->normal_termios);
1615*4882a593Smuzhiyun 				} else {
1616*4882a593Smuzhiyun 					cflag = tty->termios.c_cflag;
1617*4882a593Smuzhiyun 					iflag = tty->termios.c_iflag;
1618*4882a593Smuzhiyun 					me->baudrate[p] = tty_get_baud_rate(tty);
1619*4882a593Smuzhiyun 				}
1620*4882a593Smuzhiyun 				tty_kref_put(tty);
1621*4882a593Smuzhiyun 
1622*4882a593Smuzhiyun 				me->databits[p] = cflag & CSIZE;
1623*4882a593Smuzhiyun 				me->stopbits[p] = cflag & CSTOPB;
1624*4882a593Smuzhiyun 				me->parity[p] = cflag & (PARENB | PARODD |
1625*4882a593Smuzhiyun 						CMSPAR);
1626*4882a593Smuzhiyun 
1627*4882a593Smuzhiyun 				if (cflag & CRTSCTS)
1628*4882a593Smuzhiyun 					me->flowctrl[p] |= 0x03;
1629*4882a593Smuzhiyun 
1630*4882a593Smuzhiyun 				if (iflag & (IXON | IXOFF))
1631*4882a593Smuzhiyun 					me->flowctrl[p] |= 0x0C;
1632*4882a593Smuzhiyun 
1633*4882a593Smuzhiyun 				if (ip->type == PORT_16550A)
1634*4882a593Smuzhiyun 					me->fifo[p] = 1;
1635*4882a593Smuzhiyun 
1636*4882a593Smuzhiyun 				if (ip->board->chip_flag == MOXA_MUST_MU860_HWID) {
1637*4882a593Smuzhiyun 					opmode = inb(ip->opmode_ioaddr)>>((p % 4) * 2);
1638*4882a593Smuzhiyun 					opmode &= OP_MODE_MASK;
1639*4882a593Smuzhiyun 				} else {
1640*4882a593Smuzhiyun 					opmode = RS232_MODE;
1641*4882a593Smuzhiyun 				}
1642*4882a593Smuzhiyun 				me->iftype[p] = opmode;
1643*4882a593Smuzhiyun 				mutex_unlock(&port->mutex);
1644*4882a593Smuzhiyun 			}
1645*4882a593Smuzhiyun 		}
1646*4882a593Smuzhiyun 		if (copy_to_user(argp, me, sizeof(*me)))
1647*4882a593Smuzhiyun 			ret = -EFAULT;
1648*4882a593Smuzhiyun 		kfree(me);
1649*4882a593Smuzhiyun 		return ret;
1650*4882a593Smuzhiyun 	}
1651*4882a593Smuzhiyun 	default:
1652*4882a593Smuzhiyun 		return -ENOIOCTLCMD;
1653*4882a593Smuzhiyun 	}
1654*4882a593Smuzhiyun 	return 0;
1655*4882a593Smuzhiyun }
1656*4882a593Smuzhiyun 
mxser_cflags_changed(struct mxser_port * info,unsigned long arg,struct async_icount * cprev)1657*4882a593Smuzhiyun static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg,
1658*4882a593Smuzhiyun 		struct async_icount *cprev)
1659*4882a593Smuzhiyun {
1660*4882a593Smuzhiyun 	struct async_icount cnow;
1661*4882a593Smuzhiyun 	unsigned long flags;
1662*4882a593Smuzhiyun 	int ret;
1663*4882a593Smuzhiyun 
1664*4882a593Smuzhiyun 	spin_lock_irqsave(&info->slock, flags);
1665*4882a593Smuzhiyun 	cnow = info->icount;	/* atomic copy */
1666*4882a593Smuzhiyun 	spin_unlock_irqrestore(&info->slock, flags);
1667*4882a593Smuzhiyun 
1668*4882a593Smuzhiyun 	ret =	((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) ||
1669*4882a593Smuzhiyun 		((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) ||
1670*4882a593Smuzhiyun 		((arg & TIOCM_CD)  && (cnow.dcd != cprev->dcd)) ||
1671*4882a593Smuzhiyun 		((arg & TIOCM_CTS) && (cnow.cts != cprev->cts));
1672*4882a593Smuzhiyun 
1673*4882a593Smuzhiyun 	*cprev = cnow;
1674*4882a593Smuzhiyun 
1675*4882a593Smuzhiyun 	return ret;
1676*4882a593Smuzhiyun }
1677*4882a593Smuzhiyun 
mxser_ioctl(struct tty_struct * tty,unsigned int cmd,unsigned long arg)1678*4882a593Smuzhiyun static int mxser_ioctl(struct tty_struct *tty,
1679*4882a593Smuzhiyun 		unsigned int cmd, unsigned long arg)
1680*4882a593Smuzhiyun {
1681*4882a593Smuzhiyun 	struct mxser_port *info = tty->driver_data;
1682*4882a593Smuzhiyun 	struct async_icount cnow;
1683*4882a593Smuzhiyun 	unsigned long flags;
1684*4882a593Smuzhiyun 	void __user *argp = (void __user *)arg;
1685*4882a593Smuzhiyun 
1686*4882a593Smuzhiyun 	if (tty->index == MXSER_PORTS)
1687*4882a593Smuzhiyun 		return mxser_ioctl_special(cmd, argp);
1688*4882a593Smuzhiyun 
1689*4882a593Smuzhiyun 	if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) {
1690*4882a593Smuzhiyun 		int p;
1691*4882a593Smuzhiyun 		unsigned long opmode;
1692*4882a593Smuzhiyun 		static unsigned char ModeMask[] = { 0xfc, 0xf3, 0xcf, 0x3f };
1693*4882a593Smuzhiyun 		int shiftbit;
1694*4882a593Smuzhiyun 		unsigned char val, mask;
1695*4882a593Smuzhiyun 
1696*4882a593Smuzhiyun 		if (info->board->chip_flag != MOXA_MUST_MU860_HWID)
1697*4882a593Smuzhiyun 			return -EFAULT;
1698*4882a593Smuzhiyun 
1699*4882a593Smuzhiyun 		p = tty->index % 4;
1700*4882a593Smuzhiyun 		if (cmd == MOXA_SET_OP_MODE) {
1701*4882a593Smuzhiyun 			if (get_user(opmode, (int __user *) argp))
1702*4882a593Smuzhiyun 				return -EFAULT;
1703*4882a593Smuzhiyun 			if (opmode != RS232_MODE &&
1704*4882a593Smuzhiyun 					opmode != RS485_2WIRE_MODE &&
1705*4882a593Smuzhiyun 					opmode != RS422_MODE &&
1706*4882a593Smuzhiyun 					opmode != RS485_4WIRE_MODE)
1707*4882a593Smuzhiyun 				return -EFAULT;
1708*4882a593Smuzhiyun 			mask = ModeMask[p];
1709*4882a593Smuzhiyun 			shiftbit = p * 2;
1710*4882a593Smuzhiyun 			spin_lock_irq(&info->slock);
1711*4882a593Smuzhiyun 			val = inb(info->opmode_ioaddr);
1712*4882a593Smuzhiyun 			val &= mask;
1713*4882a593Smuzhiyun 			val |= (opmode << shiftbit);
1714*4882a593Smuzhiyun 			outb(val, info->opmode_ioaddr);
1715*4882a593Smuzhiyun 			spin_unlock_irq(&info->slock);
1716*4882a593Smuzhiyun 		} else {
1717*4882a593Smuzhiyun 			shiftbit = p * 2;
1718*4882a593Smuzhiyun 			spin_lock_irq(&info->slock);
1719*4882a593Smuzhiyun 			opmode = inb(info->opmode_ioaddr) >> shiftbit;
1720*4882a593Smuzhiyun 			spin_unlock_irq(&info->slock);
1721*4882a593Smuzhiyun 			opmode &= OP_MODE_MASK;
1722*4882a593Smuzhiyun 			if (put_user(opmode, (int __user *)argp))
1723*4882a593Smuzhiyun 				return -EFAULT;
1724*4882a593Smuzhiyun 		}
1725*4882a593Smuzhiyun 		return 0;
1726*4882a593Smuzhiyun 	}
1727*4882a593Smuzhiyun 
1728*4882a593Smuzhiyun 	if (cmd != TIOCMIWAIT && tty_io_error(tty))
1729*4882a593Smuzhiyun 		return -EIO;
1730*4882a593Smuzhiyun 
1731*4882a593Smuzhiyun 	switch (cmd) {
1732*4882a593Smuzhiyun 	case TIOCSERGETLSR:	/* Get line status register */
1733*4882a593Smuzhiyun 		return  mxser_get_lsr_info(info, argp);
1734*4882a593Smuzhiyun 		/*
1735*4882a593Smuzhiyun 		 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
1736*4882a593Smuzhiyun 		 * - mask passed in arg for lines of interest
1737*4882a593Smuzhiyun 		 *   (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
1738*4882a593Smuzhiyun 		 * Caller should use TIOCGICOUNT to see which one it was
1739*4882a593Smuzhiyun 		 */
1740*4882a593Smuzhiyun 	case TIOCMIWAIT:
1741*4882a593Smuzhiyun 		spin_lock_irqsave(&info->slock, flags);
1742*4882a593Smuzhiyun 		cnow = info->icount;	/* note the counters on entry */
1743*4882a593Smuzhiyun 		spin_unlock_irqrestore(&info->slock, flags);
1744*4882a593Smuzhiyun 
1745*4882a593Smuzhiyun 		return wait_event_interruptible(info->port.delta_msr_wait,
1746*4882a593Smuzhiyun 				mxser_cflags_changed(info, arg, &cnow));
1747*4882a593Smuzhiyun 	case MOXA_HighSpeedOn:
1748*4882a593Smuzhiyun 		return put_user(info->baud_base != 115200 ? 1 : 0, (int __user *)argp);
1749*4882a593Smuzhiyun 	case MOXA_SDS_RSTICOUNTER:
1750*4882a593Smuzhiyun 		spin_lock_irq(&info->slock);
1751*4882a593Smuzhiyun 		info->mon_data.rxcnt = 0;
1752*4882a593Smuzhiyun 		info->mon_data.txcnt = 0;
1753*4882a593Smuzhiyun 		spin_unlock_irq(&info->slock);
1754*4882a593Smuzhiyun 		return 0;
1755*4882a593Smuzhiyun 
1756*4882a593Smuzhiyun 	case MOXA_ASPP_OQUEUE:{
1757*4882a593Smuzhiyun 		int len, lsr;
1758*4882a593Smuzhiyun 
1759*4882a593Smuzhiyun 		len = mxser_chars_in_buffer(tty);
1760*4882a593Smuzhiyun 		spin_lock_irq(&info->slock);
1761*4882a593Smuzhiyun 		lsr = inb(info->ioaddr + UART_LSR) & UART_LSR_THRE;
1762*4882a593Smuzhiyun 		spin_unlock_irq(&info->slock);
1763*4882a593Smuzhiyun 		len += (lsr ? 0 : 1);
1764*4882a593Smuzhiyun 
1765*4882a593Smuzhiyun 		return put_user(len, (int __user *)argp);
1766*4882a593Smuzhiyun 	}
1767*4882a593Smuzhiyun 	case MOXA_ASPP_MON: {
1768*4882a593Smuzhiyun 		int mcr, status;
1769*4882a593Smuzhiyun 
1770*4882a593Smuzhiyun 		spin_lock_irq(&info->slock);
1771*4882a593Smuzhiyun 		status = mxser_get_msr(info->ioaddr, 1, tty->index);
1772*4882a593Smuzhiyun 		mxser_check_modem_status(tty, info, status);
1773*4882a593Smuzhiyun 
1774*4882a593Smuzhiyun 		mcr = inb(info->ioaddr + UART_MCR);
1775*4882a593Smuzhiyun 		spin_unlock_irq(&info->slock);
1776*4882a593Smuzhiyun 
1777*4882a593Smuzhiyun 		if (mcr & MOXA_MUST_MCR_XON_FLAG)
1778*4882a593Smuzhiyun 			info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFHOLD;
1779*4882a593Smuzhiyun 		else
1780*4882a593Smuzhiyun 			info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFHOLD;
1781*4882a593Smuzhiyun 
1782*4882a593Smuzhiyun 		if (mcr & MOXA_MUST_MCR_TX_XON)
1783*4882a593Smuzhiyun 			info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFXENT;
1784*4882a593Smuzhiyun 		else
1785*4882a593Smuzhiyun 			info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFXENT;
1786*4882a593Smuzhiyun 
1787*4882a593Smuzhiyun 		if (tty->hw_stopped)
1788*4882a593Smuzhiyun 			info->mon_data.hold_reason |= NPPI_NOTIFY_CTSHOLD;
1789*4882a593Smuzhiyun 		else
1790*4882a593Smuzhiyun 			info->mon_data.hold_reason &= ~NPPI_NOTIFY_CTSHOLD;
1791*4882a593Smuzhiyun 
1792*4882a593Smuzhiyun 		if (copy_to_user(argp, &info->mon_data,
1793*4882a593Smuzhiyun 				sizeof(struct mxser_mon)))
1794*4882a593Smuzhiyun 			return -EFAULT;
1795*4882a593Smuzhiyun 
1796*4882a593Smuzhiyun 		return 0;
1797*4882a593Smuzhiyun 	}
1798*4882a593Smuzhiyun 	case MOXA_ASPP_LSTATUS: {
1799*4882a593Smuzhiyun 		if (put_user(info->err_shadow, (unsigned char __user *)argp))
1800*4882a593Smuzhiyun 			return -EFAULT;
1801*4882a593Smuzhiyun 
1802*4882a593Smuzhiyun 		info->err_shadow = 0;
1803*4882a593Smuzhiyun 		return 0;
1804*4882a593Smuzhiyun 	}
1805*4882a593Smuzhiyun 	case MOXA_SET_BAUD_METHOD: {
1806*4882a593Smuzhiyun 		int method;
1807*4882a593Smuzhiyun 
1808*4882a593Smuzhiyun 		if (get_user(method, (int __user *)argp))
1809*4882a593Smuzhiyun 			return -EFAULT;
1810*4882a593Smuzhiyun 		mxser_set_baud_method[tty->index] = method;
1811*4882a593Smuzhiyun 		return put_user(method, (int __user *)argp);
1812*4882a593Smuzhiyun 	}
1813*4882a593Smuzhiyun 	default:
1814*4882a593Smuzhiyun 		return -ENOIOCTLCMD;
1815*4882a593Smuzhiyun 	}
1816*4882a593Smuzhiyun 	return 0;
1817*4882a593Smuzhiyun }
1818*4882a593Smuzhiyun 
1819*4882a593Smuzhiyun 	/*
1820*4882a593Smuzhiyun 	 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1821*4882a593Smuzhiyun 	 * Return: write counters to the user passed counter struct
1822*4882a593Smuzhiyun 	 * NB: both 1->0 and 0->1 transitions are counted except for
1823*4882a593Smuzhiyun 	 *     RI where only 0->1 is counted.
1824*4882a593Smuzhiyun 	 */
1825*4882a593Smuzhiyun 
mxser_get_icount(struct tty_struct * tty,struct serial_icounter_struct * icount)1826*4882a593Smuzhiyun static int mxser_get_icount(struct tty_struct *tty,
1827*4882a593Smuzhiyun 		struct serial_icounter_struct *icount)
1828*4882a593Smuzhiyun 
1829*4882a593Smuzhiyun {
1830*4882a593Smuzhiyun 	struct mxser_port *info = tty->driver_data;
1831*4882a593Smuzhiyun 	struct async_icount cnow;
1832*4882a593Smuzhiyun 	unsigned long flags;
1833*4882a593Smuzhiyun 
1834*4882a593Smuzhiyun 	spin_lock_irqsave(&info->slock, flags);
1835*4882a593Smuzhiyun 	cnow = info->icount;
1836*4882a593Smuzhiyun 	spin_unlock_irqrestore(&info->slock, flags);
1837*4882a593Smuzhiyun 
1838*4882a593Smuzhiyun 	icount->frame = cnow.frame;
1839*4882a593Smuzhiyun 	icount->brk = cnow.brk;
1840*4882a593Smuzhiyun 	icount->overrun = cnow.overrun;
1841*4882a593Smuzhiyun 	icount->buf_overrun = cnow.buf_overrun;
1842*4882a593Smuzhiyun 	icount->parity = cnow.parity;
1843*4882a593Smuzhiyun 	icount->rx = cnow.rx;
1844*4882a593Smuzhiyun 	icount->tx = cnow.tx;
1845*4882a593Smuzhiyun 	icount->cts = cnow.cts;
1846*4882a593Smuzhiyun 	icount->dsr = cnow.dsr;
1847*4882a593Smuzhiyun 	icount->rng = cnow.rng;
1848*4882a593Smuzhiyun 	icount->dcd = cnow.dcd;
1849*4882a593Smuzhiyun 	return 0;
1850*4882a593Smuzhiyun }
1851*4882a593Smuzhiyun 
mxser_stoprx(struct tty_struct * tty)1852*4882a593Smuzhiyun static void mxser_stoprx(struct tty_struct *tty)
1853*4882a593Smuzhiyun {
1854*4882a593Smuzhiyun 	struct mxser_port *info = tty->driver_data;
1855*4882a593Smuzhiyun 
1856*4882a593Smuzhiyun 	info->ldisc_stop_rx = 1;
1857*4882a593Smuzhiyun 	if (I_IXOFF(tty)) {
1858*4882a593Smuzhiyun 		if (info->board->chip_flag) {
1859*4882a593Smuzhiyun 			info->IER &= ~MOXA_MUST_RECV_ISR;
1860*4882a593Smuzhiyun 			outb(info->IER, info->ioaddr + UART_IER);
1861*4882a593Smuzhiyun 		} else {
1862*4882a593Smuzhiyun 			info->x_char = STOP_CHAR(tty);
1863*4882a593Smuzhiyun 			outb(0, info->ioaddr + UART_IER);
1864*4882a593Smuzhiyun 			info->IER |= UART_IER_THRI;
1865*4882a593Smuzhiyun 			outb(info->IER, info->ioaddr + UART_IER);
1866*4882a593Smuzhiyun 		}
1867*4882a593Smuzhiyun 	}
1868*4882a593Smuzhiyun 
1869*4882a593Smuzhiyun 	if (C_CRTSCTS(tty)) {
1870*4882a593Smuzhiyun 		info->MCR &= ~UART_MCR_RTS;
1871*4882a593Smuzhiyun 		outb(info->MCR, info->ioaddr + UART_MCR);
1872*4882a593Smuzhiyun 	}
1873*4882a593Smuzhiyun }
1874*4882a593Smuzhiyun 
1875*4882a593Smuzhiyun /*
1876*4882a593Smuzhiyun  * This routine is called by the upper-layer tty layer to signal that
1877*4882a593Smuzhiyun  * incoming characters should be throttled.
1878*4882a593Smuzhiyun  */
mxser_throttle(struct tty_struct * tty)1879*4882a593Smuzhiyun static void mxser_throttle(struct tty_struct *tty)
1880*4882a593Smuzhiyun {
1881*4882a593Smuzhiyun 	mxser_stoprx(tty);
1882*4882a593Smuzhiyun }
1883*4882a593Smuzhiyun 
mxser_unthrottle(struct tty_struct * tty)1884*4882a593Smuzhiyun static void mxser_unthrottle(struct tty_struct *tty)
1885*4882a593Smuzhiyun {
1886*4882a593Smuzhiyun 	struct mxser_port *info = tty->driver_data;
1887*4882a593Smuzhiyun 
1888*4882a593Smuzhiyun 	/* startrx */
1889*4882a593Smuzhiyun 	info->ldisc_stop_rx = 0;
1890*4882a593Smuzhiyun 	if (I_IXOFF(tty)) {
1891*4882a593Smuzhiyun 		if (info->x_char)
1892*4882a593Smuzhiyun 			info->x_char = 0;
1893*4882a593Smuzhiyun 		else {
1894*4882a593Smuzhiyun 			if (info->board->chip_flag) {
1895*4882a593Smuzhiyun 				info->IER |= MOXA_MUST_RECV_ISR;
1896*4882a593Smuzhiyun 				outb(info->IER, info->ioaddr + UART_IER);
1897*4882a593Smuzhiyun 			} else {
1898*4882a593Smuzhiyun 				info->x_char = START_CHAR(tty);
1899*4882a593Smuzhiyun 				outb(0, info->ioaddr + UART_IER);
1900*4882a593Smuzhiyun 				info->IER |= UART_IER_THRI;
1901*4882a593Smuzhiyun 				outb(info->IER, info->ioaddr + UART_IER);
1902*4882a593Smuzhiyun 			}
1903*4882a593Smuzhiyun 		}
1904*4882a593Smuzhiyun 	}
1905*4882a593Smuzhiyun 
1906*4882a593Smuzhiyun 	if (C_CRTSCTS(tty)) {
1907*4882a593Smuzhiyun 		info->MCR |= UART_MCR_RTS;
1908*4882a593Smuzhiyun 		outb(info->MCR, info->ioaddr + UART_MCR);
1909*4882a593Smuzhiyun 	}
1910*4882a593Smuzhiyun }
1911*4882a593Smuzhiyun 
1912*4882a593Smuzhiyun /*
1913*4882a593Smuzhiyun  * mxser_stop() and mxser_start()
1914*4882a593Smuzhiyun  *
1915*4882a593Smuzhiyun  * This routines are called before setting or resetting tty->stopped.
1916*4882a593Smuzhiyun  * They enable or disable transmitter interrupts, as necessary.
1917*4882a593Smuzhiyun  */
mxser_stop(struct tty_struct * tty)1918*4882a593Smuzhiyun static void mxser_stop(struct tty_struct *tty)
1919*4882a593Smuzhiyun {
1920*4882a593Smuzhiyun 	struct mxser_port *info = tty->driver_data;
1921*4882a593Smuzhiyun 	unsigned long flags;
1922*4882a593Smuzhiyun 
1923*4882a593Smuzhiyun 	spin_lock_irqsave(&info->slock, flags);
1924*4882a593Smuzhiyun 	if (info->IER & UART_IER_THRI) {
1925*4882a593Smuzhiyun 		info->IER &= ~UART_IER_THRI;
1926*4882a593Smuzhiyun 		outb(info->IER, info->ioaddr + UART_IER);
1927*4882a593Smuzhiyun 	}
1928*4882a593Smuzhiyun 	spin_unlock_irqrestore(&info->slock, flags);
1929*4882a593Smuzhiyun }
1930*4882a593Smuzhiyun 
mxser_start(struct tty_struct * tty)1931*4882a593Smuzhiyun static void mxser_start(struct tty_struct *tty)
1932*4882a593Smuzhiyun {
1933*4882a593Smuzhiyun 	struct mxser_port *info = tty->driver_data;
1934*4882a593Smuzhiyun 	unsigned long flags;
1935*4882a593Smuzhiyun 
1936*4882a593Smuzhiyun 	spin_lock_irqsave(&info->slock, flags);
1937*4882a593Smuzhiyun 	if (info->xmit_cnt && info->port.xmit_buf) {
1938*4882a593Smuzhiyun 		outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1939*4882a593Smuzhiyun 		info->IER |= UART_IER_THRI;
1940*4882a593Smuzhiyun 		outb(info->IER, info->ioaddr + UART_IER);
1941*4882a593Smuzhiyun 	}
1942*4882a593Smuzhiyun 	spin_unlock_irqrestore(&info->slock, flags);
1943*4882a593Smuzhiyun }
1944*4882a593Smuzhiyun 
mxser_set_termios(struct tty_struct * tty,struct ktermios * old_termios)1945*4882a593Smuzhiyun static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1946*4882a593Smuzhiyun {
1947*4882a593Smuzhiyun 	struct mxser_port *info = tty->driver_data;
1948*4882a593Smuzhiyun 	unsigned long flags;
1949*4882a593Smuzhiyun 
1950*4882a593Smuzhiyun 	spin_lock_irqsave(&info->slock, flags);
1951*4882a593Smuzhiyun 	mxser_change_speed(tty);
1952*4882a593Smuzhiyun 	spin_unlock_irqrestore(&info->slock, flags);
1953*4882a593Smuzhiyun 
1954*4882a593Smuzhiyun 	if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
1955*4882a593Smuzhiyun 		tty->hw_stopped = 0;
1956*4882a593Smuzhiyun 		mxser_start(tty);
1957*4882a593Smuzhiyun 	}
1958*4882a593Smuzhiyun 
1959*4882a593Smuzhiyun 	/* Handle sw stopped */
1960*4882a593Smuzhiyun 	if ((old_termios->c_iflag & IXON) && !I_IXON(tty)) {
1961*4882a593Smuzhiyun 		tty->stopped = 0;
1962*4882a593Smuzhiyun 
1963*4882a593Smuzhiyun 		if (info->board->chip_flag) {
1964*4882a593Smuzhiyun 			spin_lock_irqsave(&info->slock, flags);
1965*4882a593Smuzhiyun 			mxser_disable_must_rx_software_flow_control(
1966*4882a593Smuzhiyun 					info->ioaddr);
1967*4882a593Smuzhiyun 			spin_unlock_irqrestore(&info->slock, flags);
1968*4882a593Smuzhiyun 		}
1969*4882a593Smuzhiyun 
1970*4882a593Smuzhiyun 		mxser_start(tty);
1971*4882a593Smuzhiyun 	}
1972*4882a593Smuzhiyun }
1973*4882a593Smuzhiyun 
1974*4882a593Smuzhiyun /*
1975*4882a593Smuzhiyun  * mxser_wait_until_sent() --- wait until the transmitter is empty
1976*4882a593Smuzhiyun  */
mxser_wait_until_sent(struct tty_struct * tty,int timeout)1977*4882a593Smuzhiyun static void mxser_wait_until_sent(struct tty_struct *tty, int timeout)
1978*4882a593Smuzhiyun {
1979*4882a593Smuzhiyun 	struct mxser_port *info = tty->driver_data;
1980*4882a593Smuzhiyun 	unsigned long orig_jiffies, char_time;
1981*4882a593Smuzhiyun 	unsigned long flags;
1982*4882a593Smuzhiyun 	int lsr;
1983*4882a593Smuzhiyun 
1984*4882a593Smuzhiyun 	if (info->type == PORT_UNKNOWN)
1985*4882a593Smuzhiyun 		return;
1986*4882a593Smuzhiyun 
1987*4882a593Smuzhiyun 	if (info->xmit_fifo_size == 0)
1988*4882a593Smuzhiyun 		return;		/* Just in case.... */
1989*4882a593Smuzhiyun 
1990*4882a593Smuzhiyun 	orig_jiffies = jiffies;
1991*4882a593Smuzhiyun 	/*
1992*4882a593Smuzhiyun 	 * Set the check interval to be 1/5 of the estimated time to
1993*4882a593Smuzhiyun 	 * send a single character, and make it at least 1.  The check
1994*4882a593Smuzhiyun 	 * interval should also be less than the timeout.
1995*4882a593Smuzhiyun 	 *
1996*4882a593Smuzhiyun 	 * Note: we have to use pretty tight timings here to satisfy
1997*4882a593Smuzhiyun 	 * the NIST-PCTS.
1998*4882a593Smuzhiyun 	 */
1999*4882a593Smuzhiyun 	char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size;
2000*4882a593Smuzhiyun 	char_time = char_time / 5;
2001*4882a593Smuzhiyun 	if (char_time == 0)
2002*4882a593Smuzhiyun 		char_time = 1;
2003*4882a593Smuzhiyun 	if (timeout && timeout < char_time)
2004*4882a593Smuzhiyun 		char_time = timeout;
2005*4882a593Smuzhiyun 	/*
2006*4882a593Smuzhiyun 	 * If the transmitter hasn't cleared in twice the approximate
2007*4882a593Smuzhiyun 	 * amount of time to send the entire FIFO, it probably won't
2008*4882a593Smuzhiyun 	 * ever clear.  This assumes the UART isn't doing flow
2009*4882a593Smuzhiyun 	 * control, which is currently the case.  Hence, if it ever
2010*4882a593Smuzhiyun 	 * takes longer than info->timeout, this is probably due to a
2011*4882a593Smuzhiyun 	 * UART bug of some kind.  So, we clamp the timeout parameter at
2012*4882a593Smuzhiyun 	 * 2*info->timeout.
2013*4882a593Smuzhiyun 	 */
2014*4882a593Smuzhiyun 	if (!timeout || timeout > 2 * info->timeout)
2015*4882a593Smuzhiyun 		timeout = 2 * info->timeout;
2016*4882a593Smuzhiyun 
2017*4882a593Smuzhiyun 	spin_lock_irqsave(&info->slock, flags);
2018*4882a593Smuzhiyun 	while (!((lsr = inb(info->ioaddr + UART_LSR)) & UART_LSR_TEMT)) {
2019*4882a593Smuzhiyun 		spin_unlock_irqrestore(&info->slock, flags);
2020*4882a593Smuzhiyun 		schedule_timeout_interruptible(char_time);
2021*4882a593Smuzhiyun 		spin_lock_irqsave(&info->slock, flags);
2022*4882a593Smuzhiyun 		if (signal_pending(current))
2023*4882a593Smuzhiyun 			break;
2024*4882a593Smuzhiyun 		if (timeout && time_after(jiffies, orig_jiffies + timeout))
2025*4882a593Smuzhiyun 			break;
2026*4882a593Smuzhiyun 	}
2027*4882a593Smuzhiyun 	spin_unlock_irqrestore(&info->slock, flags);
2028*4882a593Smuzhiyun 	set_current_state(TASK_RUNNING);
2029*4882a593Smuzhiyun }
2030*4882a593Smuzhiyun 
2031*4882a593Smuzhiyun /*
2032*4882a593Smuzhiyun  * This routine is called by tty_hangup() when a hangup is signaled.
2033*4882a593Smuzhiyun  */
mxser_hangup(struct tty_struct * tty)2034*4882a593Smuzhiyun static void mxser_hangup(struct tty_struct *tty)
2035*4882a593Smuzhiyun {
2036*4882a593Smuzhiyun 	struct mxser_port *info = tty->driver_data;
2037*4882a593Smuzhiyun 
2038*4882a593Smuzhiyun 	mxser_flush_buffer(tty);
2039*4882a593Smuzhiyun 	tty_port_hangup(&info->port);
2040*4882a593Smuzhiyun }
2041*4882a593Smuzhiyun 
2042*4882a593Smuzhiyun /*
2043*4882a593Smuzhiyun  * mxser_rs_break() --- routine which turns the break handling on or off
2044*4882a593Smuzhiyun  */
mxser_rs_break(struct tty_struct * tty,int break_state)2045*4882a593Smuzhiyun static int mxser_rs_break(struct tty_struct *tty, int break_state)
2046*4882a593Smuzhiyun {
2047*4882a593Smuzhiyun 	struct mxser_port *info = tty->driver_data;
2048*4882a593Smuzhiyun 	unsigned long flags;
2049*4882a593Smuzhiyun 
2050*4882a593Smuzhiyun 	spin_lock_irqsave(&info->slock, flags);
2051*4882a593Smuzhiyun 	if (break_state == -1)
2052*4882a593Smuzhiyun 		outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC,
2053*4882a593Smuzhiyun 			info->ioaddr + UART_LCR);
2054*4882a593Smuzhiyun 	else
2055*4882a593Smuzhiyun 		outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC,
2056*4882a593Smuzhiyun 			info->ioaddr + UART_LCR);
2057*4882a593Smuzhiyun 	spin_unlock_irqrestore(&info->slock, flags);
2058*4882a593Smuzhiyun 	return 0;
2059*4882a593Smuzhiyun }
2060*4882a593Smuzhiyun 
mxser_receive_chars(struct tty_struct * tty,struct mxser_port * port,int * status)2061*4882a593Smuzhiyun static void mxser_receive_chars(struct tty_struct *tty,
2062*4882a593Smuzhiyun 				struct mxser_port *port, int *status)
2063*4882a593Smuzhiyun {
2064*4882a593Smuzhiyun 	unsigned char ch, gdl;
2065*4882a593Smuzhiyun 	int ignored = 0;
2066*4882a593Smuzhiyun 	int cnt = 0;
2067*4882a593Smuzhiyun 	int recv_room;
2068*4882a593Smuzhiyun 	int max = 256;
2069*4882a593Smuzhiyun 
2070*4882a593Smuzhiyun 	recv_room = tty->receive_room;
2071*4882a593Smuzhiyun 	if (recv_room == 0 && !port->ldisc_stop_rx)
2072*4882a593Smuzhiyun 		mxser_stoprx(tty);
2073*4882a593Smuzhiyun 	if (port->board->chip_flag != MOXA_OTHER_UART) {
2074*4882a593Smuzhiyun 
2075*4882a593Smuzhiyun 		if (*status & UART_LSR_SPECIAL)
2076*4882a593Smuzhiyun 			goto intr_old;
2077*4882a593Smuzhiyun 		if (port->board->chip_flag == MOXA_MUST_MU860_HWID &&
2078*4882a593Smuzhiyun 				(*status & MOXA_MUST_LSR_RERR))
2079*4882a593Smuzhiyun 			goto intr_old;
2080*4882a593Smuzhiyun 		if (*status & MOXA_MUST_LSR_RERR)
2081*4882a593Smuzhiyun 			goto intr_old;
2082*4882a593Smuzhiyun 
2083*4882a593Smuzhiyun 		gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER);
2084*4882a593Smuzhiyun 
2085*4882a593Smuzhiyun 		if (port->board->chip_flag == MOXA_MUST_MU150_HWID)
2086*4882a593Smuzhiyun 			gdl &= MOXA_MUST_GDL_MASK;
2087*4882a593Smuzhiyun 		if (gdl >= recv_room) {
2088*4882a593Smuzhiyun 			if (!port->ldisc_stop_rx)
2089*4882a593Smuzhiyun 				mxser_stoprx(tty);
2090*4882a593Smuzhiyun 		}
2091*4882a593Smuzhiyun 		while (gdl--) {
2092*4882a593Smuzhiyun 			ch = inb(port->ioaddr + UART_RX);
2093*4882a593Smuzhiyun 			tty_insert_flip_char(&port->port, ch, 0);
2094*4882a593Smuzhiyun 			cnt++;
2095*4882a593Smuzhiyun 		}
2096*4882a593Smuzhiyun 		goto end_intr;
2097*4882a593Smuzhiyun 	}
2098*4882a593Smuzhiyun intr_old:
2099*4882a593Smuzhiyun 
2100*4882a593Smuzhiyun 	do {
2101*4882a593Smuzhiyun 		if (max-- < 0)
2102*4882a593Smuzhiyun 			break;
2103*4882a593Smuzhiyun 
2104*4882a593Smuzhiyun 		ch = inb(port->ioaddr + UART_RX);
2105*4882a593Smuzhiyun 		if (port->board->chip_flag && (*status & UART_LSR_OE))
2106*4882a593Smuzhiyun 			outb(0x23, port->ioaddr + UART_FCR);
2107*4882a593Smuzhiyun 		*status &= port->read_status_mask;
2108*4882a593Smuzhiyun 		if (*status & port->ignore_status_mask) {
2109*4882a593Smuzhiyun 			if (++ignored > 100)
2110*4882a593Smuzhiyun 				break;
2111*4882a593Smuzhiyun 		} else {
2112*4882a593Smuzhiyun 			char flag = 0;
2113*4882a593Smuzhiyun 			if (*status & UART_LSR_SPECIAL) {
2114*4882a593Smuzhiyun 				if (*status & UART_LSR_BI) {
2115*4882a593Smuzhiyun 					flag = TTY_BREAK;
2116*4882a593Smuzhiyun 					port->icount.brk++;
2117*4882a593Smuzhiyun 
2118*4882a593Smuzhiyun 					if (port->port.flags & ASYNC_SAK)
2119*4882a593Smuzhiyun 						do_SAK(tty);
2120*4882a593Smuzhiyun 				} else if (*status & UART_LSR_PE) {
2121*4882a593Smuzhiyun 					flag = TTY_PARITY;
2122*4882a593Smuzhiyun 					port->icount.parity++;
2123*4882a593Smuzhiyun 				} else if (*status & UART_LSR_FE) {
2124*4882a593Smuzhiyun 					flag = TTY_FRAME;
2125*4882a593Smuzhiyun 					port->icount.frame++;
2126*4882a593Smuzhiyun 				} else if (*status & UART_LSR_OE) {
2127*4882a593Smuzhiyun 					flag = TTY_OVERRUN;
2128*4882a593Smuzhiyun 					port->icount.overrun++;
2129*4882a593Smuzhiyun 				} else
2130*4882a593Smuzhiyun 					flag = TTY_BREAK;
2131*4882a593Smuzhiyun 			}
2132*4882a593Smuzhiyun 			tty_insert_flip_char(&port->port, ch, flag);
2133*4882a593Smuzhiyun 			cnt++;
2134*4882a593Smuzhiyun 			if (cnt >= recv_room) {
2135*4882a593Smuzhiyun 				if (!port->ldisc_stop_rx)
2136*4882a593Smuzhiyun 					mxser_stoprx(tty);
2137*4882a593Smuzhiyun 				break;
2138*4882a593Smuzhiyun 			}
2139*4882a593Smuzhiyun 
2140*4882a593Smuzhiyun 		}
2141*4882a593Smuzhiyun 
2142*4882a593Smuzhiyun 		if (port->board->chip_flag)
2143*4882a593Smuzhiyun 			break;
2144*4882a593Smuzhiyun 
2145*4882a593Smuzhiyun 		*status = inb(port->ioaddr + UART_LSR);
2146*4882a593Smuzhiyun 	} while (*status & UART_LSR_DR);
2147*4882a593Smuzhiyun 
2148*4882a593Smuzhiyun end_intr:
2149*4882a593Smuzhiyun 	mxvar_log.rxcnt[tty->index] += cnt;
2150*4882a593Smuzhiyun 	port->mon_data.rxcnt += cnt;
2151*4882a593Smuzhiyun 	port->mon_data.up_rxcnt += cnt;
2152*4882a593Smuzhiyun 
2153*4882a593Smuzhiyun 	/*
2154*4882a593Smuzhiyun 	 * We are called from an interrupt context with &port->slock
2155*4882a593Smuzhiyun 	 * being held. Drop it temporarily in order to prevent
2156*4882a593Smuzhiyun 	 * recursive locking.
2157*4882a593Smuzhiyun 	 */
2158*4882a593Smuzhiyun 	spin_unlock(&port->slock);
2159*4882a593Smuzhiyun 	tty_flip_buffer_push(&port->port);
2160*4882a593Smuzhiyun 	spin_lock(&port->slock);
2161*4882a593Smuzhiyun }
2162*4882a593Smuzhiyun 
mxser_transmit_chars(struct tty_struct * tty,struct mxser_port * port)2163*4882a593Smuzhiyun static void mxser_transmit_chars(struct tty_struct *tty, struct mxser_port *port)
2164*4882a593Smuzhiyun {
2165*4882a593Smuzhiyun 	int count, cnt;
2166*4882a593Smuzhiyun 
2167*4882a593Smuzhiyun 	if (port->x_char) {
2168*4882a593Smuzhiyun 		outb(port->x_char, port->ioaddr + UART_TX);
2169*4882a593Smuzhiyun 		port->x_char = 0;
2170*4882a593Smuzhiyun 		mxvar_log.txcnt[tty->index]++;
2171*4882a593Smuzhiyun 		port->mon_data.txcnt++;
2172*4882a593Smuzhiyun 		port->mon_data.up_txcnt++;
2173*4882a593Smuzhiyun 		port->icount.tx++;
2174*4882a593Smuzhiyun 		return;
2175*4882a593Smuzhiyun 	}
2176*4882a593Smuzhiyun 
2177*4882a593Smuzhiyun 	if (port->port.xmit_buf == NULL)
2178*4882a593Smuzhiyun 		return;
2179*4882a593Smuzhiyun 
2180*4882a593Smuzhiyun 	if (port->xmit_cnt <= 0 || tty->stopped ||
2181*4882a593Smuzhiyun 			(tty->hw_stopped &&
2182*4882a593Smuzhiyun 			(port->type != PORT_16550A) &&
2183*4882a593Smuzhiyun 			(!port->board->chip_flag))) {
2184*4882a593Smuzhiyun 		port->IER &= ~UART_IER_THRI;
2185*4882a593Smuzhiyun 		outb(port->IER, port->ioaddr + UART_IER);
2186*4882a593Smuzhiyun 		return;
2187*4882a593Smuzhiyun 	}
2188*4882a593Smuzhiyun 
2189*4882a593Smuzhiyun 	cnt = port->xmit_cnt;
2190*4882a593Smuzhiyun 	count = port->xmit_fifo_size;
2191*4882a593Smuzhiyun 	do {
2192*4882a593Smuzhiyun 		outb(port->port.xmit_buf[port->xmit_tail++],
2193*4882a593Smuzhiyun 			port->ioaddr + UART_TX);
2194*4882a593Smuzhiyun 		port->xmit_tail = port->xmit_tail & (SERIAL_XMIT_SIZE - 1);
2195*4882a593Smuzhiyun 		if (--port->xmit_cnt <= 0)
2196*4882a593Smuzhiyun 			break;
2197*4882a593Smuzhiyun 	} while (--count > 0);
2198*4882a593Smuzhiyun 	mxvar_log.txcnt[tty->index] += (cnt - port->xmit_cnt);
2199*4882a593Smuzhiyun 
2200*4882a593Smuzhiyun 	port->mon_data.txcnt += (cnt - port->xmit_cnt);
2201*4882a593Smuzhiyun 	port->mon_data.up_txcnt += (cnt - port->xmit_cnt);
2202*4882a593Smuzhiyun 	port->icount.tx += (cnt - port->xmit_cnt);
2203*4882a593Smuzhiyun 
2204*4882a593Smuzhiyun 	if (port->xmit_cnt < WAKEUP_CHARS)
2205*4882a593Smuzhiyun 		tty_wakeup(tty);
2206*4882a593Smuzhiyun 
2207*4882a593Smuzhiyun 	if (port->xmit_cnt <= 0) {
2208*4882a593Smuzhiyun 		port->IER &= ~UART_IER_THRI;
2209*4882a593Smuzhiyun 		outb(port->IER, port->ioaddr + UART_IER);
2210*4882a593Smuzhiyun 	}
2211*4882a593Smuzhiyun }
2212*4882a593Smuzhiyun 
2213*4882a593Smuzhiyun /*
2214*4882a593Smuzhiyun  * This is the serial driver's generic interrupt routine
2215*4882a593Smuzhiyun  */
mxser_interrupt(int irq,void * dev_id)2216*4882a593Smuzhiyun static irqreturn_t mxser_interrupt(int irq, void *dev_id)
2217*4882a593Smuzhiyun {
2218*4882a593Smuzhiyun 	int status, iir, i;
2219*4882a593Smuzhiyun 	struct mxser_board *brd = NULL;
2220*4882a593Smuzhiyun 	struct mxser_port *port;
2221*4882a593Smuzhiyun 	int max, irqbits, bits, msr;
2222*4882a593Smuzhiyun 	unsigned int int_cnt, pass_counter = 0;
2223*4882a593Smuzhiyun 	int handled = IRQ_NONE;
2224*4882a593Smuzhiyun 	struct tty_struct *tty;
2225*4882a593Smuzhiyun 
2226*4882a593Smuzhiyun 	for (i = 0; i < MXSER_BOARDS; i++)
2227*4882a593Smuzhiyun 		if (dev_id == &mxser_boards[i]) {
2228*4882a593Smuzhiyun 			brd = dev_id;
2229*4882a593Smuzhiyun 			break;
2230*4882a593Smuzhiyun 		}
2231*4882a593Smuzhiyun 
2232*4882a593Smuzhiyun 	if (i == MXSER_BOARDS)
2233*4882a593Smuzhiyun 		goto irq_stop;
2234*4882a593Smuzhiyun 	if (brd == NULL)
2235*4882a593Smuzhiyun 		goto irq_stop;
2236*4882a593Smuzhiyun 	max = brd->info->nports;
2237*4882a593Smuzhiyun 	while (pass_counter++ < MXSER_ISR_PASS_LIMIT) {
2238*4882a593Smuzhiyun 		irqbits = inb(brd->vector) & brd->vector_mask;
2239*4882a593Smuzhiyun 		if (irqbits == brd->vector_mask)
2240*4882a593Smuzhiyun 			break;
2241*4882a593Smuzhiyun 
2242*4882a593Smuzhiyun 		handled = IRQ_HANDLED;
2243*4882a593Smuzhiyun 		for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) {
2244*4882a593Smuzhiyun 			if (irqbits == brd->vector_mask)
2245*4882a593Smuzhiyun 				break;
2246*4882a593Smuzhiyun 			if (bits & irqbits)
2247*4882a593Smuzhiyun 				continue;
2248*4882a593Smuzhiyun 			port = &brd->ports[i];
2249*4882a593Smuzhiyun 
2250*4882a593Smuzhiyun 			int_cnt = 0;
2251*4882a593Smuzhiyun 			spin_lock(&port->slock);
2252*4882a593Smuzhiyun 			do {
2253*4882a593Smuzhiyun 				iir = inb(port->ioaddr + UART_IIR);
2254*4882a593Smuzhiyun 				if (iir & UART_IIR_NO_INT)
2255*4882a593Smuzhiyun 					break;
2256*4882a593Smuzhiyun 				iir &= MOXA_MUST_IIR_MASK;
2257*4882a593Smuzhiyun 				tty = tty_port_tty_get(&port->port);
2258*4882a593Smuzhiyun 				if (!tty || port->closing ||
2259*4882a593Smuzhiyun 				    !tty_port_initialized(&port->port)) {
2260*4882a593Smuzhiyun 					status = inb(port->ioaddr + UART_LSR);
2261*4882a593Smuzhiyun 					outb(0x27, port->ioaddr + UART_FCR);
2262*4882a593Smuzhiyun 					inb(port->ioaddr + UART_MSR);
2263*4882a593Smuzhiyun 					tty_kref_put(tty);
2264*4882a593Smuzhiyun 					break;
2265*4882a593Smuzhiyun 				}
2266*4882a593Smuzhiyun 
2267*4882a593Smuzhiyun 				status = inb(port->ioaddr + UART_LSR);
2268*4882a593Smuzhiyun 
2269*4882a593Smuzhiyun 				if (status & UART_LSR_PE)
2270*4882a593Smuzhiyun 					port->err_shadow |= NPPI_NOTIFY_PARITY;
2271*4882a593Smuzhiyun 				if (status & UART_LSR_FE)
2272*4882a593Smuzhiyun 					port->err_shadow |= NPPI_NOTIFY_FRAMING;
2273*4882a593Smuzhiyun 				if (status & UART_LSR_OE)
2274*4882a593Smuzhiyun 					port->err_shadow |=
2275*4882a593Smuzhiyun 						NPPI_NOTIFY_HW_OVERRUN;
2276*4882a593Smuzhiyun 				if (status & UART_LSR_BI)
2277*4882a593Smuzhiyun 					port->err_shadow |= NPPI_NOTIFY_BREAK;
2278*4882a593Smuzhiyun 
2279*4882a593Smuzhiyun 				if (port->board->chip_flag) {
2280*4882a593Smuzhiyun 					if (iir == MOXA_MUST_IIR_GDA ||
2281*4882a593Smuzhiyun 					    iir == MOXA_MUST_IIR_RDA ||
2282*4882a593Smuzhiyun 					    iir == MOXA_MUST_IIR_RTO ||
2283*4882a593Smuzhiyun 					    iir == MOXA_MUST_IIR_LSR)
2284*4882a593Smuzhiyun 						mxser_receive_chars(tty, port,
2285*4882a593Smuzhiyun 								&status);
2286*4882a593Smuzhiyun 
2287*4882a593Smuzhiyun 				} else {
2288*4882a593Smuzhiyun 					status &= port->read_status_mask;
2289*4882a593Smuzhiyun 					if (status & UART_LSR_DR)
2290*4882a593Smuzhiyun 						mxser_receive_chars(tty, port,
2291*4882a593Smuzhiyun 								&status);
2292*4882a593Smuzhiyun 				}
2293*4882a593Smuzhiyun 				msr = inb(port->ioaddr + UART_MSR);
2294*4882a593Smuzhiyun 				if (msr & UART_MSR_ANY_DELTA)
2295*4882a593Smuzhiyun 					mxser_check_modem_status(tty, port, msr);
2296*4882a593Smuzhiyun 
2297*4882a593Smuzhiyun 				if (port->board->chip_flag) {
2298*4882a593Smuzhiyun 					if (iir == 0x02 && (status &
2299*4882a593Smuzhiyun 								UART_LSR_THRE))
2300*4882a593Smuzhiyun 						mxser_transmit_chars(tty, port);
2301*4882a593Smuzhiyun 				} else {
2302*4882a593Smuzhiyun 					if (status & UART_LSR_THRE)
2303*4882a593Smuzhiyun 						mxser_transmit_chars(tty, port);
2304*4882a593Smuzhiyun 				}
2305*4882a593Smuzhiyun 				tty_kref_put(tty);
2306*4882a593Smuzhiyun 			} while (int_cnt++ < MXSER_ISR_PASS_LIMIT);
2307*4882a593Smuzhiyun 			spin_unlock(&port->slock);
2308*4882a593Smuzhiyun 		}
2309*4882a593Smuzhiyun 	}
2310*4882a593Smuzhiyun 
2311*4882a593Smuzhiyun irq_stop:
2312*4882a593Smuzhiyun 	return handled;
2313*4882a593Smuzhiyun }
2314*4882a593Smuzhiyun 
2315*4882a593Smuzhiyun static const struct tty_operations mxser_ops = {
2316*4882a593Smuzhiyun 	.open = mxser_open,
2317*4882a593Smuzhiyun 	.close = mxser_close,
2318*4882a593Smuzhiyun 	.write = mxser_write,
2319*4882a593Smuzhiyun 	.put_char = mxser_put_char,
2320*4882a593Smuzhiyun 	.flush_chars = mxser_flush_chars,
2321*4882a593Smuzhiyun 	.write_room = mxser_write_room,
2322*4882a593Smuzhiyun 	.chars_in_buffer = mxser_chars_in_buffer,
2323*4882a593Smuzhiyun 	.flush_buffer = mxser_flush_buffer,
2324*4882a593Smuzhiyun 	.ioctl = mxser_ioctl,
2325*4882a593Smuzhiyun 	.throttle = mxser_throttle,
2326*4882a593Smuzhiyun 	.unthrottle = mxser_unthrottle,
2327*4882a593Smuzhiyun 	.set_termios = mxser_set_termios,
2328*4882a593Smuzhiyun 	.stop = mxser_stop,
2329*4882a593Smuzhiyun 	.start = mxser_start,
2330*4882a593Smuzhiyun 	.hangup = mxser_hangup,
2331*4882a593Smuzhiyun 	.break_ctl = mxser_rs_break,
2332*4882a593Smuzhiyun 	.wait_until_sent = mxser_wait_until_sent,
2333*4882a593Smuzhiyun 	.tiocmget = mxser_tiocmget,
2334*4882a593Smuzhiyun 	.tiocmset = mxser_tiocmset,
2335*4882a593Smuzhiyun 	.set_serial = mxser_set_serial_info,
2336*4882a593Smuzhiyun 	.get_serial = mxser_get_serial_info,
2337*4882a593Smuzhiyun 	.get_icount = mxser_get_icount,
2338*4882a593Smuzhiyun };
2339*4882a593Smuzhiyun 
2340*4882a593Smuzhiyun static const struct tty_port_operations mxser_port_ops = {
2341*4882a593Smuzhiyun 	.carrier_raised = mxser_carrier_raised,
2342*4882a593Smuzhiyun 	.dtr_rts = mxser_dtr_rts,
2343*4882a593Smuzhiyun 	.activate = mxser_activate,
2344*4882a593Smuzhiyun 	.shutdown = mxser_shutdown_port,
2345*4882a593Smuzhiyun };
2346*4882a593Smuzhiyun 
2347*4882a593Smuzhiyun /*
2348*4882a593Smuzhiyun  * The MOXA Smartio/Industio serial driver boot-time initialization code!
2349*4882a593Smuzhiyun  */
2350*4882a593Smuzhiyun 
2351*4882a593Smuzhiyun static bool allow_overlapping_vector;
2352*4882a593Smuzhiyun module_param(allow_overlapping_vector, bool, S_IRUGO);
2353*4882a593Smuzhiyun MODULE_PARM_DESC(allow_overlapping_vector, "whether we allow ISA cards to be configured such that vector overlabs IO ports (default=no)");
2354*4882a593Smuzhiyun 
mxser_overlapping_vector(struct mxser_board * brd)2355*4882a593Smuzhiyun static bool mxser_overlapping_vector(struct mxser_board *brd)
2356*4882a593Smuzhiyun {
2357*4882a593Smuzhiyun 	return allow_overlapping_vector &&
2358*4882a593Smuzhiyun 		brd->vector >= brd->ports[0].ioaddr &&
2359*4882a593Smuzhiyun 		brd->vector < brd->ports[0].ioaddr + 8 * brd->info->nports;
2360*4882a593Smuzhiyun }
2361*4882a593Smuzhiyun 
mxser_request_vector(struct mxser_board * brd)2362*4882a593Smuzhiyun static int mxser_request_vector(struct mxser_board *brd)
2363*4882a593Smuzhiyun {
2364*4882a593Smuzhiyun 	if (mxser_overlapping_vector(brd))
2365*4882a593Smuzhiyun 		return 0;
2366*4882a593Smuzhiyun 	return request_region(brd->vector, 1, "mxser(vector)") ? 0 : -EIO;
2367*4882a593Smuzhiyun }
2368*4882a593Smuzhiyun 
mxser_release_vector(struct mxser_board * brd)2369*4882a593Smuzhiyun static void mxser_release_vector(struct mxser_board *brd)
2370*4882a593Smuzhiyun {
2371*4882a593Smuzhiyun 	if (mxser_overlapping_vector(brd))
2372*4882a593Smuzhiyun 		return;
2373*4882a593Smuzhiyun 	release_region(brd->vector, 1);
2374*4882a593Smuzhiyun }
2375*4882a593Smuzhiyun 
mxser_release_ISA_res(struct mxser_board * brd)2376*4882a593Smuzhiyun static void mxser_release_ISA_res(struct mxser_board *brd)
2377*4882a593Smuzhiyun {
2378*4882a593Smuzhiyun 	release_region(brd->ports[0].ioaddr, 8 * brd->info->nports);
2379*4882a593Smuzhiyun 	mxser_release_vector(brd);
2380*4882a593Smuzhiyun }
2381*4882a593Smuzhiyun 
mxser_initbrd(struct mxser_board * brd)2382*4882a593Smuzhiyun static int mxser_initbrd(struct mxser_board *brd)
2383*4882a593Smuzhiyun {
2384*4882a593Smuzhiyun 	struct mxser_port *info;
2385*4882a593Smuzhiyun 	unsigned int i;
2386*4882a593Smuzhiyun 	int retval;
2387*4882a593Smuzhiyun 
2388*4882a593Smuzhiyun 	printk(KERN_INFO "mxser: max. baud rate = %d bps\n",
2389*4882a593Smuzhiyun 			brd->ports[0].max_baud);
2390*4882a593Smuzhiyun 
2391*4882a593Smuzhiyun 	for (i = 0; i < brd->info->nports; i++) {
2392*4882a593Smuzhiyun 		info = &brd->ports[i];
2393*4882a593Smuzhiyun 		tty_port_init(&info->port);
2394*4882a593Smuzhiyun 		info->port.ops = &mxser_port_ops;
2395*4882a593Smuzhiyun 		info->board = brd;
2396*4882a593Smuzhiyun 		info->stop_rx = 0;
2397*4882a593Smuzhiyun 		info->ldisc_stop_rx = 0;
2398*4882a593Smuzhiyun 
2399*4882a593Smuzhiyun 		/* Enhance mode enabled here */
2400*4882a593Smuzhiyun 		if (brd->chip_flag != MOXA_OTHER_UART)
2401*4882a593Smuzhiyun 			mxser_enable_must_enchance_mode(info->ioaddr);
2402*4882a593Smuzhiyun 
2403*4882a593Smuzhiyun 		info->type = brd->uart_type;
2404*4882a593Smuzhiyun 
2405*4882a593Smuzhiyun 		process_txrx_fifo(info);
2406*4882a593Smuzhiyun 
2407*4882a593Smuzhiyun 		info->custom_divisor = info->baud_base * 16;
2408*4882a593Smuzhiyun 		info->port.close_delay = 5 * HZ / 10;
2409*4882a593Smuzhiyun 		info->port.closing_wait = 30 * HZ;
2410*4882a593Smuzhiyun 		info->normal_termios = mxvar_sdriver->init_termios;
2411*4882a593Smuzhiyun 		memset(&info->mon_data, 0, sizeof(struct mxser_mon));
2412*4882a593Smuzhiyun 		info->err_shadow = 0;
2413*4882a593Smuzhiyun 		spin_lock_init(&info->slock);
2414*4882a593Smuzhiyun 
2415*4882a593Smuzhiyun 		/* before set INT ISR, disable all int */
2416*4882a593Smuzhiyun 		outb(inb(info->ioaddr + UART_IER) & 0xf0,
2417*4882a593Smuzhiyun 			info->ioaddr + UART_IER);
2418*4882a593Smuzhiyun 	}
2419*4882a593Smuzhiyun 
2420*4882a593Smuzhiyun 	retval = request_irq(brd->irq, mxser_interrupt, IRQF_SHARED, "mxser",
2421*4882a593Smuzhiyun 			brd);
2422*4882a593Smuzhiyun 	if (retval) {
2423*4882a593Smuzhiyun 		for (i = 0; i < brd->info->nports; i++)
2424*4882a593Smuzhiyun 			tty_port_destroy(&brd->ports[i].port);
2425*4882a593Smuzhiyun 		printk(KERN_ERR "Board %s: Request irq failed, IRQ (%d) may "
2426*4882a593Smuzhiyun 			"conflict with another device.\n",
2427*4882a593Smuzhiyun 			brd->info->name, brd->irq);
2428*4882a593Smuzhiyun 	}
2429*4882a593Smuzhiyun 
2430*4882a593Smuzhiyun 	return retval;
2431*4882a593Smuzhiyun }
2432*4882a593Smuzhiyun 
mxser_board_remove(struct mxser_board * brd)2433*4882a593Smuzhiyun static void mxser_board_remove(struct mxser_board *brd)
2434*4882a593Smuzhiyun {
2435*4882a593Smuzhiyun 	unsigned int i;
2436*4882a593Smuzhiyun 
2437*4882a593Smuzhiyun 	for (i = 0; i < brd->info->nports; i++) {
2438*4882a593Smuzhiyun 		tty_unregister_device(mxvar_sdriver, brd->idx + i);
2439*4882a593Smuzhiyun 		tty_port_destroy(&brd->ports[i].port);
2440*4882a593Smuzhiyun 	}
2441*4882a593Smuzhiyun 	free_irq(brd->irq, brd);
2442*4882a593Smuzhiyun }
2443*4882a593Smuzhiyun 
mxser_get_ISA_conf(int cap,struct mxser_board * brd)2444*4882a593Smuzhiyun static int __init mxser_get_ISA_conf(int cap, struct mxser_board *brd)
2445*4882a593Smuzhiyun {
2446*4882a593Smuzhiyun 	int id, i, bits, ret;
2447*4882a593Smuzhiyun 	unsigned short regs[16], irq;
2448*4882a593Smuzhiyun 	unsigned char scratch, scratch2;
2449*4882a593Smuzhiyun 
2450*4882a593Smuzhiyun 	brd->chip_flag = MOXA_OTHER_UART;
2451*4882a593Smuzhiyun 
2452*4882a593Smuzhiyun 	id = mxser_read_register(cap, regs);
2453*4882a593Smuzhiyun 	switch (id) {
2454*4882a593Smuzhiyun 	case C168_ASIC_ID:
2455*4882a593Smuzhiyun 		brd->info = &mxser_cards[0];
2456*4882a593Smuzhiyun 		break;
2457*4882a593Smuzhiyun 	case C104_ASIC_ID:
2458*4882a593Smuzhiyun 		brd->info = &mxser_cards[1];
2459*4882a593Smuzhiyun 		break;
2460*4882a593Smuzhiyun 	case CI104J_ASIC_ID:
2461*4882a593Smuzhiyun 		brd->info = &mxser_cards[2];
2462*4882a593Smuzhiyun 		break;
2463*4882a593Smuzhiyun 	case C102_ASIC_ID:
2464*4882a593Smuzhiyun 		brd->info = &mxser_cards[5];
2465*4882a593Smuzhiyun 		break;
2466*4882a593Smuzhiyun 	case CI132_ASIC_ID:
2467*4882a593Smuzhiyun 		brd->info = &mxser_cards[6];
2468*4882a593Smuzhiyun 		break;
2469*4882a593Smuzhiyun 	case CI134_ASIC_ID:
2470*4882a593Smuzhiyun 		brd->info = &mxser_cards[7];
2471*4882a593Smuzhiyun 		break;
2472*4882a593Smuzhiyun 	default:
2473*4882a593Smuzhiyun 		return 0;
2474*4882a593Smuzhiyun 	}
2475*4882a593Smuzhiyun 
2476*4882a593Smuzhiyun 	irq = 0;
2477*4882a593Smuzhiyun 	/* some ISA cards have 2 ports, but we want to see them as 4-port (why?)
2478*4882a593Smuzhiyun 	   Flag-hack checks if configuration should be read as 2-port here. */
2479*4882a593Smuzhiyun 	if (brd->info->nports == 2 || (brd->info->flags & MXSER_HAS2)) {
2480*4882a593Smuzhiyun 		irq = regs[9] & 0xF000;
2481*4882a593Smuzhiyun 		irq = irq | (irq >> 4);
2482*4882a593Smuzhiyun 		if (irq != (regs[9] & 0xFF00))
2483*4882a593Smuzhiyun 			goto err_irqconflict;
2484*4882a593Smuzhiyun 	} else if (brd->info->nports == 4) {
2485*4882a593Smuzhiyun 		irq = regs[9] & 0xF000;
2486*4882a593Smuzhiyun 		irq = irq | (irq >> 4);
2487*4882a593Smuzhiyun 		irq = irq | (irq >> 8);
2488*4882a593Smuzhiyun 		if (irq != regs[9])
2489*4882a593Smuzhiyun 			goto err_irqconflict;
2490*4882a593Smuzhiyun 	} else if (brd->info->nports == 8) {
2491*4882a593Smuzhiyun 		irq = regs[9] & 0xF000;
2492*4882a593Smuzhiyun 		irq = irq | (irq >> 4);
2493*4882a593Smuzhiyun 		irq = irq | (irq >> 8);
2494*4882a593Smuzhiyun 		if ((irq != regs[9]) || (irq != regs[10]))
2495*4882a593Smuzhiyun 			goto err_irqconflict;
2496*4882a593Smuzhiyun 	}
2497*4882a593Smuzhiyun 
2498*4882a593Smuzhiyun 	if (!irq) {
2499*4882a593Smuzhiyun 		printk(KERN_ERR "mxser: interrupt number unset\n");
2500*4882a593Smuzhiyun 		return -EIO;
2501*4882a593Smuzhiyun 	}
2502*4882a593Smuzhiyun 	brd->irq = ((int)(irq & 0xF000) >> 12);
2503*4882a593Smuzhiyun 	for (i = 0; i < 8; i++)
2504*4882a593Smuzhiyun 		brd->ports[i].ioaddr = (int) regs[i + 1] & 0xFFF8;
2505*4882a593Smuzhiyun 	if ((regs[12] & 0x80) == 0) {
2506*4882a593Smuzhiyun 		printk(KERN_ERR "mxser: invalid interrupt vector\n");
2507*4882a593Smuzhiyun 		return -EIO;
2508*4882a593Smuzhiyun 	}
2509*4882a593Smuzhiyun 	brd->vector = (int)regs[11];	/* interrupt vector */
2510*4882a593Smuzhiyun 	if (id == 1)
2511*4882a593Smuzhiyun 		brd->vector_mask = 0x00FF;
2512*4882a593Smuzhiyun 	else
2513*4882a593Smuzhiyun 		brd->vector_mask = 0x000F;
2514*4882a593Smuzhiyun 	for (i = 7, bits = 0x0100; i >= 0; i--, bits <<= 1) {
2515*4882a593Smuzhiyun 		if (regs[12] & bits) {
2516*4882a593Smuzhiyun 			brd->ports[i].baud_base = 921600;
2517*4882a593Smuzhiyun 			brd->ports[i].max_baud = 921600;
2518*4882a593Smuzhiyun 		} else {
2519*4882a593Smuzhiyun 			brd->ports[i].baud_base = 115200;
2520*4882a593Smuzhiyun 			brd->ports[i].max_baud = 115200;
2521*4882a593Smuzhiyun 		}
2522*4882a593Smuzhiyun 	}
2523*4882a593Smuzhiyun 	scratch2 = inb(cap + UART_LCR) & (~UART_LCR_DLAB);
2524*4882a593Smuzhiyun 	outb(scratch2 | UART_LCR_DLAB, cap + UART_LCR);
2525*4882a593Smuzhiyun 	outb(0, cap + UART_EFR);	/* EFR is the same as FCR */
2526*4882a593Smuzhiyun 	outb(scratch2, cap + UART_LCR);
2527*4882a593Smuzhiyun 	outb(UART_FCR_ENABLE_FIFO, cap + UART_FCR);
2528*4882a593Smuzhiyun 	scratch = inb(cap + UART_IIR);
2529*4882a593Smuzhiyun 
2530*4882a593Smuzhiyun 	if (scratch & 0xC0)
2531*4882a593Smuzhiyun 		brd->uart_type = PORT_16550A;
2532*4882a593Smuzhiyun 	else
2533*4882a593Smuzhiyun 		brd->uart_type = PORT_16450;
2534*4882a593Smuzhiyun 	if (!request_region(brd->ports[0].ioaddr, 8 * brd->info->nports,
2535*4882a593Smuzhiyun 			"mxser(IO)")) {
2536*4882a593Smuzhiyun 		printk(KERN_ERR "mxser: can't request ports I/O region: "
2537*4882a593Smuzhiyun 				"0x%.8lx-0x%.8lx\n",
2538*4882a593Smuzhiyun 				brd->ports[0].ioaddr, brd->ports[0].ioaddr +
2539*4882a593Smuzhiyun 				8 * brd->info->nports - 1);
2540*4882a593Smuzhiyun 		return -EIO;
2541*4882a593Smuzhiyun 	}
2542*4882a593Smuzhiyun 
2543*4882a593Smuzhiyun 	ret = mxser_request_vector(brd);
2544*4882a593Smuzhiyun 	if (ret) {
2545*4882a593Smuzhiyun 		release_region(brd->ports[0].ioaddr, 8 * brd->info->nports);
2546*4882a593Smuzhiyun 		printk(KERN_ERR "mxser: can't request interrupt vector region: "
2547*4882a593Smuzhiyun 				"0x%.8lx-0x%.8lx\n",
2548*4882a593Smuzhiyun 				brd->ports[0].ioaddr, brd->ports[0].ioaddr +
2549*4882a593Smuzhiyun 				8 * brd->info->nports - 1);
2550*4882a593Smuzhiyun 		return ret;
2551*4882a593Smuzhiyun 	}
2552*4882a593Smuzhiyun 	return brd->info->nports;
2553*4882a593Smuzhiyun 
2554*4882a593Smuzhiyun err_irqconflict:
2555*4882a593Smuzhiyun 	printk(KERN_ERR "mxser: invalid interrupt number\n");
2556*4882a593Smuzhiyun 	return -EIO;
2557*4882a593Smuzhiyun }
2558*4882a593Smuzhiyun 
mxser_probe(struct pci_dev * pdev,const struct pci_device_id * ent)2559*4882a593Smuzhiyun static int mxser_probe(struct pci_dev *pdev,
2560*4882a593Smuzhiyun 		const struct pci_device_id *ent)
2561*4882a593Smuzhiyun {
2562*4882a593Smuzhiyun #ifdef CONFIG_PCI
2563*4882a593Smuzhiyun 	struct mxser_board *brd;
2564*4882a593Smuzhiyun 	unsigned int i, j;
2565*4882a593Smuzhiyun 	unsigned long ioaddress;
2566*4882a593Smuzhiyun 	struct device *tty_dev;
2567*4882a593Smuzhiyun 	int retval = -EINVAL;
2568*4882a593Smuzhiyun 
2569*4882a593Smuzhiyun 	for (i = 0; i < MXSER_BOARDS; i++)
2570*4882a593Smuzhiyun 		if (mxser_boards[i].info == NULL)
2571*4882a593Smuzhiyun 			break;
2572*4882a593Smuzhiyun 
2573*4882a593Smuzhiyun 	if (i >= MXSER_BOARDS) {
2574*4882a593Smuzhiyun 		dev_err(&pdev->dev, "too many boards found (maximum %d), board "
2575*4882a593Smuzhiyun 				"not configured\n", MXSER_BOARDS);
2576*4882a593Smuzhiyun 		goto err;
2577*4882a593Smuzhiyun 	}
2578*4882a593Smuzhiyun 
2579*4882a593Smuzhiyun 	brd = &mxser_boards[i];
2580*4882a593Smuzhiyun 	brd->idx = i * MXSER_PORTS_PER_BOARD;
2581*4882a593Smuzhiyun 	dev_info(&pdev->dev, "found MOXA %s board (BusNo=%d, DevNo=%d)\n",
2582*4882a593Smuzhiyun 		mxser_cards[ent->driver_data].name,
2583*4882a593Smuzhiyun 		pdev->bus->number, PCI_SLOT(pdev->devfn));
2584*4882a593Smuzhiyun 
2585*4882a593Smuzhiyun 	retval = pci_enable_device(pdev);
2586*4882a593Smuzhiyun 	if (retval) {
2587*4882a593Smuzhiyun 		dev_err(&pdev->dev, "PCI enable failed\n");
2588*4882a593Smuzhiyun 		goto err;
2589*4882a593Smuzhiyun 	}
2590*4882a593Smuzhiyun 
2591*4882a593Smuzhiyun 	/* io address */
2592*4882a593Smuzhiyun 	ioaddress = pci_resource_start(pdev, 2);
2593*4882a593Smuzhiyun 	retval = pci_request_region(pdev, 2, "mxser(IO)");
2594*4882a593Smuzhiyun 	if (retval)
2595*4882a593Smuzhiyun 		goto err_dis;
2596*4882a593Smuzhiyun 
2597*4882a593Smuzhiyun 	brd->info = &mxser_cards[ent->driver_data];
2598*4882a593Smuzhiyun 	for (i = 0; i < brd->info->nports; i++)
2599*4882a593Smuzhiyun 		brd->ports[i].ioaddr = ioaddress + 8 * i;
2600*4882a593Smuzhiyun 
2601*4882a593Smuzhiyun 	/* vector */
2602*4882a593Smuzhiyun 	ioaddress = pci_resource_start(pdev, 3);
2603*4882a593Smuzhiyun 	retval = pci_request_region(pdev, 3, "mxser(vector)");
2604*4882a593Smuzhiyun 	if (retval)
2605*4882a593Smuzhiyun 		goto err_zero;
2606*4882a593Smuzhiyun 	brd->vector = ioaddress;
2607*4882a593Smuzhiyun 
2608*4882a593Smuzhiyun 	/* irq */
2609*4882a593Smuzhiyun 	brd->irq = pdev->irq;
2610*4882a593Smuzhiyun 
2611*4882a593Smuzhiyun 	brd->chip_flag = CheckIsMoxaMust(brd->ports[0].ioaddr);
2612*4882a593Smuzhiyun 	brd->uart_type = PORT_16550A;
2613*4882a593Smuzhiyun 	brd->vector_mask = 0;
2614*4882a593Smuzhiyun 
2615*4882a593Smuzhiyun 	for (i = 0; i < brd->info->nports; i++) {
2616*4882a593Smuzhiyun 		for (j = 0; j < UART_INFO_NUM; j++) {
2617*4882a593Smuzhiyun 			if (Gpci_uart_info[j].type == brd->chip_flag) {
2618*4882a593Smuzhiyun 				brd->ports[i].max_baud =
2619*4882a593Smuzhiyun 					Gpci_uart_info[j].max_baud;
2620*4882a593Smuzhiyun 
2621*4882a593Smuzhiyun 				/* exception....CP-102 */
2622*4882a593Smuzhiyun 				if (brd->info->flags & MXSER_HIGHBAUD)
2623*4882a593Smuzhiyun 					brd->ports[i].max_baud = 921600;
2624*4882a593Smuzhiyun 				break;
2625*4882a593Smuzhiyun 			}
2626*4882a593Smuzhiyun 		}
2627*4882a593Smuzhiyun 	}
2628*4882a593Smuzhiyun 
2629*4882a593Smuzhiyun 	if (brd->chip_flag == MOXA_MUST_MU860_HWID) {
2630*4882a593Smuzhiyun 		for (i = 0; i < brd->info->nports; i++) {
2631*4882a593Smuzhiyun 			if (i < 4)
2632*4882a593Smuzhiyun 				brd->ports[i].opmode_ioaddr = ioaddress + 4;
2633*4882a593Smuzhiyun 			else
2634*4882a593Smuzhiyun 				brd->ports[i].opmode_ioaddr = ioaddress + 0x0c;
2635*4882a593Smuzhiyun 		}
2636*4882a593Smuzhiyun 		outb(0, ioaddress + 4);	/* default set to RS232 mode */
2637*4882a593Smuzhiyun 		outb(0, ioaddress + 0x0c);	/* default set to RS232 mode */
2638*4882a593Smuzhiyun 	}
2639*4882a593Smuzhiyun 
2640*4882a593Smuzhiyun 	for (i = 0; i < brd->info->nports; i++) {
2641*4882a593Smuzhiyun 		brd->vector_mask |= (1 << i);
2642*4882a593Smuzhiyun 		brd->ports[i].baud_base = 921600;
2643*4882a593Smuzhiyun 	}
2644*4882a593Smuzhiyun 
2645*4882a593Smuzhiyun 	/* mxser_initbrd will hook ISR. */
2646*4882a593Smuzhiyun 	retval = mxser_initbrd(brd);
2647*4882a593Smuzhiyun 	if (retval)
2648*4882a593Smuzhiyun 		goto err_rel3;
2649*4882a593Smuzhiyun 
2650*4882a593Smuzhiyun 	for (i = 0; i < brd->info->nports; i++) {
2651*4882a593Smuzhiyun 		tty_dev = tty_port_register_device(&brd->ports[i].port,
2652*4882a593Smuzhiyun 				mxvar_sdriver, brd->idx + i, &pdev->dev);
2653*4882a593Smuzhiyun 		if (IS_ERR(tty_dev)) {
2654*4882a593Smuzhiyun 			retval = PTR_ERR(tty_dev);
2655*4882a593Smuzhiyun 			for (; i > 0; i--)
2656*4882a593Smuzhiyun 				tty_unregister_device(mxvar_sdriver,
2657*4882a593Smuzhiyun 					brd->idx + i - 1);
2658*4882a593Smuzhiyun 			goto err_relbrd;
2659*4882a593Smuzhiyun 		}
2660*4882a593Smuzhiyun 	}
2661*4882a593Smuzhiyun 
2662*4882a593Smuzhiyun 	pci_set_drvdata(pdev, brd);
2663*4882a593Smuzhiyun 
2664*4882a593Smuzhiyun 	return 0;
2665*4882a593Smuzhiyun err_relbrd:
2666*4882a593Smuzhiyun 	for (i = 0; i < brd->info->nports; i++)
2667*4882a593Smuzhiyun 		tty_port_destroy(&brd->ports[i].port);
2668*4882a593Smuzhiyun 	free_irq(brd->irq, brd);
2669*4882a593Smuzhiyun err_rel3:
2670*4882a593Smuzhiyun 	pci_release_region(pdev, 3);
2671*4882a593Smuzhiyun err_zero:
2672*4882a593Smuzhiyun 	brd->info = NULL;
2673*4882a593Smuzhiyun 	pci_release_region(pdev, 2);
2674*4882a593Smuzhiyun err_dis:
2675*4882a593Smuzhiyun 	pci_disable_device(pdev);
2676*4882a593Smuzhiyun err:
2677*4882a593Smuzhiyun 	return retval;
2678*4882a593Smuzhiyun #else
2679*4882a593Smuzhiyun 	return -ENODEV;
2680*4882a593Smuzhiyun #endif
2681*4882a593Smuzhiyun }
2682*4882a593Smuzhiyun 
mxser_remove(struct pci_dev * pdev)2683*4882a593Smuzhiyun static void mxser_remove(struct pci_dev *pdev)
2684*4882a593Smuzhiyun {
2685*4882a593Smuzhiyun #ifdef CONFIG_PCI
2686*4882a593Smuzhiyun 	struct mxser_board *brd = pci_get_drvdata(pdev);
2687*4882a593Smuzhiyun 
2688*4882a593Smuzhiyun 	mxser_board_remove(brd);
2689*4882a593Smuzhiyun 
2690*4882a593Smuzhiyun 	pci_release_region(pdev, 2);
2691*4882a593Smuzhiyun 	pci_release_region(pdev, 3);
2692*4882a593Smuzhiyun 	pci_disable_device(pdev);
2693*4882a593Smuzhiyun 	brd->info = NULL;
2694*4882a593Smuzhiyun #endif
2695*4882a593Smuzhiyun }
2696*4882a593Smuzhiyun 
2697*4882a593Smuzhiyun static struct pci_driver mxser_driver = {
2698*4882a593Smuzhiyun 	.name = "mxser",
2699*4882a593Smuzhiyun 	.id_table = mxser_pcibrds,
2700*4882a593Smuzhiyun 	.probe = mxser_probe,
2701*4882a593Smuzhiyun 	.remove = mxser_remove
2702*4882a593Smuzhiyun };
2703*4882a593Smuzhiyun 
mxser_module_init(void)2704*4882a593Smuzhiyun static int __init mxser_module_init(void)
2705*4882a593Smuzhiyun {
2706*4882a593Smuzhiyun 	struct mxser_board *brd;
2707*4882a593Smuzhiyun 	struct device *tty_dev;
2708*4882a593Smuzhiyun 	unsigned int b, i, m;
2709*4882a593Smuzhiyun 	int retval;
2710*4882a593Smuzhiyun 
2711*4882a593Smuzhiyun 	mxvar_sdriver = alloc_tty_driver(MXSER_PORTS + 1);
2712*4882a593Smuzhiyun 	if (!mxvar_sdriver)
2713*4882a593Smuzhiyun 		return -ENOMEM;
2714*4882a593Smuzhiyun 
2715*4882a593Smuzhiyun 	printk(KERN_INFO "MOXA Smartio/Industio family driver version %s\n",
2716*4882a593Smuzhiyun 		MXSER_VERSION);
2717*4882a593Smuzhiyun 
2718*4882a593Smuzhiyun 	/* Initialize the tty_driver structure */
2719*4882a593Smuzhiyun 	mxvar_sdriver->name = "ttyMI";
2720*4882a593Smuzhiyun 	mxvar_sdriver->major = ttymajor;
2721*4882a593Smuzhiyun 	mxvar_sdriver->minor_start = 0;
2722*4882a593Smuzhiyun 	mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL;
2723*4882a593Smuzhiyun 	mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL;
2724*4882a593Smuzhiyun 	mxvar_sdriver->init_termios = tty_std_termios;
2725*4882a593Smuzhiyun 	mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL;
2726*4882a593Smuzhiyun 	mxvar_sdriver->flags = TTY_DRIVER_REAL_RAW|TTY_DRIVER_DYNAMIC_DEV;
2727*4882a593Smuzhiyun 	tty_set_operations(mxvar_sdriver, &mxser_ops);
2728*4882a593Smuzhiyun 
2729*4882a593Smuzhiyun 	retval = tty_register_driver(mxvar_sdriver);
2730*4882a593Smuzhiyun 	if (retval) {
2731*4882a593Smuzhiyun 		printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family "
2732*4882a593Smuzhiyun 				"tty driver !\n");
2733*4882a593Smuzhiyun 		goto err_put;
2734*4882a593Smuzhiyun 	}
2735*4882a593Smuzhiyun 
2736*4882a593Smuzhiyun 	/* Start finding ISA boards here */
2737*4882a593Smuzhiyun 	for (m = 0, b = 0; b < MXSER_BOARDS; b++) {
2738*4882a593Smuzhiyun 		if (!ioaddr[b])
2739*4882a593Smuzhiyun 			continue;
2740*4882a593Smuzhiyun 
2741*4882a593Smuzhiyun 		brd = &mxser_boards[m];
2742*4882a593Smuzhiyun 		retval = mxser_get_ISA_conf(ioaddr[b], brd);
2743*4882a593Smuzhiyun 		if (retval <= 0) {
2744*4882a593Smuzhiyun 			brd->info = NULL;
2745*4882a593Smuzhiyun 			continue;
2746*4882a593Smuzhiyun 		}
2747*4882a593Smuzhiyun 
2748*4882a593Smuzhiyun 		printk(KERN_INFO "mxser: found MOXA %s board (CAP=0x%lx)\n",
2749*4882a593Smuzhiyun 				brd->info->name, ioaddr[b]);
2750*4882a593Smuzhiyun 
2751*4882a593Smuzhiyun 		/* mxser_initbrd will hook ISR. */
2752*4882a593Smuzhiyun 		if (mxser_initbrd(brd) < 0) {
2753*4882a593Smuzhiyun 			mxser_release_ISA_res(brd);
2754*4882a593Smuzhiyun 			brd->info = NULL;
2755*4882a593Smuzhiyun 			continue;
2756*4882a593Smuzhiyun 		}
2757*4882a593Smuzhiyun 
2758*4882a593Smuzhiyun 		brd->idx = m * MXSER_PORTS_PER_BOARD;
2759*4882a593Smuzhiyun 		for (i = 0; i < brd->info->nports; i++) {
2760*4882a593Smuzhiyun 			tty_dev = tty_port_register_device(&brd->ports[i].port,
2761*4882a593Smuzhiyun 					mxvar_sdriver, brd->idx + i, NULL);
2762*4882a593Smuzhiyun 			if (IS_ERR(tty_dev)) {
2763*4882a593Smuzhiyun 				for (; i > 0; i--)
2764*4882a593Smuzhiyun 					tty_unregister_device(mxvar_sdriver,
2765*4882a593Smuzhiyun 						brd->idx + i - 1);
2766*4882a593Smuzhiyun 				for (i = 0; i < brd->info->nports; i++)
2767*4882a593Smuzhiyun 					tty_port_destroy(&brd->ports[i].port);
2768*4882a593Smuzhiyun 				free_irq(brd->irq, brd);
2769*4882a593Smuzhiyun 				mxser_release_ISA_res(brd);
2770*4882a593Smuzhiyun 				brd->info = NULL;
2771*4882a593Smuzhiyun 				break;
2772*4882a593Smuzhiyun 			}
2773*4882a593Smuzhiyun 		}
2774*4882a593Smuzhiyun 		if (brd->info == NULL)
2775*4882a593Smuzhiyun 			continue;
2776*4882a593Smuzhiyun 
2777*4882a593Smuzhiyun 		m++;
2778*4882a593Smuzhiyun 	}
2779*4882a593Smuzhiyun 
2780*4882a593Smuzhiyun 	retval = pci_register_driver(&mxser_driver);
2781*4882a593Smuzhiyun 	if (retval) {
2782*4882a593Smuzhiyun 		printk(KERN_ERR "mxser: can't register pci driver\n");
2783*4882a593Smuzhiyun 		if (!m) {
2784*4882a593Smuzhiyun 			retval = -ENODEV;
2785*4882a593Smuzhiyun 			goto err_unr;
2786*4882a593Smuzhiyun 		} /* else: we have some ISA cards under control */
2787*4882a593Smuzhiyun 	}
2788*4882a593Smuzhiyun 
2789*4882a593Smuzhiyun 	return 0;
2790*4882a593Smuzhiyun err_unr:
2791*4882a593Smuzhiyun 	tty_unregister_driver(mxvar_sdriver);
2792*4882a593Smuzhiyun err_put:
2793*4882a593Smuzhiyun 	put_tty_driver(mxvar_sdriver);
2794*4882a593Smuzhiyun 	return retval;
2795*4882a593Smuzhiyun }
2796*4882a593Smuzhiyun 
mxser_module_exit(void)2797*4882a593Smuzhiyun static void __exit mxser_module_exit(void)
2798*4882a593Smuzhiyun {
2799*4882a593Smuzhiyun 	unsigned int i;
2800*4882a593Smuzhiyun 
2801*4882a593Smuzhiyun 	pci_unregister_driver(&mxser_driver);
2802*4882a593Smuzhiyun 
2803*4882a593Smuzhiyun 	for (i = 0; i < MXSER_BOARDS; i++) /* ISA remains */
2804*4882a593Smuzhiyun 		if (mxser_boards[i].info != NULL)
2805*4882a593Smuzhiyun 			mxser_board_remove(&mxser_boards[i]);
2806*4882a593Smuzhiyun 	tty_unregister_driver(mxvar_sdriver);
2807*4882a593Smuzhiyun 	put_tty_driver(mxvar_sdriver);
2808*4882a593Smuzhiyun 
2809*4882a593Smuzhiyun 	for (i = 0; i < MXSER_BOARDS; i++)
2810*4882a593Smuzhiyun 		if (mxser_boards[i].info != NULL)
2811*4882a593Smuzhiyun 			mxser_release_ISA_res(&mxser_boards[i]);
2812*4882a593Smuzhiyun }
2813*4882a593Smuzhiyun 
2814*4882a593Smuzhiyun module_init(mxser_module_init);
2815*4882a593Smuzhiyun module_exit(mxser_module_exit);
2816