xref: /OK3568_Linux_fs/kernel/drivers/thunderbolt/tmu.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Thunderbolt Time Management Unit (TMU) support
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2019, Intel Corporation
6*4882a593Smuzhiyun  * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
7*4882a593Smuzhiyun  *	    Rajmohan Mani <rajmohan.mani@intel.com>
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/delay.h>
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include "tb.h"
13*4882a593Smuzhiyun 
tb_switch_tmu_mode_name(const struct tb_switch * sw)14*4882a593Smuzhiyun static const char *tb_switch_tmu_mode_name(const struct tb_switch *sw)
15*4882a593Smuzhiyun {
16*4882a593Smuzhiyun 	bool root_switch = !tb_route(sw);
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun 	switch (sw->tmu.rate) {
19*4882a593Smuzhiyun 	case TB_SWITCH_TMU_RATE_OFF:
20*4882a593Smuzhiyun 		return "off";
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun 	case TB_SWITCH_TMU_RATE_HIFI:
23*4882a593Smuzhiyun 		/* Root switch does not have upstream directionality */
24*4882a593Smuzhiyun 		if (root_switch)
25*4882a593Smuzhiyun 			return "HiFi";
26*4882a593Smuzhiyun 		if (sw->tmu.unidirectional)
27*4882a593Smuzhiyun 			return "uni-directional, HiFi";
28*4882a593Smuzhiyun 		return "bi-directional, HiFi";
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun 	case TB_SWITCH_TMU_RATE_NORMAL:
31*4882a593Smuzhiyun 		if (root_switch)
32*4882a593Smuzhiyun 			return "normal";
33*4882a593Smuzhiyun 		return "uni-directional, normal";
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun 	default:
36*4882a593Smuzhiyun 		return "unknown";
37*4882a593Smuzhiyun 	}
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun 
tb_switch_tmu_ucap_supported(struct tb_switch * sw)40*4882a593Smuzhiyun static bool tb_switch_tmu_ucap_supported(struct tb_switch *sw)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun 	int ret;
43*4882a593Smuzhiyun 	u32 val;
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
46*4882a593Smuzhiyun 			 sw->tmu.cap + TMU_RTR_CS_0, 1);
47*4882a593Smuzhiyun 	if (ret)
48*4882a593Smuzhiyun 		return false;
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun 	return !!(val & TMU_RTR_CS_0_UCAP);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun 
tb_switch_tmu_rate_read(struct tb_switch * sw)53*4882a593Smuzhiyun static int tb_switch_tmu_rate_read(struct tb_switch *sw)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun 	int ret;
56*4882a593Smuzhiyun 	u32 val;
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
59*4882a593Smuzhiyun 			 sw->tmu.cap + TMU_RTR_CS_3, 1);
60*4882a593Smuzhiyun 	if (ret)
61*4882a593Smuzhiyun 		return ret;
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun 	val >>= TMU_RTR_CS_3_TS_PACKET_INTERVAL_SHIFT;
64*4882a593Smuzhiyun 	return val;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun 
tb_switch_tmu_rate_write(struct tb_switch * sw,int rate)67*4882a593Smuzhiyun static int tb_switch_tmu_rate_write(struct tb_switch *sw, int rate)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun 	int ret;
70*4882a593Smuzhiyun 	u32 val;
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
73*4882a593Smuzhiyun 			 sw->tmu.cap + TMU_RTR_CS_3, 1);
74*4882a593Smuzhiyun 	if (ret)
75*4882a593Smuzhiyun 		return ret;
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	val &= ~TMU_RTR_CS_3_TS_PACKET_INTERVAL_MASK;
78*4882a593Smuzhiyun 	val |= rate << TMU_RTR_CS_3_TS_PACKET_INTERVAL_SHIFT;
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	return tb_sw_write(sw, &val, TB_CFG_SWITCH,
81*4882a593Smuzhiyun 			   sw->tmu.cap + TMU_RTR_CS_3, 1);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun 
tb_port_tmu_write(struct tb_port * port,u8 offset,u32 mask,u32 value)84*4882a593Smuzhiyun static int tb_port_tmu_write(struct tb_port *port, u8 offset, u32 mask,
85*4882a593Smuzhiyun 			     u32 value)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun 	u32 data;
88*4882a593Smuzhiyun 	int ret;
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	ret = tb_port_read(port, &data, TB_CFG_PORT, port->cap_tmu + offset, 1);
91*4882a593Smuzhiyun 	if (ret)
92*4882a593Smuzhiyun 		return ret;
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	data &= ~mask;
95*4882a593Smuzhiyun 	data |= value;
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	return tb_port_write(port, &data, TB_CFG_PORT,
98*4882a593Smuzhiyun 			     port->cap_tmu + offset, 1);
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun 
tb_port_tmu_set_unidirectional(struct tb_port * port,bool unidirectional)101*4882a593Smuzhiyun static int tb_port_tmu_set_unidirectional(struct tb_port *port,
102*4882a593Smuzhiyun 					  bool unidirectional)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun 	u32 val;
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	if (!port->sw->tmu.has_ucap)
107*4882a593Smuzhiyun 		return 0;
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	val = unidirectional ? TMU_ADP_CS_3_UDM : 0;
110*4882a593Smuzhiyun 	return tb_port_tmu_write(port, TMU_ADP_CS_3, TMU_ADP_CS_3_UDM, val);
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun 
tb_port_tmu_unidirectional_disable(struct tb_port * port)113*4882a593Smuzhiyun static inline int tb_port_tmu_unidirectional_disable(struct tb_port *port)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun 	return tb_port_tmu_set_unidirectional(port, false);
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun 
tb_port_tmu_is_unidirectional(struct tb_port * port)118*4882a593Smuzhiyun static bool tb_port_tmu_is_unidirectional(struct tb_port *port)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun 	int ret;
121*4882a593Smuzhiyun 	u32 val;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	ret = tb_port_read(port, &val, TB_CFG_PORT,
124*4882a593Smuzhiyun 			   port->cap_tmu + TMU_ADP_CS_3, 1);
125*4882a593Smuzhiyun 	if (ret)
126*4882a593Smuzhiyun 		return false;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	return val & TMU_ADP_CS_3_UDM;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun 
tb_switch_tmu_set_time_disruption(struct tb_switch * sw,bool set)131*4882a593Smuzhiyun static int tb_switch_tmu_set_time_disruption(struct tb_switch *sw, bool set)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun 	int ret;
134*4882a593Smuzhiyun 	u32 val;
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
137*4882a593Smuzhiyun 			 sw->tmu.cap + TMU_RTR_CS_0, 1);
138*4882a593Smuzhiyun 	if (ret)
139*4882a593Smuzhiyun 		return ret;
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	if (set)
142*4882a593Smuzhiyun 		val |= TMU_RTR_CS_0_TD;
143*4882a593Smuzhiyun 	else
144*4882a593Smuzhiyun 		val &= ~TMU_RTR_CS_0_TD;
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	return tb_sw_write(sw, &val, TB_CFG_SWITCH,
147*4882a593Smuzhiyun 			   sw->tmu.cap + TMU_RTR_CS_0, 1);
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun /**
151*4882a593Smuzhiyun  * tb_switch_tmu_init() - Initialize switch TMU structures
152*4882a593Smuzhiyun  * @sw: Switch to initialized
153*4882a593Smuzhiyun  *
154*4882a593Smuzhiyun  * This function must be called before other TMU related functions to
155*4882a593Smuzhiyun  * makes the internal structures are filled in correctly. Does not
156*4882a593Smuzhiyun  * change any hardware configuration.
157*4882a593Smuzhiyun  */
tb_switch_tmu_init(struct tb_switch * sw)158*4882a593Smuzhiyun int tb_switch_tmu_init(struct tb_switch *sw)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun 	struct tb_port *port;
161*4882a593Smuzhiyun 	int ret;
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	if (tb_switch_is_icm(sw))
164*4882a593Smuzhiyun 		return 0;
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun 	ret = tb_switch_find_cap(sw, TB_SWITCH_CAP_TMU);
167*4882a593Smuzhiyun 	if (ret > 0)
168*4882a593Smuzhiyun 		sw->tmu.cap = ret;
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	tb_switch_for_each_port(sw, port) {
171*4882a593Smuzhiyun 		int cap;
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 		cap = tb_port_find_cap(port, TB_PORT_CAP_TIME1);
174*4882a593Smuzhiyun 		if (cap > 0)
175*4882a593Smuzhiyun 			port->cap_tmu = cap;
176*4882a593Smuzhiyun 	}
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	ret = tb_switch_tmu_rate_read(sw);
179*4882a593Smuzhiyun 	if (ret < 0)
180*4882a593Smuzhiyun 		return ret;
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	sw->tmu.rate = ret;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	sw->tmu.has_ucap = tb_switch_tmu_ucap_supported(sw);
185*4882a593Smuzhiyun 	if (sw->tmu.has_ucap) {
186*4882a593Smuzhiyun 		tb_sw_dbg(sw, "TMU: supports uni-directional mode\n");
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 		if (tb_route(sw)) {
189*4882a593Smuzhiyun 			struct tb_port *up = tb_upstream_port(sw);
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 			sw->tmu.unidirectional =
192*4882a593Smuzhiyun 				tb_port_tmu_is_unidirectional(up);
193*4882a593Smuzhiyun 		}
194*4882a593Smuzhiyun 	} else {
195*4882a593Smuzhiyun 		sw->tmu.unidirectional = false;
196*4882a593Smuzhiyun 	}
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	tb_sw_dbg(sw, "TMU: current mode: %s\n", tb_switch_tmu_mode_name(sw));
199*4882a593Smuzhiyun 	return 0;
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun /**
203*4882a593Smuzhiyun  * tb_switch_tmu_post_time() - Update switch local time
204*4882a593Smuzhiyun  * @sw: Switch whose time to update
205*4882a593Smuzhiyun  *
206*4882a593Smuzhiyun  * Updates switch local time using time posting procedure.
207*4882a593Smuzhiyun  */
tb_switch_tmu_post_time(struct tb_switch * sw)208*4882a593Smuzhiyun int tb_switch_tmu_post_time(struct tb_switch *sw)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun 	unsigned int  post_local_time_offset, post_time_offset;
211*4882a593Smuzhiyun 	struct tb_switch *root_switch = sw->tb->root_switch;
212*4882a593Smuzhiyun 	u64 hi, mid, lo, local_time, post_time;
213*4882a593Smuzhiyun 	int i, ret, retries = 100;
214*4882a593Smuzhiyun 	u32 gm_local_time[3];
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	if (!tb_route(sw))
217*4882a593Smuzhiyun 		return 0;
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 	if (!tb_switch_is_usb4(sw))
220*4882a593Smuzhiyun 		return 0;
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	/* Need to be able to read the grand master time */
223*4882a593Smuzhiyun 	if (!root_switch->tmu.cap)
224*4882a593Smuzhiyun 		return 0;
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 	ret = tb_sw_read(root_switch, gm_local_time, TB_CFG_SWITCH,
227*4882a593Smuzhiyun 			 root_switch->tmu.cap + TMU_RTR_CS_1,
228*4882a593Smuzhiyun 			 ARRAY_SIZE(gm_local_time));
229*4882a593Smuzhiyun 	if (ret)
230*4882a593Smuzhiyun 		return ret;
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(gm_local_time); i++)
233*4882a593Smuzhiyun 		tb_sw_dbg(root_switch, "local_time[%d]=0x%08x\n", i,
234*4882a593Smuzhiyun 			  gm_local_time[i]);
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun 	/* Convert to nanoseconds (drop fractional part) */
237*4882a593Smuzhiyun 	hi = gm_local_time[2] & TMU_RTR_CS_3_LOCAL_TIME_NS_MASK;
238*4882a593Smuzhiyun 	mid = gm_local_time[1];
239*4882a593Smuzhiyun 	lo = (gm_local_time[0] & TMU_RTR_CS_1_LOCAL_TIME_NS_MASK) >>
240*4882a593Smuzhiyun 		TMU_RTR_CS_1_LOCAL_TIME_NS_SHIFT;
241*4882a593Smuzhiyun 	local_time = hi << 48 | mid << 16 | lo;
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	/* Tell the switch that time sync is disrupted for a while */
244*4882a593Smuzhiyun 	ret = tb_switch_tmu_set_time_disruption(sw, true);
245*4882a593Smuzhiyun 	if (ret)
246*4882a593Smuzhiyun 		return ret;
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	post_local_time_offset = sw->tmu.cap + TMU_RTR_CS_22;
249*4882a593Smuzhiyun 	post_time_offset = sw->tmu.cap + TMU_RTR_CS_24;
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	/*
252*4882a593Smuzhiyun 	 * Write the Grandmaster time to the Post Local Time registers
253*4882a593Smuzhiyun 	 * of the new switch.
254*4882a593Smuzhiyun 	 */
255*4882a593Smuzhiyun 	ret = tb_sw_write(sw, &local_time, TB_CFG_SWITCH,
256*4882a593Smuzhiyun 			  post_local_time_offset, 2);
257*4882a593Smuzhiyun 	if (ret)
258*4882a593Smuzhiyun 		goto out;
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun 	/*
261*4882a593Smuzhiyun 	 * Have the new switch update its local time (by writing 1 to
262*4882a593Smuzhiyun 	 * the post_time registers) and wait for the completion of the
263*4882a593Smuzhiyun 	 * same (post_time register becomes 0). This means the time has
264*4882a593Smuzhiyun 	 * been converged properly.
265*4882a593Smuzhiyun 	 */
266*4882a593Smuzhiyun 	post_time = 1;
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	ret = tb_sw_write(sw, &post_time, TB_CFG_SWITCH, post_time_offset, 2);
269*4882a593Smuzhiyun 	if (ret)
270*4882a593Smuzhiyun 		goto out;
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	do {
273*4882a593Smuzhiyun 		usleep_range(5, 10);
274*4882a593Smuzhiyun 		ret = tb_sw_read(sw, &post_time, TB_CFG_SWITCH,
275*4882a593Smuzhiyun 				 post_time_offset, 2);
276*4882a593Smuzhiyun 		if (ret)
277*4882a593Smuzhiyun 			goto out;
278*4882a593Smuzhiyun 	} while (--retries && post_time);
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun 	if (!retries) {
281*4882a593Smuzhiyun 		ret = -ETIMEDOUT;
282*4882a593Smuzhiyun 		goto out;
283*4882a593Smuzhiyun 	}
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 	tb_sw_dbg(sw, "TMU: updated local time to %#llx\n", local_time);
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun out:
288*4882a593Smuzhiyun 	tb_switch_tmu_set_time_disruption(sw, false);
289*4882a593Smuzhiyun 	return ret;
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun /**
293*4882a593Smuzhiyun  * tb_switch_tmu_disable() - Disable TMU of a switch
294*4882a593Smuzhiyun  * @sw: Switch whose TMU to disable
295*4882a593Smuzhiyun  *
296*4882a593Smuzhiyun  * Turns off TMU of @sw if it is enabled. If not enabled does nothing.
297*4882a593Smuzhiyun  */
tb_switch_tmu_disable(struct tb_switch * sw)298*4882a593Smuzhiyun int tb_switch_tmu_disable(struct tb_switch *sw)
299*4882a593Smuzhiyun {
300*4882a593Smuzhiyun 	int ret;
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 	if (!tb_switch_is_usb4(sw))
303*4882a593Smuzhiyun 		return 0;
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun 	/* Already disabled? */
306*4882a593Smuzhiyun 	if (sw->tmu.rate == TB_SWITCH_TMU_RATE_OFF)
307*4882a593Smuzhiyun 		return 0;
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 	if (sw->tmu.unidirectional) {
310*4882a593Smuzhiyun 		struct tb_switch *parent = tb_switch_parent(sw);
311*4882a593Smuzhiyun 		struct tb_port *up, *down;
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 		up = tb_upstream_port(sw);
314*4882a593Smuzhiyun 		down = tb_port_at(tb_route(sw), parent);
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun 		/* The switch may be unplugged so ignore any errors */
317*4882a593Smuzhiyun 		tb_port_tmu_unidirectional_disable(up);
318*4882a593Smuzhiyun 		ret = tb_port_tmu_unidirectional_disable(down);
319*4882a593Smuzhiyun 		if (ret)
320*4882a593Smuzhiyun 			return ret;
321*4882a593Smuzhiyun 	}
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun 	tb_switch_tmu_rate_write(sw, TB_SWITCH_TMU_RATE_OFF);
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun 	sw->tmu.unidirectional = false;
326*4882a593Smuzhiyun 	sw->tmu.rate = TB_SWITCH_TMU_RATE_OFF;
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun 	tb_sw_dbg(sw, "TMU: disabled\n");
329*4882a593Smuzhiyun 	return 0;
330*4882a593Smuzhiyun }
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun /**
333*4882a593Smuzhiyun  * tb_switch_tmu_enable() - Enable TMU on a switch
334*4882a593Smuzhiyun  * @sw: Switch whose TMU to enable
335*4882a593Smuzhiyun  *
336*4882a593Smuzhiyun  * Enables TMU of a switch to be in bi-directional, HiFi mode. In this mode
337*4882a593Smuzhiyun  * all tunneling should work.
338*4882a593Smuzhiyun  */
tb_switch_tmu_enable(struct tb_switch * sw)339*4882a593Smuzhiyun int tb_switch_tmu_enable(struct tb_switch *sw)
340*4882a593Smuzhiyun {
341*4882a593Smuzhiyun 	int ret;
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun 	if (!tb_switch_is_usb4(sw))
344*4882a593Smuzhiyun 		return 0;
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun 	if (tb_switch_tmu_is_enabled(sw))
347*4882a593Smuzhiyun 		return 0;
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun 	ret = tb_switch_tmu_set_time_disruption(sw, true);
350*4882a593Smuzhiyun 	if (ret)
351*4882a593Smuzhiyun 		return ret;
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun 	/* Change mode to bi-directional */
354*4882a593Smuzhiyun 	if (tb_route(sw) && sw->tmu.unidirectional) {
355*4882a593Smuzhiyun 		struct tb_switch *parent = tb_switch_parent(sw);
356*4882a593Smuzhiyun 		struct tb_port *up, *down;
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun 		up = tb_upstream_port(sw);
359*4882a593Smuzhiyun 		down = tb_port_at(tb_route(sw), parent);
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun 		ret = tb_port_tmu_unidirectional_disable(down);
362*4882a593Smuzhiyun 		if (ret)
363*4882a593Smuzhiyun 			return ret;
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun 		ret = tb_switch_tmu_rate_write(sw, TB_SWITCH_TMU_RATE_HIFI);
366*4882a593Smuzhiyun 		if (ret)
367*4882a593Smuzhiyun 			return ret;
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun 		ret = tb_port_tmu_unidirectional_disable(up);
370*4882a593Smuzhiyun 		if (ret)
371*4882a593Smuzhiyun 			return ret;
372*4882a593Smuzhiyun 	} else {
373*4882a593Smuzhiyun 		ret = tb_switch_tmu_rate_write(sw, TB_SWITCH_TMU_RATE_HIFI);
374*4882a593Smuzhiyun 		if (ret)
375*4882a593Smuzhiyun 			return ret;
376*4882a593Smuzhiyun 	}
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun 	sw->tmu.unidirectional = false;
379*4882a593Smuzhiyun 	sw->tmu.rate = TB_SWITCH_TMU_RATE_HIFI;
380*4882a593Smuzhiyun 	tb_sw_dbg(sw, "TMU: mode set to: %s\n", tb_switch_tmu_mode_name(sw));
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun 	return tb_switch_tmu_set_time_disruption(sw, false);
383*4882a593Smuzhiyun }
384