1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * NHI specific operations
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2019, Intel Corporation
6*4882a593Smuzhiyun * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include <linux/suspend.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "nhi.h"
13*4882a593Smuzhiyun #include "nhi_regs.h"
14*4882a593Smuzhiyun #include "tb.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /* Ice Lake specific NHI operations */
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define ICL_LC_MAILBOX_TIMEOUT 500 /* ms */
19*4882a593Smuzhiyun
check_for_device(struct device * dev,void * data)20*4882a593Smuzhiyun static int check_for_device(struct device *dev, void *data)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun return tb_is_switch(dev);
23*4882a593Smuzhiyun }
24*4882a593Smuzhiyun
icl_nhi_is_device_connected(struct tb_nhi * nhi)25*4882a593Smuzhiyun static bool icl_nhi_is_device_connected(struct tb_nhi *nhi)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun struct tb *tb = pci_get_drvdata(nhi->pdev);
28*4882a593Smuzhiyun int ret;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun ret = device_for_each_child(&tb->root_switch->dev, NULL,
31*4882a593Smuzhiyun check_for_device);
32*4882a593Smuzhiyun return ret > 0;
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun
icl_nhi_force_power(struct tb_nhi * nhi,bool power)35*4882a593Smuzhiyun static int icl_nhi_force_power(struct tb_nhi *nhi, bool power)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun u32 vs_cap;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /*
40*4882a593Smuzhiyun * The Thunderbolt host controller is present always in Ice Lake
41*4882a593Smuzhiyun * but the firmware may not be loaded and running (depending
42*4882a593Smuzhiyun * whether there is device connected and so on). Each time the
43*4882a593Smuzhiyun * controller is used we need to "Force Power" it first and wait
44*4882a593Smuzhiyun * for the firmware to indicate it is up and running. This "Force
45*4882a593Smuzhiyun * Power" is really not about actually powering on/off the
46*4882a593Smuzhiyun * controller so it is accessible even if "Force Power" is off.
47*4882a593Smuzhiyun *
48*4882a593Smuzhiyun * The actual power management happens inside shared ACPI power
49*4882a593Smuzhiyun * resources using standard ACPI methods.
50*4882a593Smuzhiyun */
51*4882a593Smuzhiyun pci_read_config_dword(nhi->pdev, VS_CAP_22, &vs_cap);
52*4882a593Smuzhiyun if (power) {
53*4882a593Smuzhiyun vs_cap &= ~VS_CAP_22_DMA_DELAY_MASK;
54*4882a593Smuzhiyun vs_cap |= 0x22 << VS_CAP_22_DMA_DELAY_SHIFT;
55*4882a593Smuzhiyun vs_cap |= VS_CAP_22_FORCE_POWER;
56*4882a593Smuzhiyun } else {
57*4882a593Smuzhiyun vs_cap &= ~VS_CAP_22_FORCE_POWER;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun pci_write_config_dword(nhi->pdev, VS_CAP_22, vs_cap);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun if (power) {
62*4882a593Smuzhiyun unsigned int retries = 350;
63*4882a593Smuzhiyun u32 val;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* Wait until the firmware tells it is up and running */
66*4882a593Smuzhiyun do {
67*4882a593Smuzhiyun pci_read_config_dword(nhi->pdev, VS_CAP_9, &val);
68*4882a593Smuzhiyun if (val & VS_CAP_9_FW_READY)
69*4882a593Smuzhiyun return 0;
70*4882a593Smuzhiyun usleep_range(3000, 3100);
71*4882a593Smuzhiyun } while (--retries);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun return -ETIMEDOUT;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun return 0;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
icl_nhi_lc_mailbox_cmd(struct tb_nhi * nhi,enum icl_lc_mailbox_cmd cmd)79*4882a593Smuzhiyun static void icl_nhi_lc_mailbox_cmd(struct tb_nhi *nhi, enum icl_lc_mailbox_cmd cmd)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun u32 data;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun data = (cmd << VS_CAP_19_CMD_SHIFT) & VS_CAP_19_CMD_MASK;
84*4882a593Smuzhiyun pci_write_config_dword(nhi->pdev, VS_CAP_19, data | VS_CAP_19_VALID);
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
icl_nhi_lc_mailbox_cmd_complete(struct tb_nhi * nhi,int timeout)87*4882a593Smuzhiyun static int icl_nhi_lc_mailbox_cmd_complete(struct tb_nhi *nhi, int timeout)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun unsigned long end;
90*4882a593Smuzhiyun u32 data;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun if (!timeout)
93*4882a593Smuzhiyun goto clear;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun end = jiffies + msecs_to_jiffies(timeout);
96*4882a593Smuzhiyun do {
97*4882a593Smuzhiyun pci_read_config_dword(nhi->pdev, VS_CAP_18, &data);
98*4882a593Smuzhiyun if (data & VS_CAP_18_DONE)
99*4882a593Smuzhiyun goto clear;
100*4882a593Smuzhiyun usleep_range(1000, 1100);
101*4882a593Smuzhiyun } while (time_before(jiffies, end));
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun return -ETIMEDOUT;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun clear:
106*4882a593Smuzhiyun /* Clear the valid bit */
107*4882a593Smuzhiyun pci_write_config_dword(nhi->pdev, VS_CAP_19, 0);
108*4882a593Smuzhiyun return 0;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
icl_nhi_set_ltr(struct tb_nhi * nhi)111*4882a593Smuzhiyun static void icl_nhi_set_ltr(struct tb_nhi *nhi)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun u32 max_ltr, ltr;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun pci_read_config_dword(nhi->pdev, VS_CAP_16, &max_ltr);
116*4882a593Smuzhiyun max_ltr &= 0xffff;
117*4882a593Smuzhiyun /* Program the same value for both snoop and no-snoop */
118*4882a593Smuzhiyun ltr = max_ltr << 16 | max_ltr;
119*4882a593Smuzhiyun pci_write_config_dword(nhi->pdev, VS_CAP_15, ltr);
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
icl_nhi_suspend(struct tb_nhi * nhi)122*4882a593Smuzhiyun static int icl_nhi_suspend(struct tb_nhi *nhi)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun struct tb *tb = pci_get_drvdata(nhi->pdev);
125*4882a593Smuzhiyun int ret;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun if (icl_nhi_is_device_connected(nhi))
128*4882a593Smuzhiyun return 0;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun if (tb_switch_is_icm(tb->root_switch)) {
131*4882a593Smuzhiyun /*
132*4882a593Smuzhiyun * If there is no device connected we need to perform
133*4882a593Smuzhiyun * both: a handshake through LC mailbox and force power
134*4882a593Smuzhiyun * down before entering D3.
135*4882a593Smuzhiyun */
136*4882a593Smuzhiyun icl_nhi_lc_mailbox_cmd(nhi, ICL_LC_PREPARE_FOR_RESET);
137*4882a593Smuzhiyun ret = icl_nhi_lc_mailbox_cmd_complete(nhi, ICL_LC_MAILBOX_TIMEOUT);
138*4882a593Smuzhiyun if (ret)
139*4882a593Smuzhiyun return ret;
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun return icl_nhi_force_power(nhi, false);
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
icl_nhi_suspend_noirq(struct tb_nhi * nhi,bool wakeup)145*4882a593Smuzhiyun static int icl_nhi_suspend_noirq(struct tb_nhi *nhi, bool wakeup)
146*4882a593Smuzhiyun {
147*4882a593Smuzhiyun struct tb *tb = pci_get_drvdata(nhi->pdev);
148*4882a593Smuzhiyun enum icl_lc_mailbox_cmd cmd;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun if (!pm_suspend_via_firmware())
151*4882a593Smuzhiyun return icl_nhi_suspend(nhi);
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun if (!tb_switch_is_icm(tb->root_switch))
154*4882a593Smuzhiyun return 0;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun cmd = wakeup ? ICL_LC_GO2SX : ICL_LC_GO2SX_NO_WAKE;
157*4882a593Smuzhiyun icl_nhi_lc_mailbox_cmd(nhi, cmd);
158*4882a593Smuzhiyun return icl_nhi_lc_mailbox_cmd_complete(nhi, ICL_LC_MAILBOX_TIMEOUT);
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun
icl_nhi_resume(struct tb_nhi * nhi)161*4882a593Smuzhiyun static int icl_nhi_resume(struct tb_nhi *nhi)
162*4882a593Smuzhiyun {
163*4882a593Smuzhiyun int ret;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun ret = icl_nhi_force_power(nhi, true);
166*4882a593Smuzhiyun if (ret)
167*4882a593Smuzhiyun return ret;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun icl_nhi_set_ltr(nhi);
170*4882a593Smuzhiyun return 0;
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun
icl_nhi_shutdown(struct tb_nhi * nhi)173*4882a593Smuzhiyun static void icl_nhi_shutdown(struct tb_nhi *nhi)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun icl_nhi_force_power(nhi, false);
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun const struct tb_nhi_ops icl_nhi_ops = {
179*4882a593Smuzhiyun .init = icl_nhi_resume,
180*4882a593Smuzhiyun .suspend_noirq = icl_nhi_suspend_noirq,
181*4882a593Smuzhiyun .resume_noirq = icl_nhi_resume,
182*4882a593Smuzhiyun .runtime_suspend = icl_nhi_suspend,
183*4882a593Smuzhiyun .runtime_resume = icl_nhi_resume,
184*4882a593Smuzhiyun .shutdown = icl_nhi_shutdown,
185*4882a593Smuzhiyun };
186