1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Thunderbolt driver - NHI driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com> 6*4882a593Smuzhiyun * Copyright (C) 2018, Intel Corporation 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef DSL3510_H_ 10*4882a593Smuzhiyun #define DSL3510_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/thunderbolt.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun enum nhi_fw_mode { 15*4882a593Smuzhiyun NHI_FW_SAFE_MODE, 16*4882a593Smuzhiyun NHI_FW_AUTH_MODE, 17*4882a593Smuzhiyun NHI_FW_EP_MODE, 18*4882a593Smuzhiyun NHI_FW_CM_MODE, 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun enum nhi_mailbox_cmd { 22*4882a593Smuzhiyun NHI_MAILBOX_SAVE_DEVS = 0x05, 23*4882a593Smuzhiyun NHI_MAILBOX_DISCONNECT_PCIE_PATHS = 0x06, 24*4882a593Smuzhiyun NHI_MAILBOX_DRV_UNLOADS = 0x07, 25*4882a593Smuzhiyun NHI_MAILBOX_DISCONNECT_PA = 0x10, 26*4882a593Smuzhiyun NHI_MAILBOX_DISCONNECT_PB = 0x11, 27*4882a593Smuzhiyun NHI_MAILBOX_ALLOW_ALL_DEVS = 0x23, 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data); 31*4882a593Smuzhiyun enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi); 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /** 34*4882a593Smuzhiyun * struct tb_nhi_ops - NHI specific optional operations 35*4882a593Smuzhiyun * @init: NHI specific initialization 36*4882a593Smuzhiyun * @suspend_noirq: NHI specific suspend_noirq hook 37*4882a593Smuzhiyun * @resume_noirq: NHI specific resume_noirq hook 38*4882a593Smuzhiyun * @runtime_suspend: NHI specific runtime_suspend hook 39*4882a593Smuzhiyun * @runtime_resume: NHI specific runtime_resume hook 40*4882a593Smuzhiyun * @shutdown: NHI specific shutdown 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun struct tb_nhi_ops { 43*4882a593Smuzhiyun int (*init)(struct tb_nhi *nhi); 44*4882a593Smuzhiyun int (*suspend_noirq)(struct tb_nhi *nhi, bool wakeup); 45*4882a593Smuzhiyun int (*resume_noirq)(struct tb_nhi *nhi); 46*4882a593Smuzhiyun int (*runtime_suspend)(struct tb_nhi *nhi); 47*4882a593Smuzhiyun int (*runtime_resume)(struct tb_nhi *nhi); 48*4882a593Smuzhiyun void (*shutdown)(struct tb_nhi *nhi); 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun extern const struct tb_nhi_ops icl_nhi_ops; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* 54*4882a593Smuzhiyun * PCI IDs used in this driver from Win Ridge forward. There is no 55*4882a593Smuzhiyun * need for the PCI quirk anymore as we will use ICM also on Apple 56*4882a593Smuzhiyun * hardware. 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_2C_NHI 0x1134 59*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_4C_NHI 0x1137 60*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_NHI 0x157d 61*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_BRIDGE 0x157e 62*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI 0x15bf 63*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE 0x15c0 64*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI 0x15d2 65*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE 0x15d3 66*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI 0x15d9 67*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE 0x15da 68*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI 0x15dc 69*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI 0x15dd 70*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI 0x15de 71*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_BRIDGE 0x15e7 72*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI 0x15e8 73*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_BRIDGE 0x15ea 74*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI 0x15eb 75*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_BRIDGE 0x15ef 76*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_ICL_NHI1 0x8a0d 77*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_ICL_NHI0 0x8a17 78*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_TGL_NHI0 0x9a1b 79*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_TGL_NHI1 0x9a1d 80*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_TGL_H_NHI0 0x9a1f 81*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_TGL_H_NHI1 0x9a21 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define PCI_CLASS_SERIAL_USB_USB4 0x0c0340 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #endif 86