1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * OMAP5xxx bandgap registers, bitfields and temperature definitions 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 6*4882a593Smuzhiyun * Contact: 7*4882a593Smuzhiyun * Eduardo Valentin <eduardo.valentin@ti.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #ifndef __OMAP5XXX_BANDGAP_H 10*4882a593Smuzhiyun #define __OMAP5XXX_BANDGAP_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /** 13*4882a593Smuzhiyun * *** OMAP5430 *** 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * Below, in sequence, are the Register definitions, 16*4882a593Smuzhiyun * the bitfields and the temperature definitions for OMAP5430. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /** 20*4882a593Smuzhiyun * OMAP5430 register definitions 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * Registers are defined as offsets. The offsets are 23*4882a593Smuzhiyun * relative to FUSE_OPP_BGAP_GPU on 5430. 24*4882a593Smuzhiyun * 25*4882a593Smuzhiyun * Register below are grouped by domain (not necessarily in offset order) 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* OMAP5430.GPU register offsets */ 29*4882a593Smuzhiyun #define OMAP5430_FUSE_OPP_BGAP_GPU 0x0 30*4882a593Smuzhiyun #define OMAP5430_TEMP_SENSOR_GPU_OFFSET 0x150 31*4882a593Smuzhiyun #define OMAP5430_BGAP_THRESHOLD_GPU_OFFSET 0x1A8 32*4882a593Smuzhiyun #define OMAP5430_BGAP_TSHUT_GPU_OFFSET 0x1B4 33*4882a593Smuzhiyun #define OMAP5430_BGAP_DTEMP_GPU_1_OFFSET 0x1F8 34*4882a593Smuzhiyun #define OMAP5430_BGAP_DTEMP_GPU_2_OFFSET 0x1FC 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* OMAP5430.MPU register offsets */ 37*4882a593Smuzhiyun #define OMAP5430_FUSE_OPP_BGAP_MPU 0x4 38*4882a593Smuzhiyun #define OMAP5430_TEMP_SENSOR_MPU_OFFSET 0x14C 39*4882a593Smuzhiyun #define OMAP5430_BGAP_THRESHOLD_MPU_OFFSET 0x1A4 40*4882a593Smuzhiyun #define OMAP5430_BGAP_TSHUT_MPU_OFFSET 0x1B0 41*4882a593Smuzhiyun #define OMAP5430_BGAP_DTEMP_MPU_1_OFFSET 0x1E4 42*4882a593Smuzhiyun #define OMAP5430_BGAP_DTEMP_MPU_2_OFFSET 0x1E8 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* OMAP5430.MPU register offsets */ 45*4882a593Smuzhiyun #define OMAP5430_FUSE_OPP_BGAP_CORE 0x8 46*4882a593Smuzhiyun #define OMAP5430_TEMP_SENSOR_CORE_OFFSET 0x154 47*4882a593Smuzhiyun #define OMAP5430_BGAP_THRESHOLD_CORE_OFFSET 0x1AC 48*4882a593Smuzhiyun #define OMAP5430_BGAP_TSHUT_CORE_OFFSET 0x1B8 49*4882a593Smuzhiyun #define OMAP5430_BGAP_DTEMP_CORE_1_OFFSET 0x20C 50*4882a593Smuzhiyun #define OMAP5430_BGAP_DTEMP_CORE_2_OFFSET 0x210 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* OMAP5430.common register offsets */ 53*4882a593Smuzhiyun #define OMAP5430_BGAP_CTRL_OFFSET 0x1A0 54*4882a593Smuzhiyun #define OMAP5430_BGAP_STATUS_OFFSET 0x1C8 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /** 57*4882a593Smuzhiyun * Register bitfields for OMAP5430 58*4882a593Smuzhiyun * 59*4882a593Smuzhiyun * All the macros bellow define the required bits for 60*4882a593Smuzhiyun * controlling temperature on OMAP5430. Bit defines are 61*4882a593Smuzhiyun * grouped by register. 62*4882a593Smuzhiyun */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* OMAP5430.TEMP_SENSOR */ 65*4882a593Smuzhiyun #define OMAP5430_BGAP_TEMP_SENSOR_SOC_MASK BIT(12) 66*4882a593Smuzhiyun #define OMAP5430_BGAP_TEMPSOFF_MASK BIT(11) 67*4882a593Smuzhiyun #define OMAP5430_BGAP_TEMP_SENSOR_EOCZ_MASK BIT(10) 68*4882a593Smuzhiyun #define OMAP5430_BGAP_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* OMAP5430.BANDGAP_CTRL */ 71*4882a593Smuzhiyun #define OMAP5430_MASK_COUNTER_DELAY_MASK (0x7 << 27) 72*4882a593Smuzhiyun #define OMAP5430_MASK_FREEZE_CORE_MASK BIT(23) 73*4882a593Smuzhiyun #define OMAP5430_MASK_FREEZE_GPU_MASK BIT(22) 74*4882a593Smuzhiyun #define OMAP5430_MASK_FREEZE_MPU_MASK BIT(21) 75*4882a593Smuzhiyun #define OMAP5430_MASK_HOT_CORE_MASK BIT(5) 76*4882a593Smuzhiyun #define OMAP5430_MASK_COLD_CORE_MASK BIT(4) 77*4882a593Smuzhiyun #define OMAP5430_MASK_HOT_GPU_MASK BIT(3) 78*4882a593Smuzhiyun #define OMAP5430_MASK_COLD_GPU_MASK BIT(2) 79*4882a593Smuzhiyun #define OMAP5430_MASK_HOT_MPU_MASK BIT(1) 80*4882a593Smuzhiyun #define OMAP5430_MASK_COLD_MPU_MASK BIT(0) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* OMAP5430.BANDGAP_COUNTER */ 83*4882a593Smuzhiyun #define OMAP5430_COUNTER_MASK (0xffffff << 0) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* OMAP5430.BANDGAP_THRESHOLD */ 86*4882a593Smuzhiyun #define OMAP5430_T_HOT_MASK (0x3ff << 16) 87*4882a593Smuzhiyun #define OMAP5430_T_COLD_MASK (0x3ff << 0) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* OMAP5430.TSHUT_THRESHOLD */ 90*4882a593Smuzhiyun #define OMAP5430_TSHUT_HOT_MASK (0x3ff << 16) 91*4882a593Smuzhiyun #define OMAP5430_TSHUT_COLD_MASK (0x3ff << 0) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* OMAP5430.BANDGAP_STATUS */ 94*4882a593Smuzhiyun #define OMAP5430_HOT_CORE_FLAG_MASK BIT(5) 95*4882a593Smuzhiyun #define OMAP5430_COLD_CORE_FLAG_MASK BIT(4) 96*4882a593Smuzhiyun #define OMAP5430_HOT_GPU_FLAG_MASK BIT(3) 97*4882a593Smuzhiyun #define OMAP5430_COLD_GPU_FLAG_MASK BIT(2) 98*4882a593Smuzhiyun #define OMAP5430_HOT_MPU_FLAG_MASK BIT(1) 99*4882a593Smuzhiyun #define OMAP5430_COLD_MPU_FLAG_MASK BIT(0) 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /** 102*4882a593Smuzhiyun * Temperature limits and thresholds for OMAP5430 103*4882a593Smuzhiyun * 104*4882a593Smuzhiyun * All the macros bellow are definitions for handling the 105*4882a593Smuzhiyun * ADC conversions and representation of temperature limits 106*4882a593Smuzhiyun * and thresholds for OMAP5430. Definitions are grouped 107*4882a593Smuzhiyun * by temperature domain. 108*4882a593Smuzhiyun */ 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* OMAP5430.common temperature definitions */ 111*4882a593Smuzhiyun /* ADC conversion table limits */ 112*4882a593Smuzhiyun #define OMAP5430_ADC_START_VALUE 540 113*4882a593Smuzhiyun #define OMAP5430_ADC_END_VALUE 945 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* OMAP5430.GPU temperature definitions */ 116*4882a593Smuzhiyun /* bandgap clock limits */ 117*4882a593Smuzhiyun #define OMAP5430_GPU_MAX_FREQ 1500000 118*4882a593Smuzhiyun #define OMAP5430_GPU_MIN_FREQ 1000000 119*4882a593Smuzhiyun /* interrupts thresholds */ 120*4882a593Smuzhiyun #define OMAP5430_GPU_TSHUT_HOT 915 121*4882a593Smuzhiyun #define OMAP5430_GPU_TSHUT_COLD 900 122*4882a593Smuzhiyun #define OMAP5430_GPU_T_HOT 800 123*4882a593Smuzhiyun #define OMAP5430_GPU_T_COLD 795 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun /* OMAP5430.MPU temperature definitions */ 126*4882a593Smuzhiyun /* bandgap clock limits */ 127*4882a593Smuzhiyun #define OMAP5430_MPU_MAX_FREQ 1500000 128*4882a593Smuzhiyun #define OMAP5430_MPU_MIN_FREQ 1000000 129*4882a593Smuzhiyun /* interrupts thresholds */ 130*4882a593Smuzhiyun #define OMAP5430_MPU_TSHUT_HOT 915 131*4882a593Smuzhiyun #define OMAP5430_MPU_TSHUT_COLD 900 132*4882a593Smuzhiyun #define OMAP5430_MPU_T_HOT 800 133*4882a593Smuzhiyun #define OMAP5430_MPU_T_COLD 795 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun /* OMAP5430.CORE temperature definitions */ 136*4882a593Smuzhiyun /* bandgap clock limits */ 137*4882a593Smuzhiyun #define OMAP5430_CORE_MAX_FREQ 1500000 138*4882a593Smuzhiyun #define OMAP5430_CORE_MIN_FREQ 1000000 139*4882a593Smuzhiyun /* interrupts thresholds */ 140*4882a593Smuzhiyun #define OMAP5430_CORE_TSHUT_HOT 915 141*4882a593Smuzhiyun #define OMAP5430_CORE_TSHUT_COLD 900 142*4882a593Smuzhiyun #define OMAP5430_CORE_T_HOT 800 143*4882a593Smuzhiyun #define OMAP5430_CORE_T_COLD 795 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun #endif /* __OMAP5XXX_BANDGAP_H */ 146