1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * OMAP4xxx bandgap registers, bitfields and temperature definitions 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 6*4882a593Smuzhiyun * Contact: 7*4882a593Smuzhiyun * Eduardo Valentin <eduardo.valentin@ti.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #ifndef __OMAP4XXX_BANDGAP_H 10*4882a593Smuzhiyun #define __OMAP4XXX_BANDGAP_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /** 13*4882a593Smuzhiyun * *** OMAP4430 *** 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * Below, in sequence, are the Register definitions, 16*4882a593Smuzhiyun * the bitfields and the temperature definitions for OMAP4430. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /** 20*4882a593Smuzhiyun * OMAP4430 register definitions 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * Registers are defined as offsets. The offsets are 23*4882a593Smuzhiyun * relative to FUSE_OPP_BGAP on 4430. 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* OMAP4430.FUSE_OPP_BGAP */ 27*4882a593Smuzhiyun #define OMAP4430_FUSE_OPP_BGAP 0x0 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* OMAP4430.TEMP_SENSOR */ 30*4882a593Smuzhiyun #define OMAP4430_TEMP_SENSOR_CTRL_OFFSET 0xCC 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /** 33*4882a593Smuzhiyun * Register and bit definitions for OMAP4430 34*4882a593Smuzhiyun * 35*4882a593Smuzhiyun * All the macros bellow define the required bits for 36*4882a593Smuzhiyun * controlling temperature on OMAP4430. Bit defines are 37*4882a593Smuzhiyun * grouped by register. 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* OMAP4430.TEMP_SENSOR bits */ 41*4882a593Smuzhiyun #define OMAP4430_BGAP_TEMPSOFF_MASK BIT(12) 42*4882a593Smuzhiyun #define OMAP4430_BGAP_TSHUT_MASK BIT(11) 43*4882a593Smuzhiyun #define OMAP4430_SINGLE_MODE_MASK BIT(10) 44*4882a593Smuzhiyun #define OMAP4430_BGAP_TEMP_SENSOR_SOC_MASK BIT(9) 45*4882a593Smuzhiyun #define OMAP4430_BGAP_TEMP_SENSOR_EOCZ_MASK BIT(8) 46*4882a593Smuzhiyun #define OMAP4430_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /** 49*4882a593Smuzhiyun * Temperature limits and thresholds for OMAP4430 50*4882a593Smuzhiyun * 51*4882a593Smuzhiyun * All the macros bellow are definitions for handling the 52*4882a593Smuzhiyun * ADC conversions and representation of temperature limits 53*4882a593Smuzhiyun * and thresholds for OMAP4430. 54*4882a593Smuzhiyun */ 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* 57*4882a593Smuzhiyun * ADC conversion table limits. Ignore values outside the TRM listed 58*4882a593Smuzhiyun * range to avoid bogus thermal shutdowns. See omap4430 TRM chapter 59*4882a593Smuzhiyun * "18.4.10.2.3 ADC Codes Versus Temperature". 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun #define OMAP4430_ADC_START_VALUE 13 62*4882a593Smuzhiyun #define OMAP4430_ADC_END_VALUE 107 63*4882a593Smuzhiyun /* bandgap clock limits (no control on 4430) */ 64*4882a593Smuzhiyun #define OMAP4430_MAX_FREQ 32768 65*4882a593Smuzhiyun #define OMAP4430_MIN_FREQ 32768 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /** 68*4882a593Smuzhiyun * *** OMAP4460 *** Applicable for OMAP4470 69*4882a593Smuzhiyun * 70*4882a593Smuzhiyun * Below, in sequence, are the Register definitions, 71*4882a593Smuzhiyun * the bitfields and the temperature definitions for OMAP4460. 72*4882a593Smuzhiyun */ 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /** 75*4882a593Smuzhiyun * OMAP4460 register definitions 76*4882a593Smuzhiyun * 77*4882a593Smuzhiyun * Registers are defined as offsets. The offsets are 78*4882a593Smuzhiyun * relative to FUSE_OPP_BGAP on 4460. 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* OMAP4460.FUSE_OPP_BGAP */ 82*4882a593Smuzhiyun #define OMAP4460_FUSE_OPP_BGAP 0x0 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* OMAP4460.TEMP_SENSOR */ 85*4882a593Smuzhiyun #define OMAP4460_TEMP_SENSOR_CTRL_OFFSET 0xCC 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* OMAP4460.BANDGAP_CTRL */ 88*4882a593Smuzhiyun #define OMAP4460_BGAP_CTRL_OFFSET 0x118 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* OMAP4460.BANDGAP_COUNTER */ 91*4882a593Smuzhiyun #define OMAP4460_BGAP_COUNTER_OFFSET 0x11C 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* OMAP4460.BANDGAP_THRESHOLD */ 94*4882a593Smuzhiyun #define OMAP4460_BGAP_THRESHOLD_OFFSET 0x120 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* OMAP4460.TSHUT_THRESHOLD */ 97*4882a593Smuzhiyun #define OMAP4460_BGAP_TSHUT_OFFSET 0x124 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* OMAP4460.BANDGAP_STATUS */ 100*4882a593Smuzhiyun #define OMAP4460_BGAP_STATUS_OFFSET 0x128 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /** 103*4882a593Smuzhiyun * Register bitfields for OMAP4460 104*4882a593Smuzhiyun * 105*4882a593Smuzhiyun * All the macros bellow define the required bits for 106*4882a593Smuzhiyun * controlling temperature on OMAP4460. Bit defines are 107*4882a593Smuzhiyun * grouped by register. 108*4882a593Smuzhiyun */ 109*4882a593Smuzhiyun /* OMAP4460.TEMP_SENSOR bits */ 110*4882a593Smuzhiyun #define OMAP4460_BGAP_TEMPSOFF_MASK BIT(13) 111*4882a593Smuzhiyun #define OMAP4460_BGAP_TEMP_SENSOR_SOC_MASK BIT(11) 112*4882a593Smuzhiyun #define OMAP4460_BGAP_TEMP_SENSOR_EOCZ_MASK BIT(10) 113*4882a593Smuzhiyun #define OMAP4460_BGAP_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0) 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* OMAP4460.BANDGAP_CTRL bits */ 116*4882a593Smuzhiyun #define OMAP4460_SINGLE_MODE_MASK BIT(31) 117*4882a593Smuzhiyun #define OMAP4460_MASK_HOT_MASK BIT(1) 118*4882a593Smuzhiyun #define OMAP4460_MASK_COLD_MASK BIT(0) 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* OMAP4460.BANDGAP_COUNTER bits */ 121*4882a593Smuzhiyun #define OMAP4460_COUNTER_MASK (0xffffff << 0) 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun /* OMAP4460.BANDGAP_THRESHOLD bits */ 124*4882a593Smuzhiyun #define OMAP4460_T_HOT_MASK (0x3ff << 16) 125*4882a593Smuzhiyun #define OMAP4460_T_COLD_MASK (0x3ff << 0) 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun /* OMAP4460.TSHUT_THRESHOLD bits */ 128*4882a593Smuzhiyun #define OMAP4460_TSHUT_HOT_MASK (0x3ff << 16) 129*4882a593Smuzhiyun #define OMAP4460_TSHUT_COLD_MASK (0x3ff << 0) 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* OMAP4460.BANDGAP_STATUS bits */ 132*4882a593Smuzhiyun #define OMAP4460_HOT_FLAG_MASK BIT(1) 133*4882a593Smuzhiyun #define OMAP4460_COLD_FLAG_MASK BIT(0) 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun /** 136*4882a593Smuzhiyun * Temperature limits and thresholds for OMAP4460 137*4882a593Smuzhiyun * 138*4882a593Smuzhiyun * All the macros bellow are definitions for handling the 139*4882a593Smuzhiyun * ADC conversions and representation of temperature limits 140*4882a593Smuzhiyun * and thresholds for OMAP4460. 141*4882a593Smuzhiyun */ 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun /* ADC conversion table limits */ 144*4882a593Smuzhiyun #define OMAP4460_ADC_START_VALUE 530 145*4882a593Smuzhiyun #define OMAP4460_ADC_END_VALUE 932 146*4882a593Smuzhiyun /* bandgap clock limits */ 147*4882a593Smuzhiyun #define OMAP4460_MAX_FREQ 1500000 148*4882a593Smuzhiyun #define OMAP4460_MIN_FREQ 1000000 149*4882a593Smuzhiyun /* interrupts thresholds */ 150*4882a593Smuzhiyun #define OMAP4460_TSHUT_HOT 900 /* 122 deg C */ 151*4882a593Smuzhiyun #define OMAP4460_TSHUT_COLD 895 /* 100 deg C */ 152*4882a593Smuzhiyun #define OMAP4460_T_HOT 800 /* 73 deg C */ 153*4882a593Smuzhiyun #define OMAP4460_T_COLD 795 /* 71 deg C */ 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun #endif /* __OMAP4XXX_BANDGAP_H */ 156