1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * DRA752 bandgap registers, bitfields and temperature definitions 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 6*4882a593Smuzhiyun * Contact: 7*4882a593Smuzhiyun * Eduardo Valentin <eduardo.valentin@ti.com> 8*4882a593Smuzhiyun * Tero Kristo <t-kristo@ti.com> 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * This is an auto generated file. 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun #ifndef __DRA752_BANDGAP_H 13*4882a593Smuzhiyun #define __DRA752_BANDGAP_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /** 16*4882a593Smuzhiyun * *** DRA752 *** 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * Below, in sequence, are the Register definitions, 19*4882a593Smuzhiyun * the bitfields and the temperature definitions for DRA752. 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /** 23*4882a593Smuzhiyun * DRA752 register definitions 24*4882a593Smuzhiyun * 25*4882a593Smuzhiyun * Registers are defined as offsets. The offsets are 26*4882a593Smuzhiyun * relative to FUSE_OPP_BGAP_GPU on DRA752. 27*4882a593Smuzhiyun * DRA752_BANDGAP_BASE 0x4a0021e0 28*4882a593Smuzhiyun * 29*4882a593Smuzhiyun * Register below are grouped by domain (not necessarily in offset order) 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* DRA752.common register offsets */ 34*4882a593Smuzhiyun #define DRA752_BANDGAP_CTRL_1_OFFSET 0x1a0 35*4882a593Smuzhiyun #define DRA752_BANDGAP_STATUS_1_OFFSET 0x1c8 36*4882a593Smuzhiyun #define DRA752_BANDGAP_CTRL_2_OFFSET 0x39c 37*4882a593Smuzhiyun #define DRA752_BANDGAP_STATUS_2_OFFSET 0x3b8 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* DRA752.core register offsets */ 40*4882a593Smuzhiyun #define DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET 0x8 41*4882a593Smuzhiyun #define DRA752_TEMP_SENSOR_CORE_OFFSET 0x154 42*4882a593Smuzhiyun #define DRA752_BANDGAP_THRESHOLD_CORE_OFFSET 0x1ac 43*4882a593Smuzhiyun #define DRA752_DTEMP_CORE_1_OFFSET 0x20c 44*4882a593Smuzhiyun #define DRA752_DTEMP_CORE_2_OFFSET 0x210 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* DRA752.iva register offsets */ 47*4882a593Smuzhiyun #define DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET 0x388 48*4882a593Smuzhiyun #define DRA752_TEMP_SENSOR_IVA_OFFSET 0x398 49*4882a593Smuzhiyun #define DRA752_BANDGAP_THRESHOLD_IVA_OFFSET 0x3a4 50*4882a593Smuzhiyun #define DRA752_DTEMP_IVA_1_OFFSET 0x3d4 51*4882a593Smuzhiyun #define DRA752_DTEMP_IVA_2_OFFSET 0x3d8 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* DRA752.mpu register offsets */ 54*4882a593Smuzhiyun #define DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET 0x4 55*4882a593Smuzhiyun #define DRA752_TEMP_SENSOR_MPU_OFFSET 0x14c 56*4882a593Smuzhiyun #define DRA752_BANDGAP_THRESHOLD_MPU_OFFSET 0x1a4 57*4882a593Smuzhiyun #define DRA752_DTEMP_MPU_1_OFFSET 0x1e4 58*4882a593Smuzhiyun #define DRA752_DTEMP_MPU_2_OFFSET 0x1e8 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* DRA752.dspeve register offsets */ 61*4882a593Smuzhiyun #define DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET 0x384 62*4882a593Smuzhiyun #define DRA752_TEMP_SENSOR_DSPEVE_OFFSET 0x394 63*4882a593Smuzhiyun #define DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET 0x3a0 64*4882a593Smuzhiyun #define DRA752_DTEMP_DSPEVE_1_OFFSET 0x3c0 65*4882a593Smuzhiyun #define DRA752_DTEMP_DSPEVE_2_OFFSET 0x3c4 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* DRA752.gpu register offsets */ 68*4882a593Smuzhiyun #define DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET 0x0 69*4882a593Smuzhiyun #define DRA752_TEMP_SENSOR_GPU_OFFSET 0x150 70*4882a593Smuzhiyun #define DRA752_BANDGAP_THRESHOLD_GPU_OFFSET 0x1a8 71*4882a593Smuzhiyun #define DRA752_DTEMP_GPU_1_OFFSET 0x1f8 72*4882a593Smuzhiyun #define DRA752_DTEMP_GPU_2_OFFSET 0x1fc 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /** 75*4882a593Smuzhiyun * Register bitfields for DRA752 76*4882a593Smuzhiyun * 77*4882a593Smuzhiyun * All the macros bellow define the required bits for 78*4882a593Smuzhiyun * controlling temperature on DRA752. Bit defines are 79*4882a593Smuzhiyun * grouped by register. 80*4882a593Smuzhiyun */ 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* DRA752.BANDGAP_STATUS_1 */ 83*4882a593Smuzhiyun #define DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK BIT(5) 84*4882a593Smuzhiyun #define DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK BIT(4) 85*4882a593Smuzhiyun #define DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK BIT(3) 86*4882a593Smuzhiyun #define DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK BIT(2) 87*4882a593Smuzhiyun #define DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK BIT(1) 88*4882a593Smuzhiyun #define DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK BIT(0) 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* DRA752.BANDGAP_CTRL_2 */ 91*4882a593Smuzhiyun #define DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK BIT(22) 92*4882a593Smuzhiyun #define DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK BIT(21) 93*4882a593Smuzhiyun #define DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK BIT(3) 94*4882a593Smuzhiyun #define DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK BIT(2) 95*4882a593Smuzhiyun #define DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK BIT(1) 96*4882a593Smuzhiyun #define DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK BIT(0) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* DRA752.BANDGAP_STATUS_2 */ 99*4882a593Smuzhiyun #define DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK BIT(3) 100*4882a593Smuzhiyun #define DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK BIT(2) 101*4882a593Smuzhiyun #define DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK BIT(1) 102*4882a593Smuzhiyun #define DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK BIT(0) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* DRA752.BANDGAP_CTRL_1 */ 105*4882a593Smuzhiyun #define DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK (0x7 << 27) 106*4882a593Smuzhiyun #define DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK BIT(23) 107*4882a593Smuzhiyun #define DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK BIT(22) 108*4882a593Smuzhiyun #define DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK BIT(21) 109*4882a593Smuzhiyun #define DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK BIT(5) 110*4882a593Smuzhiyun #define DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK BIT(4) 111*4882a593Smuzhiyun #define DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK BIT(3) 112*4882a593Smuzhiyun #define DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK BIT(2) 113*4882a593Smuzhiyun #define DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK BIT(1) 114*4882a593Smuzhiyun #define DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK BIT(0) 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun /* DRA752.TEMP_SENSOR */ 117*4882a593Smuzhiyun #define DRA752_TEMP_SENSOR_TMPSOFF_MASK BIT(11) 118*4882a593Smuzhiyun #define DRA752_TEMP_SENSOR_EOCZ_MASK BIT(10) 119*4882a593Smuzhiyun #define DRA752_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0) 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* DRA752.BANDGAP_THRESHOLD */ 122*4882a593Smuzhiyun #define DRA752_BANDGAP_THRESHOLD_HOT_MASK (0x3ff << 16) 123*4882a593Smuzhiyun #define DRA752_BANDGAP_THRESHOLD_COLD_MASK (0x3ff << 0) 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun /** 126*4882a593Smuzhiyun * Temperature limits and thresholds for DRA752 127*4882a593Smuzhiyun * 128*4882a593Smuzhiyun * All the macros bellow are definitions for handling the 129*4882a593Smuzhiyun * ADC conversions and representation of temperature limits 130*4882a593Smuzhiyun * and thresholds for DRA752. Definitions are grouped 131*4882a593Smuzhiyun * by temperature domain. 132*4882a593Smuzhiyun */ 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun /* DRA752.common temperature definitions */ 135*4882a593Smuzhiyun /* ADC conversion table limits */ 136*4882a593Smuzhiyun #define DRA752_ADC_START_VALUE 540 137*4882a593Smuzhiyun #define DRA752_ADC_END_VALUE 945 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun /* DRA752.GPU temperature definitions */ 140*4882a593Smuzhiyun /* bandgap clock limits */ 141*4882a593Smuzhiyun #define DRA752_GPU_MAX_FREQ 1500000 142*4882a593Smuzhiyun #define DRA752_GPU_MIN_FREQ 1000000 143*4882a593Smuzhiyun /* interrupts thresholds */ 144*4882a593Smuzhiyun #define DRA752_GPU_T_HOT 800 145*4882a593Smuzhiyun #define DRA752_GPU_T_COLD 795 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun /* DRA752.MPU temperature definitions */ 148*4882a593Smuzhiyun /* bandgap clock limits */ 149*4882a593Smuzhiyun #define DRA752_MPU_MAX_FREQ 1500000 150*4882a593Smuzhiyun #define DRA752_MPU_MIN_FREQ 1000000 151*4882a593Smuzhiyun /* interrupts thresholds */ 152*4882a593Smuzhiyun #define DRA752_MPU_T_HOT 800 153*4882a593Smuzhiyun #define DRA752_MPU_T_COLD 795 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun /* DRA752.CORE temperature definitions */ 156*4882a593Smuzhiyun /* bandgap clock limits */ 157*4882a593Smuzhiyun #define DRA752_CORE_MAX_FREQ 1500000 158*4882a593Smuzhiyun #define DRA752_CORE_MIN_FREQ 1000000 159*4882a593Smuzhiyun /* interrupts thresholds */ 160*4882a593Smuzhiyun #define DRA752_CORE_T_HOT 800 161*4882a593Smuzhiyun #define DRA752_CORE_T_COLD 795 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun /* DRA752.DSPEVE temperature definitions */ 164*4882a593Smuzhiyun /* bandgap clock limits */ 165*4882a593Smuzhiyun #define DRA752_DSPEVE_MAX_FREQ 1500000 166*4882a593Smuzhiyun #define DRA752_DSPEVE_MIN_FREQ 1000000 167*4882a593Smuzhiyun /* interrupts thresholds */ 168*4882a593Smuzhiyun #define DRA752_DSPEVE_T_HOT 800 169*4882a593Smuzhiyun #define DRA752_DSPEVE_T_COLD 795 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun /* DRA752.IVA temperature definitions */ 172*4882a593Smuzhiyun /* bandgap clock limits */ 173*4882a593Smuzhiyun #define DRA752_IVA_MAX_FREQ 1500000 174*4882a593Smuzhiyun #define DRA752_IVA_MIN_FREQ 1000000 175*4882a593Smuzhiyun /* interrupts thresholds */ 176*4882a593Smuzhiyun #define DRA752_IVA_T_HOT 800 177*4882a593Smuzhiyun #define DRA752_IVA_T_COLD 795 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun #endif /* __DRA752_BANDGAP_H */ 180