1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2019, Linaro Limited
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/bitops.h>
7*4882a593Smuzhiyun #include <linux/regmap.h>
8*4882a593Smuzhiyun #include <linux/delay.h>
9*4882a593Smuzhiyun #include <linux/slab.h>
10*4882a593Smuzhiyun #include "tsens.h"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun /* ----- SROT ------ */
13*4882a593Smuzhiyun #define SROT_HW_VER_OFF 0x0000
14*4882a593Smuzhiyun #define SROT_CTRL_OFF 0x0004
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /* ----- TM ------ */
17*4882a593Smuzhiyun #define TM_INT_EN_OFF 0x0000
18*4882a593Smuzhiyun #define TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF 0x0004
19*4882a593Smuzhiyun #define TM_Sn_STATUS_OFF 0x0044
20*4882a593Smuzhiyun #define TM_TRDY_OFF 0x0084
21*4882a593Smuzhiyun #define TM_HIGH_LOW_INT_STATUS_OFF 0x0088
22*4882a593Smuzhiyun #define TM_HIGH_LOW_Sn_INT_THRESHOLD_OFF 0x0090
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* eeprom layout data for msm8956/76 (v1) */
25*4882a593Smuzhiyun #define MSM8976_BASE0_MASK 0xff
26*4882a593Smuzhiyun #define MSM8976_BASE1_MASK 0xff
27*4882a593Smuzhiyun #define MSM8976_BASE1_SHIFT 8
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define MSM8976_S0_P1_MASK 0x3f00
30*4882a593Smuzhiyun #define MSM8976_S1_P1_MASK 0x3f00000
31*4882a593Smuzhiyun #define MSM8976_S2_P1_MASK 0x3f
32*4882a593Smuzhiyun #define MSM8976_S3_P1_MASK 0x3f000
33*4882a593Smuzhiyun #define MSM8976_S4_P1_MASK 0x3f00
34*4882a593Smuzhiyun #define MSM8976_S5_P1_MASK 0x3f00000
35*4882a593Smuzhiyun #define MSM8976_S6_P1_MASK 0x3f
36*4882a593Smuzhiyun #define MSM8976_S7_P1_MASK 0x3f000
37*4882a593Smuzhiyun #define MSM8976_S8_P1_MASK 0x1f8
38*4882a593Smuzhiyun #define MSM8976_S9_P1_MASK 0x1f8000
39*4882a593Smuzhiyun #define MSM8976_S10_P1_MASK 0xf8000000
40*4882a593Smuzhiyun #define MSM8976_S10_P1_MASK_1 0x1
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define MSM8976_S0_P2_MASK 0xfc000
43*4882a593Smuzhiyun #define MSM8976_S1_P2_MASK 0xfc000000
44*4882a593Smuzhiyun #define MSM8976_S2_P2_MASK 0xfc0
45*4882a593Smuzhiyun #define MSM8976_S3_P2_MASK 0xfc0000
46*4882a593Smuzhiyun #define MSM8976_S4_P2_MASK 0xfc000
47*4882a593Smuzhiyun #define MSM8976_S5_P2_MASK 0xfc000000
48*4882a593Smuzhiyun #define MSM8976_S6_P2_MASK 0xfc0
49*4882a593Smuzhiyun #define MSM8976_S7_P2_MASK 0xfc0000
50*4882a593Smuzhiyun #define MSM8976_S8_P2_MASK 0x7e00
51*4882a593Smuzhiyun #define MSM8976_S9_P2_MASK 0x7e00000
52*4882a593Smuzhiyun #define MSM8976_S10_P2_MASK 0x7e
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #define MSM8976_S0_P1_SHIFT 8
55*4882a593Smuzhiyun #define MSM8976_S1_P1_SHIFT 20
56*4882a593Smuzhiyun #define MSM8976_S2_P1_SHIFT 0
57*4882a593Smuzhiyun #define MSM8976_S3_P1_SHIFT 12
58*4882a593Smuzhiyun #define MSM8976_S4_P1_SHIFT 8
59*4882a593Smuzhiyun #define MSM8976_S5_P1_SHIFT 20
60*4882a593Smuzhiyun #define MSM8976_S6_P1_SHIFT 0
61*4882a593Smuzhiyun #define MSM8976_S7_P1_SHIFT 12
62*4882a593Smuzhiyun #define MSM8976_S8_P1_SHIFT 3
63*4882a593Smuzhiyun #define MSM8976_S9_P1_SHIFT 15
64*4882a593Smuzhiyun #define MSM8976_S10_P1_SHIFT 27
65*4882a593Smuzhiyun #define MSM8976_S10_P1_SHIFT_1 0
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #define MSM8976_S0_P2_SHIFT 14
68*4882a593Smuzhiyun #define MSM8976_S1_P2_SHIFT 26
69*4882a593Smuzhiyun #define MSM8976_S2_P2_SHIFT 6
70*4882a593Smuzhiyun #define MSM8976_S3_P2_SHIFT 18
71*4882a593Smuzhiyun #define MSM8976_S4_P2_SHIFT 14
72*4882a593Smuzhiyun #define MSM8976_S5_P2_SHIFT 26
73*4882a593Smuzhiyun #define MSM8976_S6_P2_SHIFT 6
74*4882a593Smuzhiyun #define MSM8976_S7_P2_SHIFT 18
75*4882a593Smuzhiyun #define MSM8976_S8_P2_SHIFT 9
76*4882a593Smuzhiyun #define MSM8976_S9_P2_SHIFT 21
77*4882a593Smuzhiyun #define MSM8976_S10_P2_SHIFT 1
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun #define MSM8976_CAL_SEL_MASK 0x3
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun #define MSM8976_CAL_DEGC_PT1 30
82*4882a593Smuzhiyun #define MSM8976_CAL_DEGC_PT2 120
83*4882a593Smuzhiyun #define MSM8976_SLOPE_FACTOR 1000
84*4882a593Smuzhiyun #define MSM8976_SLOPE_DEFAULT 3200
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /* eeprom layout data for qcs404/405 (v1) */
87*4882a593Smuzhiyun #define BASE0_MASK 0x000007f8
88*4882a593Smuzhiyun #define BASE1_MASK 0x0007f800
89*4882a593Smuzhiyun #define BASE0_SHIFT 3
90*4882a593Smuzhiyun #define BASE1_SHIFT 11
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun #define S0_P1_MASK 0x0000003f
93*4882a593Smuzhiyun #define S1_P1_MASK 0x0003f000
94*4882a593Smuzhiyun #define S2_P1_MASK 0x3f000000
95*4882a593Smuzhiyun #define S3_P1_MASK 0x000003f0
96*4882a593Smuzhiyun #define S4_P1_MASK 0x003f0000
97*4882a593Smuzhiyun #define S5_P1_MASK 0x0000003f
98*4882a593Smuzhiyun #define S6_P1_MASK 0x0003f000
99*4882a593Smuzhiyun #define S7_P1_MASK 0x3f000000
100*4882a593Smuzhiyun #define S8_P1_MASK 0x000003f0
101*4882a593Smuzhiyun #define S9_P1_MASK 0x003f0000
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun #define S0_P2_MASK 0x00000fc0
104*4882a593Smuzhiyun #define S1_P2_MASK 0x00fc0000
105*4882a593Smuzhiyun #define S2_P2_MASK_1_0 0xc0000000
106*4882a593Smuzhiyun #define S2_P2_MASK_5_2 0x0000000f
107*4882a593Smuzhiyun #define S3_P2_MASK 0x0000fc00
108*4882a593Smuzhiyun #define S4_P2_MASK 0x0fc00000
109*4882a593Smuzhiyun #define S5_P2_MASK 0x00000fc0
110*4882a593Smuzhiyun #define S6_P2_MASK 0x00fc0000
111*4882a593Smuzhiyun #define S7_P2_MASK_1_0 0xc0000000
112*4882a593Smuzhiyun #define S7_P2_MASK_5_2 0x0000000f
113*4882a593Smuzhiyun #define S8_P2_MASK 0x0000fc00
114*4882a593Smuzhiyun #define S9_P2_MASK 0x0fc00000
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun #define S0_P1_SHIFT 0
117*4882a593Smuzhiyun #define S0_P2_SHIFT 6
118*4882a593Smuzhiyun #define S1_P1_SHIFT 12
119*4882a593Smuzhiyun #define S1_P2_SHIFT 18
120*4882a593Smuzhiyun #define S2_P1_SHIFT 24
121*4882a593Smuzhiyun #define S2_P2_SHIFT_1_0 30
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun #define S2_P2_SHIFT_5_2 0
124*4882a593Smuzhiyun #define S3_P1_SHIFT 4
125*4882a593Smuzhiyun #define S3_P2_SHIFT 10
126*4882a593Smuzhiyun #define S4_P1_SHIFT 16
127*4882a593Smuzhiyun #define S4_P2_SHIFT 22
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun #define S5_P1_SHIFT 0
130*4882a593Smuzhiyun #define S5_P2_SHIFT 6
131*4882a593Smuzhiyun #define S6_P1_SHIFT 12
132*4882a593Smuzhiyun #define S6_P2_SHIFT 18
133*4882a593Smuzhiyun #define S7_P1_SHIFT 24
134*4882a593Smuzhiyun #define S7_P2_SHIFT_1_0 30
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun #define S7_P2_SHIFT_5_2 0
137*4882a593Smuzhiyun #define S8_P1_SHIFT 4
138*4882a593Smuzhiyun #define S8_P2_SHIFT 10
139*4882a593Smuzhiyun #define S9_P1_SHIFT 16
140*4882a593Smuzhiyun #define S9_P2_SHIFT 22
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun #define CAL_SEL_MASK 7
143*4882a593Smuzhiyun #define CAL_SEL_SHIFT 0
144*4882a593Smuzhiyun
compute_intercept_slope_8976(struct tsens_priv * priv,u32 * p1,u32 * p2,u32 mode)145*4882a593Smuzhiyun static void compute_intercept_slope_8976(struct tsens_priv *priv,
146*4882a593Smuzhiyun u32 *p1, u32 *p2, u32 mode)
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun int i;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun priv->sensor[0].slope = 3313;
151*4882a593Smuzhiyun priv->sensor[1].slope = 3275;
152*4882a593Smuzhiyun priv->sensor[2].slope = 3320;
153*4882a593Smuzhiyun priv->sensor[3].slope = 3246;
154*4882a593Smuzhiyun priv->sensor[4].slope = 3279;
155*4882a593Smuzhiyun priv->sensor[5].slope = 3257;
156*4882a593Smuzhiyun priv->sensor[6].slope = 3234;
157*4882a593Smuzhiyun priv->sensor[7].slope = 3269;
158*4882a593Smuzhiyun priv->sensor[8].slope = 3255;
159*4882a593Smuzhiyun priv->sensor[9].slope = 3239;
160*4882a593Smuzhiyun priv->sensor[10].slope = 3286;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun for (i = 0; i < priv->num_sensors; i++) {
163*4882a593Smuzhiyun priv->sensor[i].offset = (p1[i] * MSM8976_SLOPE_FACTOR) -
164*4882a593Smuzhiyun (MSM8976_CAL_DEGC_PT1 *
165*4882a593Smuzhiyun priv->sensor[i].slope);
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun
calibrate_v1(struct tsens_priv * priv)169*4882a593Smuzhiyun static int calibrate_v1(struct tsens_priv *priv)
170*4882a593Smuzhiyun {
171*4882a593Smuzhiyun u32 base0 = 0, base1 = 0;
172*4882a593Smuzhiyun u32 p1[10], p2[10];
173*4882a593Smuzhiyun u32 mode = 0, lsb = 0, msb = 0;
174*4882a593Smuzhiyun u32 *qfprom_cdata;
175*4882a593Smuzhiyun int i;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib");
178*4882a593Smuzhiyun if (IS_ERR(qfprom_cdata))
179*4882a593Smuzhiyun return PTR_ERR(qfprom_cdata);
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun mode = (qfprom_cdata[4] & CAL_SEL_MASK) >> CAL_SEL_SHIFT;
182*4882a593Smuzhiyun dev_dbg(priv->dev, "calibration mode is %d\n", mode);
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun switch (mode) {
185*4882a593Smuzhiyun case TWO_PT_CALIB:
186*4882a593Smuzhiyun base1 = (qfprom_cdata[4] & BASE1_MASK) >> BASE1_SHIFT;
187*4882a593Smuzhiyun p2[0] = (qfprom_cdata[0] & S0_P2_MASK) >> S0_P2_SHIFT;
188*4882a593Smuzhiyun p2[1] = (qfprom_cdata[0] & S1_P2_MASK) >> S1_P2_SHIFT;
189*4882a593Smuzhiyun /* This value is split over two registers, 2 bits and 4 bits */
190*4882a593Smuzhiyun lsb = (qfprom_cdata[0] & S2_P2_MASK_1_0) >> S2_P2_SHIFT_1_0;
191*4882a593Smuzhiyun msb = (qfprom_cdata[1] & S2_P2_MASK_5_2) >> S2_P2_SHIFT_5_2;
192*4882a593Smuzhiyun p2[2] = msb << 2 | lsb;
193*4882a593Smuzhiyun p2[3] = (qfprom_cdata[1] & S3_P2_MASK) >> S3_P2_SHIFT;
194*4882a593Smuzhiyun p2[4] = (qfprom_cdata[1] & S4_P2_MASK) >> S4_P2_SHIFT;
195*4882a593Smuzhiyun p2[5] = (qfprom_cdata[2] & S5_P2_MASK) >> S5_P2_SHIFT;
196*4882a593Smuzhiyun p2[6] = (qfprom_cdata[2] & S6_P2_MASK) >> S6_P2_SHIFT;
197*4882a593Smuzhiyun /* This value is split over two registers, 2 bits and 4 bits */
198*4882a593Smuzhiyun lsb = (qfprom_cdata[2] & S7_P2_MASK_1_0) >> S7_P2_SHIFT_1_0;
199*4882a593Smuzhiyun msb = (qfprom_cdata[3] & S7_P2_MASK_5_2) >> S7_P2_SHIFT_5_2;
200*4882a593Smuzhiyun p2[7] = msb << 2 | lsb;
201*4882a593Smuzhiyun p2[8] = (qfprom_cdata[3] & S8_P2_MASK) >> S8_P2_SHIFT;
202*4882a593Smuzhiyun p2[9] = (qfprom_cdata[3] & S9_P2_MASK) >> S9_P2_SHIFT;
203*4882a593Smuzhiyun for (i = 0; i < priv->num_sensors; i++)
204*4882a593Smuzhiyun p2[i] = ((base1 + p2[i]) << 2);
205*4882a593Smuzhiyun fallthrough;
206*4882a593Smuzhiyun case ONE_PT_CALIB2:
207*4882a593Smuzhiyun base0 = (qfprom_cdata[4] & BASE0_MASK) >> BASE0_SHIFT;
208*4882a593Smuzhiyun p1[0] = (qfprom_cdata[0] & S0_P1_MASK) >> S0_P1_SHIFT;
209*4882a593Smuzhiyun p1[1] = (qfprom_cdata[0] & S1_P1_MASK) >> S1_P1_SHIFT;
210*4882a593Smuzhiyun p1[2] = (qfprom_cdata[0] & S2_P1_MASK) >> S2_P1_SHIFT;
211*4882a593Smuzhiyun p1[3] = (qfprom_cdata[1] & S3_P1_MASK) >> S3_P1_SHIFT;
212*4882a593Smuzhiyun p1[4] = (qfprom_cdata[1] & S4_P1_MASK) >> S4_P1_SHIFT;
213*4882a593Smuzhiyun p1[5] = (qfprom_cdata[2] & S5_P1_MASK) >> S5_P1_SHIFT;
214*4882a593Smuzhiyun p1[6] = (qfprom_cdata[2] & S6_P1_MASK) >> S6_P1_SHIFT;
215*4882a593Smuzhiyun p1[7] = (qfprom_cdata[2] & S7_P1_MASK) >> S7_P1_SHIFT;
216*4882a593Smuzhiyun p1[8] = (qfprom_cdata[3] & S8_P1_MASK) >> S8_P1_SHIFT;
217*4882a593Smuzhiyun p1[9] = (qfprom_cdata[3] & S9_P1_MASK) >> S9_P1_SHIFT;
218*4882a593Smuzhiyun for (i = 0; i < priv->num_sensors; i++)
219*4882a593Smuzhiyun p1[i] = (((base0) + p1[i]) << 2);
220*4882a593Smuzhiyun break;
221*4882a593Smuzhiyun default:
222*4882a593Smuzhiyun for (i = 0; i < priv->num_sensors; i++) {
223*4882a593Smuzhiyun p1[i] = 500;
224*4882a593Smuzhiyun p2[i] = 780;
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun break;
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun compute_intercept_slope(priv, p1, p2, mode);
230*4882a593Smuzhiyun kfree(qfprom_cdata);
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun return 0;
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun
calibrate_8976(struct tsens_priv * priv)235*4882a593Smuzhiyun static int calibrate_8976(struct tsens_priv *priv)
236*4882a593Smuzhiyun {
237*4882a593Smuzhiyun int base0 = 0, base1 = 0, i;
238*4882a593Smuzhiyun u32 p1[11], p2[11];
239*4882a593Smuzhiyun int mode = 0, tmp = 0;
240*4882a593Smuzhiyun u32 *qfprom_cdata;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib");
243*4882a593Smuzhiyun if (IS_ERR(qfprom_cdata))
244*4882a593Smuzhiyun return PTR_ERR(qfprom_cdata);
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun mode = (qfprom_cdata[4] & MSM8976_CAL_SEL_MASK);
247*4882a593Smuzhiyun dev_dbg(priv->dev, "calibration mode is %d\n", mode);
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun switch (mode) {
250*4882a593Smuzhiyun case TWO_PT_CALIB:
251*4882a593Smuzhiyun base1 = (qfprom_cdata[2] & MSM8976_BASE1_MASK) >> MSM8976_BASE1_SHIFT;
252*4882a593Smuzhiyun p2[0] = (qfprom_cdata[0] & MSM8976_S0_P2_MASK) >> MSM8976_S0_P2_SHIFT;
253*4882a593Smuzhiyun p2[1] = (qfprom_cdata[0] & MSM8976_S1_P2_MASK) >> MSM8976_S1_P2_SHIFT;
254*4882a593Smuzhiyun p2[2] = (qfprom_cdata[1] & MSM8976_S2_P2_MASK) >> MSM8976_S2_P2_SHIFT;
255*4882a593Smuzhiyun p2[3] = (qfprom_cdata[1] & MSM8976_S3_P2_MASK) >> MSM8976_S3_P2_SHIFT;
256*4882a593Smuzhiyun p2[4] = (qfprom_cdata[2] & MSM8976_S4_P2_MASK) >> MSM8976_S4_P2_SHIFT;
257*4882a593Smuzhiyun p2[5] = (qfprom_cdata[2] & MSM8976_S5_P2_MASK) >> MSM8976_S5_P2_SHIFT;
258*4882a593Smuzhiyun p2[6] = (qfprom_cdata[3] & MSM8976_S6_P2_MASK) >> MSM8976_S6_P2_SHIFT;
259*4882a593Smuzhiyun p2[7] = (qfprom_cdata[3] & MSM8976_S7_P2_MASK) >> MSM8976_S7_P2_SHIFT;
260*4882a593Smuzhiyun p2[8] = (qfprom_cdata[4] & MSM8976_S8_P2_MASK) >> MSM8976_S8_P2_SHIFT;
261*4882a593Smuzhiyun p2[9] = (qfprom_cdata[4] & MSM8976_S9_P2_MASK) >> MSM8976_S9_P2_SHIFT;
262*4882a593Smuzhiyun p2[10] = (qfprom_cdata[5] & MSM8976_S10_P2_MASK) >> MSM8976_S10_P2_SHIFT;
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun for (i = 0; i < priv->num_sensors; i++)
265*4882a593Smuzhiyun p2[i] = ((base1 + p2[i]) << 2);
266*4882a593Smuzhiyun fallthrough;
267*4882a593Smuzhiyun case ONE_PT_CALIB2:
268*4882a593Smuzhiyun base0 = qfprom_cdata[0] & MSM8976_BASE0_MASK;
269*4882a593Smuzhiyun p1[0] = (qfprom_cdata[0] & MSM8976_S0_P1_MASK) >> MSM8976_S0_P1_SHIFT;
270*4882a593Smuzhiyun p1[1] = (qfprom_cdata[0] & MSM8976_S1_P1_MASK) >> MSM8976_S1_P1_SHIFT;
271*4882a593Smuzhiyun p1[2] = (qfprom_cdata[1] & MSM8976_S2_P1_MASK) >> MSM8976_S2_P1_SHIFT;
272*4882a593Smuzhiyun p1[3] = (qfprom_cdata[1] & MSM8976_S3_P1_MASK) >> MSM8976_S3_P1_SHIFT;
273*4882a593Smuzhiyun p1[4] = (qfprom_cdata[2] & MSM8976_S4_P1_MASK) >> MSM8976_S4_P1_SHIFT;
274*4882a593Smuzhiyun p1[5] = (qfprom_cdata[2] & MSM8976_S5_P1_MASK) >> MSM8976_S5_P1_SHIFT;
275*4882a593Smuzhiyun p1[6] = (qfprom_cdata[3] & MSM8976_S6_P1_MASK) >> MSM8976_S6_P1_SHIFT;
276*4882a593Smuzhiyun p1[7] = (qfprom_cdata[3] & MSM8976_S7_P1_MASK) >> MSM8976_S7_P1_SHIFT;
277*4882a593Smuzhiyun p1[8] = (qfprom_cdata[4] & MSM8976_S8_P1_MASK) >> MSM8976_S8_P1_SHIFT;
278*4882a593Smuzhiyun p1[9] = (qfprom_cdata[4] & MSM8976_S9_P1_MASK) >> MSM8976_S9_P1_SHIFT;
279*4882a593Smuzhiyun p1[10] = (qfprom_cdata[4] & MSM8976_S10_P1_MASK) >> MSM8976_S10_P1_SHIFT;
280*4882a593Smuzhiyun tmp = (qfprom_cdata[5] & MSM8976_S10_P1_MASK_1) << MSM8976_S10_P1_SHIFT_1;
281*4882a593Smuzhiyun p1[10] |= tmp;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun for (i = 0; i < priv->num_sensors; i++)
284*4882a593Smuzhiyun p1[i] = (((base0) + p1[i]) << 2);
285*4882a593Smuzhiyun break;
286*4882a593Smuzhiyun default:
287*4882a593Smuzhiyun for (i = 0; i < priv->num_sensors; i++) {
288*4882a593Smuzhiyun p1[i] = 500;
289*4882a593Smuzhiyun p2[i] = 780;
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun break;
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun compute_intercept_slope_8976(priv, p1, p2, mode);
295*4882a593Smuzhiyun kfree(qfprom_cdata);
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun return 0;
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun /* v1.x: msm8956,8976,qcs404,405 */
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun static struct tsens_features tsens_v1_feat = {
303*4882a593Smuzhiyun .ver_major = VER_1_X,
304*4882a593Smuzhiyun .crit_int = 0,
305*4882a593Smuzhiyun .adc = 1,
306*4882a593Smuzhiyun .srot_split = 1,
307*4882a593Smuzhiyun .max_sensors = 11,
308*4882a593Smuzhiyun };
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = {
311*4882a593Smuzhiyun /* ----- SROT ------ */
312*4882a593Smuzhiyun /* VERSION */
313*4882a593Smuzhiyun [VER_MAJOR] = REG_FIELD(SROT_HW_VER_OFF, 28, 31),
314*4882a593Smuzhiyun [VER_MINOR] = REG_FIELD(SROT_HW_VER_OFF, 16, 27),
315*4882a593Smuzhiyun [VER_STEP] = REG_FIELD(SROT_HW_VER_OFF, 0, 15),
316*4882a593Smuzhiyun /* CTRL_OFFSET */
317*4882a593Smuzhiyun [TSENS_EN] = REG_FIELD(SROT_CTRL_OFF, 0, 0),
318*4882a593Smuzhiyun [TSENS_SW_RST] = REG_FIELD(SROT_CTRL_OFF, 1, 1),
319*4882a593Smuzhiyun [SENSOR_EN] = REG_FIELD(SROT_CTRL_OFF, 3, 13),
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun /* ----- TM ------ */
322*4882a593Smuzhiyun /* INTERRUPT ENABLE */
323*4882a593Smuzhiyun [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 0),
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun /* UPPER/LOWER TEMPERATURE THRESHOLDS */
326*4882a593Smuzhiyun REG_FIELD_FOR_EACH_SENSOR11(LOW_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 0, 9),
327*4882a593Smuzhiyun REG_FIELD_FOR_EACH_SENSOR11(UP_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 10, 19),
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun /* UPPER/LOWER INTERRUPTS [CLEAR/STATUS] */
330*4882a593Smuzhiyun REG_FIELD_FOR_EACH_SENSOR11(LOW_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 20, 20),
331*4882a593Smuzhiyun REG_FIELD_FOR_EACH_SENSOR11(UP_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 21, 21),
332*4882a593Smuzhiyun [LOW_INT_STATUS_0] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 0, 0),
333*4882a593Smuzhiyun [LOW_INT_STATUS_1] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 1, 1),
334*4882a593Smuzhiyun [LOW_INT_STATUS_2] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 2, 2),
335*4882a593Smuzhiyun [LOW_INT_STATUS_3] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 3, 3),
336*4882a593Smuzhiyun [LOW_INT_STATUS_4] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 4, 4),
337*4882a593Smuzhiyun [LOW_INT_STATUS_5] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 5, 5),
338*4882a593Smuzhiyun [LOW_INT_STATUS_6] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 6, 6),
339*4882a593Smuzhiyun [LOW_INT_STATUS_7] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 7, 7),
340*4882a593Smuzhiyun [UP_INT_STATUS_0] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 8, 8),
341*4882a593Smuzhiyun [UP_INT_STATUS_1] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 9, 9),
342*4882a593Smuzhiyun [UP_INT_STATUS_2] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 10, 10),
343*4882a593Smuzhiyun [UP_INT_STATUS_3] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 11, 11),
344*4882a593Smuzhiyun [UP_INT_STATUS_4] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 12, 12),
345*4882a593Smuzhiyun [UP_INT_STATUS_5] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 13, 13),
346*4882a593Smuzhiyun [UP_INT_STATUS_6] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 14, 14),
347*4882a593Smuzhiyun [UP_INT_STATUS_7] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 15, 15),
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun /* NO CRITICAL INTERRUPT SUPPORT on v1 */
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun /* Sn_STATUS */
352*4882a593Smuzhiyun REG_FIELD_FOR_EACH_SENSOR11(LAST_TEMP, TM_Sn_STATUS_OFF, 0, 9),
353*4882a593Smuzhiyun REG_FIELD_FOR_EACH_SENSOR11(VALID, TM_Sn_STATUS_OFF, 14, 14),
354*4882a593Smuzhiyun /* xxx_STATUS bits: 1 == threshold violated */
355*4882a593Smuzhiyun REG_FIELD_FOR_EACH_SENSOR11(MIN_STATUS, TM_Sn_STATUS_OFF, 10, 10),
356*4882a593Smuzhiyun REG_FIELD_FOR_EACH_SENSOR11(LOWER_STATUS, TM_Sn_STATUS_OFF, 11, 11),
357*4882a593Smuzhiyun REG_FIELD_FOR_EACH_SENSOR11(UPPER_STATUS, TM_Sn_STATUS_OFF, 12, 12),
358*4882a593Smuzhiyun /* No CRITICAL field on v1.x */
359*4882a593Smuzhiyun REG_FIELD_FOR_EACH_SENSOR11(MAX_STATUS, TM_Sn_STATUS_OFF, 13, 13),
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun /* TRDY: 1=ready, 0=in progress */
362*4882a593Smuzhiyun [TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0),
363*4882a593Smuzhiyun };
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun static const struct tsens_ops ops_generic_v1 = {
366*4882a593Smuzhiyun .init = init_common,
367*4882a593Smuzhiyun .calibrate = calibrate_v1,
368*4882a593Smuzhiyun .get_temp = get_temp_tsens_valid,
369*4882a593Smuzhiyun };
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun struct tsens_plat_data data_tsens_v1 = {
372*4882a593Smuzhiyun .ops = &ops_generic_v1,
373*4882a593Smuzhiyun .feat = &tsens_v1_feat,
374*4882a593Smuzhiyun .fields = tsens_v1_regfields,
375*4882a593Smuzhiyun };
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun static const struct tsens_ops ops_8976 = {
378*4882a593Smuzhiyun .init = init_common,
379*4882a593Smuzhiyun .calibrate = calibrate_8976,
380*4882a593Smuzhiyun .get_temp = get_temp_tsens_valid,
381*4882a593Smuzhiyun };
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun /* Valid for both MSM8956 and MSM8976. Sensor ID 3 is unused. */
384*4882a593Smuzhiyun struct tsens_plat_data data_8976 = {
385*4882a593Smuzhiyun .num_sensors = 11,
386*4882a593Smuzhiyun .ops = &ops_8976,
387*4882a593Smuzhiyun .hw_ids = (unsigned int[]){0, 1, 2, 4, 5, 6, 7, 8, 9, 10},
388*4882a593Smuzhiyun .feat = &tsens_v1_feat,
389*4882a593Smuzhiyun .fields = tsens_v1_regfields,
390*4882a593Smuzhiyun };
391