1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/platform_device.h>
7*4882a593Smuzhiyun #include "tsens.h"
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun /* ----- SROT ------ */
10*4882a593Smuzhiyun #define SROT_CTRL_OFF 0x0000
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun /* ----- TM ------ */
13*4882a593Smuzhiyun #define TM_INT_EN_OFF 0x0000
14*4882a593Smuzhiyun #define TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF 0x0004
15*4882a593Smuzhiyun #define TM_Sn_STATUS_OFF 0x0030
16*4882a593Smuzhiyun #define TM_TRDY_OFF 0x005c
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /* eeprom layout data for 8916 */
19*4882a593Smuzhiyun #define MSM8916_BASE0_MASK 0x0000007f
20*4882a593Smuzhiyun #define MSM8916_BASE1_MASK 0xfe000000
21*4882a593Smuzhiyun #define MSM8916_BASE0_SHIFT 0
22*4882a593Smuzhiyun #define MSM8916_BASE1_SHIFT 25
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define MSM8916_S0_P1_MASK 0x00000f80
25*4882a593Smuzhiyun #define MSM8916_S1_P1_MASK 0x003e0000
26*4882a593Smuzhiyun #define MSM8916_S2_P1_MASK 0xf8000000
27*4882a593Smuzhiyun #define MSM8916_S3_P1_MASK 0x000003e0
28*4882a593Smuzhiyun #define MSM8916_S4_P1_MASK 0x000f8000
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define MSM8916_S0_P2_MASK 0x0001f000
31*4882a593Smuzhiyun #define MSM8916_S1_P2_MASK 0x07c00000
32*4882a593Smuzhiyun #define MSM8916_S2_P2_MASK 0x0000001f
33*4882a593Smuzhiyun #define MSM8916_S3_P2_MASK 0x00007c00
34*4882a593Smuzhiyun #define MSM8916_S4_P2_MASK 0x01f00000
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define MSM8916_S0_P1_SHIFT 7
37*4882a593Smuzhiyun #define MSM8916_S1_P1_SHIFT 17
38*4882a593Smuzhiyun #define MSM8916_S2_P1_SHIFT 27
39*4882a593Smuzhiyun #define MSM8916_S3_P1_SHIFT 5
40*4882a593Smuzhiyun #define MSM8916_S4_P1_SHIFT 15
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define MSM8916_S0_P2_SHIFT 12
43*4882a593Smuzhiyun #define MSM8916_S1_P2_SHIFT 22
44*4882a593Smuzhiyun #define MSM8916_S2_P2_SHIFT 0
45*4882a593Smuzhiyun #define MSM8916_S3_P2_SHIFT 10
46*4882a593Smuzhiyun #define MSM8916_S4_P2_SHIFT 20
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #define MSM8916_CAL_SEL_MASK 0xe0000000
49*4882a593Smuzhiyun #define MSM8916_CAL_SEL_SHIFT 29
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /* eeprom layout data for 8939 */
52*4882a593Smuzhiyun #define MSM8939_BASE0_MASK 0x000000ff
53*4882a593Smuzhiyun #define MSM8939_BASE1_MASK 0xff000000
54*4882a593Smuzhiyun #define MSM8939_BASE0_SHIFT 0
55*4882a593Smuzhiyun #define MSM8939_BASE1_SHIFT 24
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #define MSM8939_S0_P1_MASK 0x000001f8
58*4882a593Smuzhiyun #define MSM8939_S1_P1_MASK 0x001f8000
59*4882a593Smuzhiyun #define MSM8939_S2_P1_MASK_0_4 0xf8000000
60*4882a593Smuzhiyun #define MSM8939_S2_P1_MASK_5 0x00000001
61*4882a593Smuzhiyun #define MSM8939_S3_P1_MASK 0x00001f80
62*4882a593Smuzhiyun #define MSM8939_S4_P1_MASK 0x01f80000
63*4882a593Smuzhiyun #define MSM8939_S5_P1_MASK 0x00003f00
64*4882a593Smuzhiyun #define MSM8939_S6_P1_MASK 0x03f00000
65*4882a593Smuzhiyun #define MSM8939_S7_P1_MASK 0x0000003f
66*4882a593Smuzhiyun #define MSM8939_S8_P1_MASK 0x0003f000
67*4882a593Smuzhiyun #define MSM8939_S9_P1_MASK 0x07e00000
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun #define MSM8939_S0_P2_MASK 0x00007e00
70*4882a593Smuzhiyun #define MSM8939_S1_P2_MASK 0x07e00000
71*4882a593Smuzhiyun #define MSM8939_S2_P2_MASK 0x0000007e
72*4882a593Smuzhiyun #define MSM8939_S3_P2_MASK 0x0007e000
73*4882a593Smuzhiyun #define MSM8939_S4_P2_MASK 0x7e000000
74*4882a593Smuzhiyun #define MSM8939_S5_P2_MASK 0x000fc000
75*4882a593Smuzhiyun #define MSM8939_S6_P2_MASK 0xfc000000
76*4882a593Smuzhiyun #define MSM8939_S7_P2_MASK 0x00000fc0
77*4882a593Smuzhiyun #define MSM8939_S8_P2_MASK 0x00fc0000
78*4882a593Smuzhiyun #define MSM8939_S9_P2_MASK_0_4 0xf8000000
79*4882a593Smuzhiyun #define MSM8939_S9_P2_MASK_5 0x00002000
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun #define MSM8939_S0_P1_SHIFT 3
82*4882a593Smuzhiyun #define MSM8939_S1_P1_SHIFT 15
83*4882a593Smuzhiyun #define MSM8939_S2_P1_SHIFT_0_4 27
84*4882a593Smuzhiyun #define MSM8939_S2_P1_SHIFT_5 0
85*4882a593Smuzhiyun #define MSM8939_S3_P1_SHIFT 7
86*4882a593Smuzhiyun #define MSM8939_S4_P1_SHIFT 19
87*4882a593Smuzhiyun #define MSM8939_S5_P1_SHIFT 8
88*4882a593Smuzhiyun #define MSM8939_S6_P1_SHIFT 20
89*4882a593Smuzhiyun #define MSM8939_S7_P1_SHIFT 0
90*4882a593Smuzhiyun #define MSM8939_S8_P1_SHIFT 12
91*4882a593Smuzhiyun #define MSM8939_S9_P1_SHIFT 21
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun #define MSM8939_S0_P2_SHIFT 9
94*4882a593Smuzhiyun #define MSM8939_S1_P2_SHIFT 21
95*4882a593Smuzhiyun #define MSM8939_S2_P2_SHIFT 1
96*4882a593Smuzhiyun #define MSM8939_S3_P2_SHIFT 13
97*4882a593Smuzhiyun #define MSM8939_S4_P2_SHIFT 25
98*4882a593Smuzhiyun #define MSM8939_S5_P2_SHIFT 14
99*4882a593Smuzhiyun #define MSM8939_S6_P2_SHIFT 26
100*4882a593Smuzhiyun #define MSM8939_S7_P2_SHIFT 6
101*4882a593Smuzhiyun #define MSM8939_S8_P2_SHIFT 18
102*4882a593Smuzhiyun #define MSM8939_S9_P2_SHIFT_0_4 27
103*4882a593Smuzhiyun #define MSM8939_S9_P2_SHIFT_5 13
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun #define MSM8939_CAL_SEL_MASK 0x7
106*4882a593Smuzhiyun #define MSM8939_CAL_SEL_SHIFT 0
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /* eeprom layout data for 8974 */
109*4882a593Smuzhiyun #define BASE1_MASK 0xff
110*4882a593Smuzhiyun #define S0_P1_MASK 0x3f00
111*4882a593Smuzhiyun #define S1_P1_MASK 0xfc000
112*4882a593Smuzhiyun #define S2_P1_MASK 0x3f00000
113*4882a593Smuzhiyun #define S3_P1_MASK 0xfc000000
114*4882a593Smuzhiyun #define S4_P1_MASK 0x3f
115*4882a593Smuzhiyun #define S5_P1_MASK 0xfc0
116*4882a593Smuzhiyun #define S6_P1_MASK 0x3f000
117*4882a593Smuzhiyun #define S7_P1_MASK 0xfc0000
118*4882a593Smuzhiyun #define S8_P1_MASK 0x3f000000
119*4882a593Smuzhiyun #define S8_P1_MASK_BKP 0x3f
120*4882a593Smuzhiyun #define S9_P1_MASK 0x3f
121*4882a593Smuzhiyun #define S9_P1_MASK_BKP 0xfc0
122*4882a593Smuzhiyun #define S10_P1_MASK 0xfc0
123*4882a593Smuzhiyun #define S10_P1_MASK_BKP 0x3f000
124*4882a593Smuzhiyun #define CAL_SEL_0_1 0xc0000000
125*4882a593Smuzhiyun #define CAL_SEL_2 0x40000000
126*4882a593Smuzhiyun #define CAL_SEL_SHIFT 30
127*4882a593Smuzhiyun #define CAL_SEL_SHIFT_2 28
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun #define S0_P1_SHIFT 8
130*4882a593Smuzhiyun #define S1_P1_SHIFT 14
131*4882a593Smuzhiyun #define S2_P1_SHIFT 20
132*4882a593Smuzhiyun #define S3_P1_SHIFT 26
133*4882a593Smuzhiyun #define S5_P1_SHIFT 6
134*4882a593Smuzhiyun #define S6_P1_SHIFT 12
135*4882a593Smuzhiyun #define S7_P1_SHIFT 18
136*4882a593Smuzhiyun #define S8_P1_SHIFT 24
137*4882a593Smuzhiyun #define S9_P1_BKP_SHIFT 6
138*4882a593Smuzhiyun #define S10_P1_SHIFT 6
139*4882a593Smuzhiyun #define S10_P1_BKP_SHIFT 12
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun #define BASE2_SHIFT 12
142*4882a593Smuzhiyun #define BASE2_BKP_SHIFT 18
143*4882a593Smuzhiyun #define S0_P2_SHIFT 20
144*4882a593Smuzhiyun #define S0_P2_BKP_SHIFT 26
145*4882a593Smuzhiyun #define S1_P2_SHIFT 26
146*4882a593Smuzhiyun #define S2_P2_BKP_SHIFT 6
147*4882a593Smuzhiyun #define S3_P2_SHIFT 6
148*4882a593Smuzhiyun #define S3_P2_BKP_SHIFT 12
149*4882a593Smuzhiyun #define S4_P2_SHIFT 12
150*4882a593Smuzhiyun #define S4_P2_BKP_SHIFT 18
151*4882a593Smuzhiyun #define S5_P2_SHIFT 18
152*4882a593Smuzhiyun #define S5_P2_BKP_SHIFT 24
153*4882a593Smuzhiyun #define S6_P2_SHIFT 24
154*4882a593Smuzhiyun #define S7_P2_BKP_SHIFT 6
155*4882a593Smuzhiyun #define S8_P2_SHIFT 6
156*4882a593Smuzhiyun #define S8_P2_BKP_SHIFT 12
157*4882a593Smuzhiyun #define S9_P2_SHIFT 12
158*4882a593Smuzhiyun #define S9_P2_BKP_SHIFT 18
159*4882a593Smuzhiyun #define S10_P2_SHIFT 18
160*4882a593Smuzhiyun #define S10_P2_BKP_SHIFT 24
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun #define BASE2_MASK 0xff000
163*4882a593Smuzhiyun #define BASE2_BKP_MASK 0xfc0000
164*4882a593Smuzhiyun #define S0_P2_MASK 0x3f00000
165*4882a593Smuzhiyun #define S0_P2_BKP_MASK 0xfc000000
166*4882a593Smuzhiyun #define S1_P2_MASK 0xfc000000
167*4882a593Smuzhiyun #define S1_P2_BKP_MASK 0x3f
168*4882a593Smuzhiyun #define S2_P2_MASK 0x3f
169*4882a593Smuzhiyun #define S2_P2_BKP_MASK 0xfc0
170*4882a593Smuzhiyun #define S3_P2_MASK 0xfc0
171*4882a593Smuzhiyun #define S3_P2_BKP_MASK 0x3f000
172*4882a593Smuzhiyun #define S4_P2_MASK 0x3f000
173*4882a593Smuzhiyun #define S4_P2_BKP_MASK 0xfc0000
174*4882a593Smuzhiyun #define S5_P2_MASK 0xfc0000
175*4882a593Smuzhiyun #define S5_P2_BKP_MASK 0x3f000000
176*4882a593Smuzhiyun #define S6_P2_MASK 0x3f000000
177*4882a593Smuzhiyun #define S6_P2_BKP_MASK 0x3f
178*4882a593Smuzhiyun #define S7_P2_MASK 0x3f
179*4882a593Smuzhiyun #define S7_P2_BKP_MASK 0xfc0
180*4882a593Smuzhiyun #define S8_P2_MASK 0xfc0
181*4882a593Smuzhiyun #define S8_P2_BKP_MASK 0x3f000
182*4882a593Smuzhiyun #define S9_P2_MASK 0x3f000
183*4882a593Smuzhiyun #define S9_P2_BKP_MASK 0xfc0000
184*4882a593Smuzhiyun #define S10_P2_MASK 0xfc0000
185*4882a593Smuzhiyun #define S10_P2_BKP_MASK 0x3f000000
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun #define BKP_SEL 0x3
188*4882a593Smuzhiyun #define BKP_REDUN_SEL 0xe0000000
189*4882a593Smuzhiyun #define BKP_REDUN_SHIFT 29
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun #define BIT_APPEND 0x3
192*4882a593Smuzhiyun
calibrate_8916(struct tsens_priv * priv)193*4882a593Smuzhiyun static int calibrate_8916(struct tsens_priv *priv)
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun int base0 = 0, base1 = 0, i;
196*4882a593Smuzhiyun u32 p1[5], p2[5];
197*4882a593Smuzhiyun int mode = 0;
198*4882a593Smuzhiyun u32 *qfprom_cdata, *qfprom_csel;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib");
201*4882a593Smuzhiyun if (IS_ERR(qfprom_cdata))
202*4882a593Smuzhiyun return PTR_ERR(qfprom_cdata);
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun qfprom_csel = (u32 *)qfprom_read(priv->dev, "calib_sel");
205*4882a593Smuzhiyun if (IS_ERR(qfprom_csel)) {
206*4882a593Smuzhiyun kfree(qfprom_cdata);
207*4882a593Smuzhiyun return PTR_ERR(qfprom_csel);
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun mode = (qfprom_csel[0] & MSM8916_CAL_SEL_MASK) >> MSM8916_CAL_SEL_SHIFT;
211*4882a593Smuzhiyun dev_dbg(priv->dev, "calibration mode is %d\n", mode);
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun switch (mode) {
214*4882a593Smuzhiyun case TWO_PT_CALIB:
215*4882a593Smuzhiyun base1 = (qfprom_cdata[1] & MSM8916_BASE1_MASK) >> MSM8916_BASE1_SHIFT;
216*4882a593Smuzhiyun p2[0] = (qfprom_cdata[0] & MSM8916_S0_P2_MASK) >> MSM8916_S0_P2_SHIFT;
217*4882a593Smuzhiyun p2[1] = (qfprom_cdata[0] & MSM8916_S1_P2_MASK) >> MSM8916_S1_P2_SHIFT;
218*4882a593Smuzhiyun p2[2] = (qfprom_cdata[1] & MSM8916_S2_P2_MASK) >> MSM8916_S2_P2_SHIFT;
219*4882a593Smuzhiyun p2[3] = (qfprom_cdata[1] & MSM8916_S3_P2_MASK) >> MSM8916_S3_P2_SHIFT;
220*4882a593Smuzhiyun p2[4] = (qfprom_cdata[1] & MSM8916_S4_P2_MASK) >> MSM8916_S4_P2_SHIFT;
221*4882a593Smuzhiyun for (i = 0; i < priv->num_sensors; i++)
222*4882a593Smuzhiyun p2[i] = ((base1 + p2[i]) << 3);
223*4882a593Smuzhiyun fallthrough;
224*4882a593Smuzhiyun case ONE_PT_CALIB2:
225*4882a593Smuzhiyun base0 = (qfprom_cdata[0] & MSM8916_BASE0_MASK);
226*4882a593Smuzhiyun p1[0] = (qfprom_cdata[0] & MSM8916_S0_P1_MASK) >> MSM8916_S0_P1_SHIFT;
227*4882a593Smuzhiyun p1[1] = (qfprom_cdata[0] & MSM8916_S1_P1_MASK) >> MSM8916_S1_P1_SHIFT;
228*4882a593Smuzhiyun p1[2] = (qfprom_cdata[0] & MSM8916_S2_P1_MASK) >> MSM8916_S2_P1_SHIFT;
229*4882a593Smuzhiyun p1[3] = (qfprom_cdata[1] & MSM8916_S3_P1_MASK) >> MSM8916_S3_P1_SHIFT;
230*4882a593Smuzhiyun p1[4] = (qfprom_cdata[1] & MSM8916_S4_P1_MASK) >> MSM8916_S4_P1_SHIFT;
231*4882a593Smuzhiyun for (i = 0; i < priv->num_sensors; i++)
232*4882a593Smuzhiyun p1[i] = (((base0) + p1[i]) << 3);
233*4882a593Smuzhiyun break;
234*4882a593Smuzhiyun default:
235*4882a593Smuzhiyun for (i = 0; i < priv->num_sensors; i++) {
236*4882a593Smuzhiyun p1[i] = 500;
237*4882a593Smuzhiyun p2[i] = 780;
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun break;
240*4882a593Smuzhiyun }
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun compute_intercept_slope(priv, p1, p2, mode);
243*4882a593Smuzhiyun kfree(qfprom_cdata);
244*4882a593Smuzhiyun kfree(qfprom_csel);
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun return 0;
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun
calibrate_8939(struct tsens_priv * priv)249*4882a593Smuzhiyun static int calibrate_8939(struct tsens_priv *priv)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun int base0 = 0, base1 = 0, i;
252*4882a593Smuzhiyun u32 p1[10], p2[10];
253*4882a593Smuzhiyun int mode = 0;
254*4882a593Smuzhiyun u32 *qfprom_cdata;
255*4882a593Smuzhiyun u32 cdata[6];
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib");
258*4882a593Smuzhiyun if (IS_ERR(qfprom_cdata))
259*4882a593Smuzhiyun return PTR_ERR(qfprom_cdata);
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun /* Mapping between qfprom nvmem and calibration data */
262*4882a593Smuzhiyun cdata[0] = qfprom_cdata[12];
263*4882a593Smuzhiyun cdata[1] = qfprom_cdata[13];
264*4882a593Smuzhiyun cdata[2] = qfprom_cdata[0];
265*4882a593Smuzhiyun cdata[3] = qfprom_cdata[1];
266*4882a593Smuzhiyun cdata[4] = qfprom_cdata[22];
267*4882a593Smuzhiyun cdata[5] = qfprom_cdata[21];
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun mode = (cdata[0] & MSM8939_CAL_SEL_MASK) >> MSM8939_CAL_SEL_SHIFT;
270*4882a593Smuzhiyun dev_dbg(priv->dev, "calibration mode is %d\n", mode);
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun switch (mode) {
273*4882a593Smuzhiyun case TWO_PT_CALIB:
274*4882a593Smuzhiyun base1 = (cdata[3] & MSM8939_BASE1_MASK) >> MSM8939_BASE1_SHIFT;
275*4882a593Smuzhiyun p2[0] = (cdata[0] & MSM8939_S0_P2_MASK) >> MSM8939_S0_P2_SHIFT;
276*4882a593Smuzhiyun p2[1] = (cdata[0] & MSM8939_S1_P2_MASK) >> MSM8939_S1_P2_SHIFT;
277*4882a593Smuzhiyun p2[2] = (cdata[1] & MSM8939_S2_P2_MASK) >> MSM8939_S2_P2_SHIFT;
278*4882a593Smuzhiyun p2[3] = (cdata[1] & MSM8939_S3_P2_MASK) >> MSM8939_S3_P2_SHIFT;
279*4882a593Smuzhiyun p2[4] = (cdata[1] & MSM8939_S4_P2_MASK) >> MSM8939_S4_P2_SHIFT;
280*4882a593Smuzhiyun p2[5] = (cdata[2] & MSM8939_S5_P2_MASK) >> MSM8939_S5_P2_SHIFT;
281*4882a593Smuzhiyun p2[6] = (cdata[2] & MSM8939_S6_P2_MASK) >> MSM8939_S6_P2_SHIFT;
282*4882a593Smuzhiyun p2[7] = (cdata[3] & MSM8939_S7_P2_MASK) >> MSM8939_S7_P2_SHIFT;
283*4882a593Smuzhiyun p2[8] = (cdata[3] & MSM8939_S8_P2_MASK) >> MSM8939_S8_P2_SHIFT;
284*4882a593Smuzhiyun p2[9] = (cdata[4] & MSM8939_S9_P2_MASK_0_4) >> MSM8939_S9_P2_SHIFT_0_4;
285*4882a593Smuzhiyun p2[9] |= ((cdata[5] & MSM8939_S9_P2_MASK_5) >> MSM8939_S9_P2_SHIFT_5) << 5;
286*4882a593Smuzhiyun for (i = 0; i < priv->num_sensors; i++)
287*4882a593Smuzhiyun p2[i] = (base1 + p2[i]) << 2;
288*4882a593Smuzhiyun fallthrough;
289*4882a593Smuzhiyun case ONE_PT_CALIB2:
290*4882a593Smuzhiyun base0 = (cdata[2] & MSM8939_BASE0_MASK) >> MSM8939_BASE0_SHIFT;
291*4882a593Smuzhiyun p1[0] = (cdata[0] & MSM8939_S0_P1_MASK) >> MSM8939_S0_P1_SHIFT;
292*4882a593Smuzhiyun p1[1] = (cdata[0] & MSM8939_S1_P1_MASK) >> MSM8939_S1_P1_SHIFT;
293*4882a593Smuzhiyun p1[2] = (cdata[0] & MSM8939_S2_P1_MASK_0_4) >> MSM8939_S2_P1_SHIFT_0_4;
294*4882a593Smuzhiyun p1[2] |= ((cdata[1] & MSM8939_S2_P1_MASK_5) >> MSM8939_S2_P1_SHIFT_5) << 5;
295*4882a593Smuzhiyun p1[3] = (cdata[1] & MSM8939_S3_P1_MASK) >> MSM8939_S3_P1_SHIFT;
296*4882a593Smuzhiyun p1[4] = (cdata[1] & MSM8939_S4_P1_MASK) >> MSM8939_S4_P1_SHIFT;
297*4882a593Smuzhiyun p1[5] = (cdata[2] & MSM8939_S5_P1_MASK) >> MSM8939_S5_P1_SHIFT;
298*4882a593Smuzhiyun p1[6] = (cdata[2] & MSM8939_S6_P1_MASK) >> MSM8939_S6_P1_SHIFT;
299*4882a593Smuzhiyun p1[7] = (cdata[3] & MSM8939_S7_P1_MASK) >> MSM8939_S7_P1_SHIFT;
300*4882a593Smuzhiyun p1[8] = (cdata[3] & MSM8939_S8_P1_MASK) >> MSM8939_S8_P1_SHIFT;
301*4882a593Smuzhiyun p1[9] = (cdata[4] & MSM8939_S9_P1_MASK) >> MSM8939_S9_P1_SHIFT;
302*4882a593Smuzhiyun for (i = 0; i < priv->num_sensors; i++)
303*4882a593Smuzhiyun p1[i] = ((base0) + p1[i]) << 2;
304*4882a593Smuzhiyun break;
305*4882a593Smuzhiyun default:
306*4882a593Smuzhiyun for (i = 0; i < priv->num_sensors; i++) {
307*4882a593Smuzhiyun p1[i] = 500;
308*4882a593Smuzhiyun p2[i] = 780;
309*4882a593Smuzhiyun }
310*4882a593Smuzhiyun break;
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun compute_intercept_slope(priv, p1, p2, mode);
314*4882a593Smuzhiyun kfree(qfprom_cdata);
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun return 0;
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun
calibrate_8974(struct tsens_priv * priv)319*4882a593Smuzhiyun static int calibrate_8974(struct tsens_priv *priv)
320*4882a593Smuzhiyun {
321*4882a593Smuzhiyun int base1 = 0, base2 = 0, i;
322*4882a593Smuzhiyun u32 p1[11], p2[11];
323*4882a593Smuzhiyun int mode = 0;
324*4882a593Smuzhiyun u32 *calib, *bkp;
325*4882a593Smuzhiyun u32 calib_redun_sel;
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun calib = (u32 *)qfprom_read(priv->dev, "calib");
328*4882a593Smuzhiyun if (IS_ERR(calib))
329*4882a593Smuzhiyun return PTR_ERR(calib);
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun bkp = (u32 *)qfprom_read(priv->dev, "calib_backup");
332*4882a593Smuzhiyun if (IS_ERR(bkp)) {
333*4882a593Smuzhiyun kfree(calib);
334*4882a593Smuzhiyun return PTR_ERR(bkp);
335*4882a593Smuzhiyun }
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun calib_redun_sel = bkp[1] & BKP_REDUN_SEL;
338*4882a593Smuzhiyun calib_redun_sel >>= BKP_REDUN_SHIFT;
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun if (calib_redun_sel == BKP_SEL) {
341*4882a593Smuzhiyun mode = (calib[4] & CAL_SEL_0_1) >> CAL_SEL_SHIFT;
342*4882a593Smuzhiyun mode |= (calib[5] & CAL_SEL_2) >> CAL_SEL_SHIFT_2;
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun switch (mode) {
345*4882a593Smuzhiyun case TWO_PT_CALIB:
346*4882a593Smuzhiyun base2 = (bkp[2] & BASE2_BKP_MASK) >> BASE2_BKP_SHIFT;
347*4882a593Smuzhiyun p2[0] = (bkp[2] & S0_P2_BKP_MASK) >> S0_P2_BKP_SHIFT;
348*4882a593Smuzhiyun p2[1] = (bkp[3] & S1_P2_BKP_MASK);
349*4882a593Smuzhiyun p2[2] = (bkp[3] & S2_P2_BKP_MASK) >> S2_P2_BKP_SHIFT;
350*4882a593Smuzhiyun p2[3] = (bkp[3] & S3_P2_BKP_MASK) >> S3_P2_BKP_SHIFT;
351*4882a593Smuzhiyun p2[4] = (bkp[3] & S4_P2_BKP_MASK) >> S4_P2_BKP_SHIFT;
352*4882a593Smuzhiyun p2[5] = (calib[4] & S5_P2_BKP_MASK) >> S5_P2_BKP_SHIFT;
353*4882a593Smuzhiyun p2[6] = (calib[5] & S6_P2_BKP_MASK);
354*4882a593Smuzhiyun p2[7] = (calib[5] & S7_P2_BKP_MASK) >> S7_P2_BKP_SHIFT;
355*4882a593Smuzhiyun p2[8] = (calib[5] & S8_P2_BKP_MASK) >> S8_P2_BKP_SHIFT;
356*4882a593Smuzhiyun p2[9] = (calib[5] & S9_P2_BKP_MASK) >> S9_P2_BKP_SHIFT;
357*4882a593Smuzhiyun p2[10] = (calib[5] & S10_P2_BKP_MASK) >> S10_P2_BKP_SHIFT;
358*4882a593Smuzhiyun fallthrough;
359*4882a593Smuzhiyun case ONE_PT_CALIB:
360*4882a593Smuzhiyun case ONE_PT_CALIB2:
361*4882a593Smuzhiyun base1 = bkp[0] & BASE1_MASK;
362*4882a593Smuzhiyun p1[0] = (bkp[0] & S0_P1_MASK) >> S0_P1_SHIFT;
363*4882a593Smuzhiyun p1[1] = (bkp[0] & S1_P1_MASK) >> S1_P1_SHIFT;
364*4882a593Smuzhiyun p1[2] = (bkp[0] & S2_P1_MASK) >> S2_P1_SHIFT;
365*4882a593Smuzhiyun p1[3] = (bkp[0] & S3_P1_MASK) >> S3_P1_SHIFT;
366*4882a593Smuzhiyun p1[4] = (bkp[1] & S4_P1_MASK);
367*4882a593Smuzhiyun p1[5] = (bkp[1] & S5_P1_MASK) >> S5_P1_SHIFT;
368*4882a593Smuzhiyun p1[6] = (bkp[1] & S6_P1_MASK) >> S6_P1_SHIFT;
369*4882a593Smuzhiyun p1[7] = (bkp[1] & S7_P1_MASK) >> S7_P1_SHIFT;
370*4882a593Smuzhiyun p1[8] = (bkp[2] & S8_P1_MASK_BKP) >> S8_P1_SHIFT;
371*4882a593Smuzhiyun p1[9] = (bkp[2] & S9_P1_MASK_BKP) >> S9_P1_BKP_SHIFT;
372*4882a593Smuzhiyun p1[10] = (bkp[2] & S10_P1_MASK_BKP) >> S10_P1_BKP_SHIFT;
373*4882a593Smuzhiyun break;
374*4882a593Smuzhiyun }
375*4882a593Smuzhiyun } else {
376*4882a593Smuzhiyun mode = (calib[1] & CAL_SEL_0_1) >> CAL_SEL_SHIFT;
377*4882a593Smuzhiyun mode |= (calib[3] & CAL_SEL_2) >> CAL_SEL_SHIFT_2;
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun switch (mode) {
380*4882a593Smuzhiyun case TWO_PT_CALIB:
381*4882a593Smuzhiyun base2 = (calib[2] & BASE2_MASK) >> BASE2_SHIFT;
382*4882a593Smuzhiyun p2[0] = (calib[2] & S0_P2_MASK) >> S0_P2_SHIFT;
383*4882a593Smuzhiyun p2[1] = (calib[2] & S1_P2_MASK) >> S1_P2_SHIFT;
384*4882a593Smuzhiyun p2[2] = (calib[3] & S2_P2_MASK);
385*4882a593Smuzhiyun p2[3] = (calib[3] & S3_P2_MASK) >> S3_P2_SHIFT;
386*4882a593Smuzhiyun p2[4] = (calib[3] & S4_P2_MASK) >> S4_P2_SHIFT;
387*4882a593Smuzhiyun p2[5] = (calib[3] & S5_P2_MASK) >> S5_P2_SHIFT;
388*4882a593Smuzhiyun p2[6] = (calib[3] & S6_P2_MASK) >> S6_P2_SHIFT;
389*4882a593Smuzhiyun p2[7] = (calib[4] & S7_P2_MASK);
390*4882a593Smuzhiyun p2[8] = (calib[4] & S8_P2_MASK) >> S8_P2_SHIFT;
391*4882a593Smuzhiyun p2[9] = (calib[4] & S9_P2_MASK) >> S9_P2_SHIFT;
392*4882a593Smuzhiyun p2[10] = (calib[4] & S10_P2_MASK) >> S10_P2_SHIFT;
393*4882a593Smuzhiyun fallthrough;
394*4882a593Smuzhiyun case ONE_PT_CALIB:
395*4882a593Smuzhiyun case ONE_PT_CALIB2:
396*4882a593Smuzhiyun base1 = calib[0] & BASE1_MASK;
397*4882a593Smuzhiyun p1[0] = (calib[0] & S0_P1_MASK) >> S0_P1_SHIFT;
398*4882a593Smuzhiyun p1[1] = (calib[0] & S1_P1_MASK) >> S1_P1_SHIFT;
399*4882a593Smuzhiyun p1[2] = (calib[0] & S2_P1_MASK) >> S2_P1_SHIFT;
400*4882a593Smuzhiyun p1[3] = (calib[0] & S3_P1_MASK) >> S3_P1_SHIFT;
401*4882a593Smuzhiyun p1[4] = (calib[1] & S4_P1_MASK);
402*4882a593Smuzhiyun p1[5] = (calib[1] & S5_P1_MASK) >> S5_P1_SHIFT;
403*4882a593Smuzhiyun p1[6] = (calib[1] & S6_P1_MASK) >> S6_P1_SHIFT;
404*4882a593Smuzhiyun p1[7] = (calib[1] & S7_P1_MASK) >> S7_P1_SHIFT;
405*4882a593Smuzhiyun p1[8] = (calib[1] & S8_P1_MASK) >> S8_P1_SHIFT;
406*4882a593Smuzhiyun p1[9] = (calib[2] & S9_P1_MASK);
407*4882a593Smuzhiyun p1[10] = (calib[2] & S10_P1_MASK) >> S10_P1_SHIFT;
408*4882a593Smuzhiyun break;
409*4882a593Smuzhiyun }
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun switch (mode) {
413*4882a593Smuzhiyun case ONE_PT_CALIB:
414*4882a593Smuzhiyun for (i = 0; i < priv->num_sensors; i++)
415*4882a593Smuzhiyun p1[i] += (base1 << 2) | BIT_APPEND;
416*4882a593Smuzhiyun break;
417*4882a593Smuzhiyun case TWO_PT_CALIB:
418*4882a593Smuzhiyun for (i = 0; i < priv->num_sensors; i++) {
419*4882a593Smuzhiyun p2[i] += base2;
420*4882a593Smuzhiyun p2[i] <<= 2;
421*4882a593Smuzhiyun p2[i] |= BIT_APPEND;
422*4882a593Smuzhiyun }
423*4882a593Smuzhiyun fallthrough;
424*4882a593Smuzhiyun case ONE_PT_CALIB2:
425*4882a593Smuzhiyun for (i = 0; i < priv->num_sensors; i++) {
426*4882a593Smuzhiyun p1[i] += base1;
427*4882a593Smuzhiyun p1[i] <<= 2;
428*4882a593Smuzhiyun p1[i] |= BIT_APPEND;
429*4882a593Smuzhiyun }
430*4882a593Smuzhiyun break;
431*4882a593Smuzhiyun default:
432*4882a593Smuzhiyun for (i = 0; i < priv->num_sensors; i++)
433*4882a593Smuzhiyun p2[i] = 780;
434*4882a593Smuzhiyun p1[0] = 502;
435*4882a593Smuzhiyun p1[1] = 509;
436*4882a593Smuzhiyun p1[2] = 503;
437*4882a593Smuzhiyun p1[3] = 509;
438*4882a593Smuzhiyun p1[4] = 505;
439*4882a593Smuzhiyun p1[5] = 509;
440*4882a593Smuzhiyun p1[6] = 507;
441*4882a593Smuzhiyun p1[7] = 510;
442*4882a593Smuzhiyun p1[8] = 508;
443*4882a593Smuzhiyun p1[9] = 509;
444*4882a593Smuzhiyun p1[10] = 508;
445*4882a593Smuzhiyun break;
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun compute_intercept_slope(priv, p1, p2, mode);
449*4882a593Smuzhiyun kfree(calib);
450*4882a593Smuzhiyun kfree(bkp);
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun return 0;
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun /* v0.1: 8916, 8939, 8974 */
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun static struct tsens_features tsens_v0_1_feat = {
458*4882a593Smuzhiyun .ver_major = VER_0_1,
459*4882a593Smuzhiyun .crit_int = 0,
460*4882a593Smuzhiyun .adc = 1,
461*4882a593Smuzhiyun .srot_split = 1,
462*4882a593Smuzhiyun .max_sensors = 11,
463*4882a593Smuzhiyun };
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun static const struct reg_field tsens_v0_1_regfields[MAX_REGFIELDS] = {
466*4882a593Smuzhiyun /* ----- SROT ------ */
467*4882a593Smuzhiyun /* No VERSION information */
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun /* CTRL_OFFSET */
470*4882a593Smuzhiyun [TSENS_EN] = REG_FIELD(SROT_CTRL_OFF, 0, 0),
471*4882a593Smuzhiyun [TSENS_SW_RST] = REG_FIELD(SROT_CTRL_OFF, 1, 1),
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun /* ----- TM ------ */
474*4882a593Smuzhiyun /* INTERRUPT ENABLE */
475*4882a593Smuzhiyun [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 0),
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun /* UPPER/LOWER TEMPERATURE THRESHOLDS */
478*4882a593Smuzhiyun REG_FIELD_FOR_EACH_SENSOR11(LOW_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 0, 9),
479*4882a593Smuzhiyun REG_FIELD_FOR_EACH_SENSOR11(UP_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 10, 19),
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun /* UPPER/LOWER INTERRUPTS [CLEAR/STATUS] */
482*4882a593Smuzhiyun REG_FIELD_FOR_EACH_SENSOR11(LOW_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 20, 20),
483*4882a593Smuzhiyun REG_FIELD_FOR_EACH_SENSOR11(UP_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 21, 21),
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun /* NO CRITICAL INTERRUPT SUPPORT on v0.1 */
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun /* Sn_STATUS */
488*4882a593Smuzhiyun REG_FIELD_FOR_EACH_SENSOR11(LAST_TEMP, TM_Sn_STATUS_OFF, 0, 9),
489*4882a593Smuzhiyun /* No VALID field on v0.1 */
490*4882a593Smuzhiyun /* xxx_STATUS bits: 1 == threshold violated */
491*4882a593Smuzhiyun REG_FIELD_FOR_EACH_SENSOR11(MIN_STATUS, TM_Sn_STATUS_OFF, 10, 10),
492*4882a593Smuzhiyun REG_FIELD_FOR_EACH_SENSOR11(LOWER_STATUS, TM_Sn_STATUS_OFF, 11, 11),
493*4882a593Smuzhiyun REG_FIELD_FOR_EACH_SENSOR11(UPPER_STATUS, TM_Sn_STATUS_OFF, 12, 12),
494*4882a593Smuzhiyun /* No CRITICAL field on v0.1 */
495*4882a593Smuzhiyun REG_FIELD_FOR_EACH_SENSOR11(MAX_STATUS, TM_Sn_STATUS_OFF, 13, 13),
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun /* TRDY: 1=ready, 0=in progress */
498*4882a593Smuzhiyun [TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0),
499*4882a593Smuzhiyun };
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun static const struct tsens_ops ops_8916 = {
502*4882a593Smuzhiyun .init = init_common,
503*4882a593Smuzhiyun .calibrate = calibrate_8916,
504*4882a593Smuzhiyun .get_temp = get_temp_common,
505*4882a593Smuzhiyun };
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun struct tsens_plat_data data_8916 = {
508*4882a593Smuzhiyun .num_sensors = 5,
509*4882a593Smuzhiyun .ops = &ops_8916,
510*4882a593Smuzhiyun .hw_ids = (unsigned int []){0, 1, 2, 4, 5 },
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun .feat = &tsens_v0_1_feat,
513*4882a593Smuzhiyun .fields = tsens_v0_1_regfields,
514*4882a593Smuzhiyun };
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun static const struct tsens_ops ops_8939 = {
517*4882a593Smuzhiyun .init = init_common,
518*4882a593Smuzhiyun .calibrate = calibrate_8939,
519*4882a593Smuzhiyun .get_temp = get_temp_common,
520*4882a593Smuzhiyun };
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun struct tsens_plat_data data_8939 = {
523*4882a593Smuzhiyun .num_sensors = 10,
524*4882a593Smuzhiyun .ops = &ops_8939,
525*4882a593Smuzhiyun .hw_ids = (unsigned int []){ 0, 1, 2, 3, 5, 6, 7, 8, 9, 10 },
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun .feat = &tsens_v0_1_feat,
528*4882a593Smuzhiyun .fields = tsens_v0_1_regfields,
529*4882a593Smuzhiyun };
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun static const struct tsens_ops ops_8974 = {
532*4882a593Smuzhiyun .init = init_common,
533*4882a593Smuzhiyun .calibrate = calibrate_8974,
534*4882a593Smuzhiyun .get_temp = get_temp_common,
535*4882a593Smuzhiyun };
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun struct tsens_plat_data data_8974 = {
538*4882a593Smuzhiyun .num_sensors = 11,
539*4882a593Smuzhiyun .ops = &ops_8974,
540*4882a593Smuzhiyun .feat = &tsens_v0_1_feat,
541*4882a593Smuzhiyun .fields = tsens_v0_1_regfields,
542*4882a593Smuzhiyun };
543