xref: /OK3568_Linux_fs/kernel/drivers/thermal/qcom/tsens-8960.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #include <linux/platform_device.h>
7*4882a593Smuzhiyun #include <linux/delay.h>
8*4882a593Smuzhiyun #include <linux/bitops.h>
9*4882a593Smuzhiyun #include <linux/regmap.h>
10*4882a593Smuzhiyun #include <linux/thermal.h>
11*4882a593Smuzhiyun #include "tsens.h"
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #define CAL_MDEGC		30000
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #define CONFIG_ADDR		0x3640
16*4882a593Smuzhiyun #define CONFIG_ADDR_8660	0x3620
17*4882a593Smuzhiyun /* CONFIG_ADDR bitmasks */
18*4882a593Smuzhiyun #define CONFIG			0x9b
19*4882a593Smuzhiyun #define CONFIG_MASK		0xf
20*4882a593Smuzhiyun #define CONFIG_8660		1
21*4882a593Smuzhiyun #define CONFIG_SHIFT_8660	28
22*4882a593Smuzhiyun #define CONFIG_MASK_8660	(3 << CONFIG_SHIFT_8660)
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #define STATUS_CNTL_ADDR_8064	0x3660
25*4882a593Smuzhiyun #define CNTL_ADDR		0x3620
26*4882a593Smuzhiyun /* CNTL_ADDR bitmasks */
27*4882a593Smuzhiyun #define EN			BIT(0)
28*4882a593Smuzhiyun #define SW_RST			BIT(1)
29*4882a593Smuzhiyun #define SENSOR0_EN		BIT(3)
30*4882a593Smuzhiyun #define SLP_CLK_ENA		BIT(26)
31*4882a593Smuzhiyun #define SLP_CLK_ENA_8660	BIT(24)
32*4882a593Smuzhiyun #define MEASURE_PERIOD		1
33*4882a593Smuzhiyun #define SENSOR0_SHIFT		3
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun /* INT_STATUS_ADDR bitmasks */
36*4882a593Smuzhiyun #define MIN_STATUS_MASK		BIT(0)
37*4882a593Smuzhiyun #define LOWER_STATUS_CLR	BIT(1)
38*4882a593Smuzhiyun #define UPPER_STATUS_CLR	BIT(2)
39*4882a593Smuzhiyun #define MAX_STATUS_MASK		BIT(3)
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define THRESHOLD_ADDR		0x3624
42*4882a593Smuzhiyun /* THRESHOLD_ADDR bitmasks */
43*4882a593Smuzhiyun #define THRESHOLD_MAX_LIMIT_SHIFT	24
44*4882a593Smuzhiyun #define THRESHOLD_MIN_LIMIT_SHIFT	16
45*4882a593Smuzhiyun #define THRESHOLD_UPPER_LIMIT_SHIFT	8
46*4882a593Smuzhiyun #define THRESHOLD_LOWER_LIMIT_SHIFT	0
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun /* Initial temperature threshold values */
49*4882a593Smuzhiyun #define LOWER_LIMIT_TH		0x50
50*4882a593Smuzhiyun #define UPPER_LIMIT_TH		0xdf
51*4882a593Smuzhiyun #define MIN_LIMIT_TH		0x0
52*4882a593Smuzhiyun #define MAX_LIMIT_TH		0xff
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun #define S0_STATUS_ADDR		0x3628
55*4882a593Smuzhiyun #define INT_STATUS_ADDR		0x363c
56*4882a593Smuzhiyun #define TRDY_MASK		BIT(7)
57*4882a593Smuzhiyun #define TIMEOUT_US		100
58*4882a593Smuzhiyun 
suspend_8960(struct tsens_priv * priv)59*4882a593Smuzhiyun static int suspend_8960(struct tsens_priv *priv)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun 	int ret;
62*4882a593Smuzhiyun 	unsigned int mask;
63*4882a593Smuzhiyun 	struct regmap *map = priv->tm_map;
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 	ret = regmap_read(map, THRESHOLD_ADDR, &priv->ctx.threshold);
66*4882a593Smuzhiyun 	if (ret)
67*4882a593Smuzhiyun 		return ret;
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	ret = regmap_read(map, CNTL_ADDR, &priv->ctx.control);
70*4882a593Smuzhiyun 	if (ret)
71*4882a593Smuzhiyun 		return ret;
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	if (priv->num_sensors > 1)
74*4882a593Smuzhiyun 		mask = SLP_CLK_ENA | EN;
75*4882a593Smuzhiyun 	else
76*4882a593Smuzhiyun 		mask = SLP_CLK_ENA_8660 | EN;
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	ret = regmap_update_bits(map, CNTL_ADDR, mask, 0);
79*4882a593Smuzhiyun 	if (ret)
80*4882a593Smuzhiyun 		return ret;
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 	return 0;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun 
resume_8960(struct tsens_priv * priv)85*4882a593Smuzhiyun static int resume_8960(struct tsens_priv *priv)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun 	int ret;
88*4882a593Smuzhiyun 	struct regmap *map = priv->tm_map;
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	ret = regmap_update_bits(map, CNTL_ADDR, SW_RST, SW_RST);
91*4882a593Smuzhiyun 	if (ret)
92*4882a593Smuzhiyun 		return ret;
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	/*
95*4882a593Smuzhiyun 	 * Separate CONFIG restore is not needed only for 8660 as
96*4882a593Smuzhiyun 	 * config is part of CTRL Addr and its restored as such
97*4882a593Smuzhiyun 	 */
98*4882a593Smuzhiyun 	if (priv->num_sensors > 1) {
99*4882a593Smuzhiyun 		ret = regmap_update_bits(map, CONFIG_ADDR, CONFIG_MASK, CONFIG);
100*4882a593Smuzhiyun 		if (ret)
101*4882a593Smuzhiyun 			return ret;
102*4882a593Smuzhiyun 	}
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	ret = regmap_write(map, THRESHOLD_ADDR, priv->ctx.threshold);
105*4882a593Smuzhiyun 	if (ret)
106*4882a593Smuzhiyun 		return ret;
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	ret = regmap_write(map, CNTL_ADDR, priv->ctx.control);
109*4882a593Smuzhiyun 	if (ret)
110*4882a593Smuzhiyun 		return ret;
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	return 0;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun 
enable_8960(struct tsens_priv * priv,int id)115*4882a593Smuzhiyun static int enable_8960(struct tsens_priv *priv, int id)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun 	int ret;
118*4882a593Smuzhiyun 	u32 reg, mask;
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	ret = regmap_read(priv->tm_map, CNTL_ADDR, &reg);
121*4882a593Smuzhiyun 	if (ret)
122*4882a593Smuzhiyun 		return ret;
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	mask = BIT(id + SENSOR0_SHIFT);
125*4882a593Smuzhiyun 	ret = regmap_write(priv->tm_map, CNTL_ADDR, reg | SW_RST);
126*4882a593Smuzhiyun 	if (ret)
127*4882a593Smuzhiyun 		return ret;
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	if (priv->num_sensors > 1)
130*4882a593Smuzhiyun 		reg |= mask | SLP_CLK_ENA | EN;
131*4882a593Smuzhiyun 	else
132*4882a593Smuzhiyun 		reg |= mask | SLP_CLK_ENA_8660 | EN;
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	ret = regmap_write(priv->tm_map, CNTL_ADDR, reg);
135*4882a593Smuzhiyun 	if (ret)
136*4882a593Smuzhiyun 		return ret;
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	return 0;
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun 
disable_8960(struct tsens_priv * priv)141*4882a593Smuzhiyun static void disable_8960(struct tsens_priv *priv)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun 	int ret;
144*4882a593Smuzhiyun 	u32 reg_cntl;
145*4882a593Smuzhiyun 	u32 mask;
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	mask = GENMASK(priv->num_sensors - 1, 0);
148*4882a593Smuzhiyun 	mask <<= SENSOR0_SHIFT;
149*4882a593Smuzhiyun 	mask |= EN;
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	ret = regmap_read(priv->tm_map, CNTL_ADDR, &reg_cntl);
152*4882a593Smuzhiyun 	if (ret)
153*4882a593Smuzhiyun 		return;
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	reg_cntl &= ~mask;
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	if (priv->num_sensors > 1)
158*4882a593Smuzhiyun 		reg_cntl &= ~SLP_CLK_ENA;
159*4882a593Smuzhiyun 	else
160*4882a593Smuzhiyun 		reg_cntl &= ~SLP_CLK_ENA_8660;
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun 
init_8960(struct tsens_priv * priv)165*4882a593Smuzhiyun static int init_8960(struct tsens_priv *priv)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun 	int ret, i;
168*4882a593Smuzhiyun 	u32 reg_cntl;
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	priv->tm_map = dev_get_regmap(priv->dev, NULL);
171*4882a593Smuzhiyun 	if (!priv->tm_map)
172*4882a593Smuzhiyun 		return -ENODEV;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	/*
175*4882a593Smuzhiyun 	 * The status registers for each sensor are discontiguous
176*4882a593Smuzhiyun 	 * because some SoCs have 5 sensors while others have more
177*4882a593Smuzhiyun 	 * but the control registers stay in the same place, i.e
178*4882a593Smuzhiyun 	 * directly after the first 5 status registers.
179*4882a593Smuzhiyun 	 */
180*4882a593Smuzhiyun 	for (i = 0; i < priv->num_sensors; i++) {
181*4882a593Smuzhiyun 		if (i >= 5)
182*4882a593Smuzhiyun 			priv->sensor[i].status = S0_STATUS_ADDR + 40;
183*4882a593Smuzhiyun 		priv->sensor[i].status += i * 4;
184*4882a593Smuzhiyun 	}
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	reg_cntl = SW_RST;
187*4882a593Smuzhiyun 	ret = regmap_update_bits(priv->tm_map, CNTL_ADDR, SW_RST, reg_cntl);
188*4882a593Smuzhiyun 	if (ret)
189*4882a593Smuzhiyun 		return ret;
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	if (priv->num_sensors > 1) {
192*4882a593Smuzhiyun 		reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18);
193*4882a593Smuzhiyun 		reg_cntl &= ~SW_RST;
194*4882a593Smuzhiyun 		ret = regmap_update_bits(priv->tm_map, CONFIG_ADDR,
195*4882a593Smuzhiyun 					 CONFIG_MASK, CONFIG);
196*4882a593Smuzhiyun 	} else {
197*4882a593Smuzhiyun 		reg_cntl |= SLP_CLK_ENA_8660 | (MEASURE_PERIOD << 16);
198*4882a593Smuzhiyun 		reg_cntl &= ~CONFIG_MASK_8660;
199*4882a593Smuzhiyun 		reg_cntl |= CONFIG_8660 << CONFIG_SHIFT_8660;
200*4882a593Smuzhiyun 	}
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	reg_cntl |= GENMASK(priv->num_sensors - 1, 0) << SENSOR0_SHIFT;
203*4882a593Smuzhiyun 	ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
204*4882a593Smuzhiyun 	if (ret)
205*4882a593Smuzhiyun 		return ret;
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	reg_cntl |= EN;
208*4882a593Smuzhiyun 	ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
209*4882a593Smuzhiyun 	if (ret)
210*4882a593Smuzhiyun 		return ret;
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	return 0;
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun 
calibrate_8960(struct tsens_priv * priv)215*4882a593Smuzhiyun static int calibrate_8960(struct tsens_priv *priv)
216*4882a593Smuzhiyun {
217*4882a593Smuzhiyun 	int i;
218*4882a593Smuzhiyun 	char *data;
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 	ssize_t num_read = priv->num_sensors;
221*4882a593Smuzhiyun 	struct tsens_sensor *s = priv->sensor;
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	data = qfprom_read(priv->dev, "calib");
224*4882a593Smuzhiyun 	if (IS_ERR(data))
225*4882a593Smuzhiyun 		data = qfprom_read(priv->dev, "calib_backup");
226*4882a593Smuzhiyun 	if (IS_ERR(data))
227*4882a593Smuzhiyun 		return PTR_ERR(data);
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	for (i = 0; i < num_read; i++, s++)
230*4882a593Smuzhiyun 		s->offset = data[i];
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	kfree(data);
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	return 0;
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun /* Temperature on y axis and ADC-code on x-axis */
code_to_mdegC(u32 adc_code,const struct tsens_sensor * s)238*4882a593Smuzhiyun static inline int code_to_mdegC(u32 adc_code, const struct tsens_sensor *s)
239*4882a593Smuzhiyun {
240*4882a593Smuzhiyun 	int slope, offset;
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	slope = thermal_zone_get_slope(s->tzd);
243*4882a593Smuzhiyun 	offset = CAL_MDEGC - slope * s->offset;
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	return adc_code * slope + offset;
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun 
get_temp_8960(const struct tsens_sensor * s,int * temp)248*4882a593Smuzhiyun static int get_temp_8960(const struct tsens_sensor *s, int *temp)
249*4882a593Smuzhiyun {
250*4882a593Smuzhiyun 	int ret;
251*4882a593Smuzhiyun 	u32 code, trdy;
252*4882a593Smuzhiyun 	struct tsens_priv *priv = s->priv;
253*4882a593Smuzhiyun 	unsigned long timeout;
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 	timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
256*4882a593Smuzhiyun 	do {
257*4882a593Smuzhiyun 		ret = regmap_read(priv->tm_map, INT_STATUS_ADDR, &trdy);
258*4882a593Smuzhiyun 		if (ret)
259*4882a593Smuzhiyun 			return ret;
260*4882a593Smuzhiyun 		if (!(trdy & TRDY_MASK))
261*4882a593Smuzhiyun 			continue;
262*4882a593Smuzhiyun 		ret = regmap_read(priv->tm_map, s->status, &code);
263*4882a593Smuzhiyun 		if (ret)
264*4882a593Smuzhiyun 			return ret;
265*4882a593Smuzhiyun 		*temp = code_to_mdegC(code, s);
266*4882a593Smuzhiyun 		return 0;
267*4882a593Smuzhiyun 	} while (time_before(jiffies, timeout));
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	return -ETIMEDOUT;
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun static const struct tsens_ops ops_8960 = {
273*4882a593Smuzhiyun 	.init		= init_8960,
274*4882a593Smuzhiyun 	.calibrate	= calibrate_8960,
275*4882a593Smuzhiyun 	.get_temp	= get_temp_8960,
276*4882a593Smuzhiyun 	.enable		= enable_8960,
277*4882a593Smuzhiyun 	.disable	= disable_8960,
278*4882a593Smuzhiyun 	.suspend	= suspend_8960,
279*4882a593Smuzhiyun 	.resume		= resume_8960,
280*4882a593Smuzhiyun };
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun struct tsens_plat_data data_8960 = {
283*4882a593Smuzhiyun 	.num_sensors	= 11,
284*4882a593Smuzhiyun 	.ops		= &ops_8960,
285*4882a593Smuzhiyun };
286