1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * intel_soc_dts_thermal.c
4*4882a593Smuzhiyun * Copyright (c) 2014, Intel Corporation.
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/acpi.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/interrupt.h>
12*4882a593Smuzhiyun #include <asm/cpu_device_id.h>
13*4882a593Smuzhiyun #include <asm/intel-family.h>
14*4882a593Smuzhiyun #include "intel_soc_dts_iosf.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define CRITICAL_OFFSET_FROM_TJ_MAX 5000
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun static int crit_offset = CRITICAL_OFFSET_FROM_TJ_MAX;
19*4882a593Smuzhiyun module_param(crit_offset, int, 0644);
20*4882a593Smuzhiyun MODULE_PARM_DESC(crit_offset,
21*4882a593Smuzhiyun "Critical Temperature offset from tj max in millidegree Celsius.");
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /* IRQ 86 is a fixed APIC interrupt for BYT DTS Aux threshold notifications */
24*4882a593Smuzhiyun #define BYT_SOC_DTS_APIC_IRQ 86
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun static int soc_dts_thres_gsi;
27*4882a593Smuzhiyun static int soc_dts_thres_irq;
28*4882a593Smuzhiyun static struct intel_soc_dts_sensors *soc_dts;
29*4882a593Smuzhiyun
soc_irq_thread_fn(int irq,void * dev_data)30*4882a593Smuzhiyun static irqreturn_t soc_irq_thread_fn(int irq, void *dev_data)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun pr_debug("proc_thermal_interrupt\n");
33*4882a593Smuzhiyun intel_soc_dts_iosf_interrupt_handler(soc_dts);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun return IRQ_HANDLED;
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun static const struct x86_cpu_id soc_thermal_ids[] = {
39*4882a593Smuzhiyun X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, BYT_SOC_DTS_APIC_IRQ),
40*4882a593Smuzhiyun {}
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun MODULE_DEVICE_TABLE(x86cpu, soc_thermal_ids);
43*4882a593Smuzhiyun
intel_soc_thermal_init(void)44*4882a593Smuzhiyun static int __init intel_soc_thermal_init(void)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun int err = 0;
47*4882a593Smuzhiyun const struct x86_cpu_id *match_cpu;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun match_cpu = x86_match_cpu(soc_thermal_ids);
50*4882a593Smuzhiyun if (!match_cpu)
51*4882a593Smuzhiyun return -ENODEV;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* Create a zone with 2 trips with marked as read only */
54*4882a593Smuzhiyun soc_dts = intel_soc_dts_iosf_init(INTEL_SOC_DTS_INTERRUPT_APIC, 2, 1);
55*4882a593Smuzhiyun if (IS_ERR(soc_dts)) {
56*4882a593Smuzhiyun err = PTR_ERR(soc_dts);
57*4882a593Smuzhiyun return err;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun soc_dts_thres_gsi = (int)match_cpu->driver_data;
61*4882a593Smuzhiyun if (soc_dts_thres_gsi) {
62*4882a593Smuzhiyun /*
63*4882a593Smuzhiyun * Note the flags here MUST match the firmware defaults, rather
64*4882a593Smuzhiyun * then the request_irq flags, otherwise we get an EBUSY error.
65*4882a593Smuzhiyun */
66*4882a593Smuzhiyun soc_dts_thres_irq = acpi_register_gsi(NULL, soc_dts_thres_gsi,
67*4882a593Smuzhiyun ACPI_LEVEL_SENSITIVE,
68*4882a593Smuzhiyun ACPI_ACTIVE_LOW);
69*4882a593Smuzhiyun if (soc_dts_thres_irq < 0) {
70*4882a593Smuzhiyun pr_warn("intel_soc_dts: Could not get IRQ for GSI %d, err %d\n",
71*4882a593Smuzhiyun soc_dts_thres_gsi, soc_dts_thres_irq);
72*4882a593Smuzhiyun soc_dts_thres_irq = 0;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun if (soc_dts_thres_irq) {
77*4882a593Smuzhiyun err = request_threaded_irq(soc_dts_thres_irq, NULL,
78*4882a593Smuzhiyun soc_irq_thread_fn,
79*4882a593Smuzhiyun IRQF_TRIGGER_RISING | IRQF_ONESHOT,
80*4882a593Smuzhiyun "soc_dts", soc_dts);
81*4882a593Smuzhiyun if (err) {
82*4882a593Smuzhiyun /*
83*4882a593Smuzhiyun * Do not just error out because the user space thermal
84*4882a593Smuzhiyun * daemon such as DPTF may use polling instead of being
85*4882a593Smuzhiyun * interrupt driven.
86*4882a593Smuzhiyun */
87*4882a593Smuzhiyun pr_warn("request_threaded_irq ret %d\n", err);
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun err = intel_soc_dts_iosf_add_read_only_critical_trip(soc_dts,
92*4882a593Smuzhiyun crit_offset);
93*4882a593Smuzhiyun if (err)
94*4882a593Smuzhiyun goto error_trips;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun return 0;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun error_trips:
99*4882a593Smuzhiyun if (soc_dts_thres_irq) {
100*4882a593Smuzhiyun free_irq(soc_dts_thres_irq, soc_dts);
101*4882a593Smuzhiyun acpi_unregister_gsi(soc_dts_thres_gsi);
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun intel_soc_dts_iosf_exit(soc_dts);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun return err;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
intel_soc_thermal_exit(void)108*4882a593Smuzhiyun static void __exit intel_soc_thermal_exit(void)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun if (soc_dts_thres_irq) {
111*4882a593Smuzhiyun free_irq(soc_dts_thres_irq, soc_dts);
112*4882a593Smuzhiyun acpi_unregister_gsi(soc_dts_thres_gsi);
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun intel_soc_dts_iosf_exit(soc_dts);
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun module_init(intel_soc_thermal_init)
118*4882a593Smuzhiyun module_exit(intel_soc_thermal_exit)
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun MODULE_DESCRIPTION("Intel SoC DTS Thermal Driver");
121*4882a593Smuzhiyun MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
122*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
123