1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * intel_soc_dts_iosf.h 4*4882a593Smuzhiyun * Copyright (c) 2015, Intel Corporation. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _INTEL_SOC_DTS_IOSF_CORE_H 8*4882a593Smuzhiyun #define _INTEL_SOC_DTS_IOSF_CORE_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/thermal.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* DTS0 and DTS 1 */ 13*4882a593Smuzhiyun #define SOC_MAX_DTS_SENSORS 2 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun enum intel_soc_dts_interrupt_type { 16*4882a593Smuzhiyun INTEL_SOC_DTS_INTERRUPT_NONE, 17*4882a593Smuzhiyun INTEL_SOC_DTS_INTERRUPT_APIC, 18*4882a593Smuzhiyun INTEL_SOC_DTS_INTERRUPT_MSI, 19*4882a593Smuzhiyun INTEL_SOC_DTS_INTERRUPT_SCI, 20*4882a593Smuzhiyun INTEL_SOC_DTS_INTERRUPT_SMI, 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun struct intel_soc_dts_sensors; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun struct intel_soc_dts_sensor_entry { 26*4882a593Smuzhiyun int id; 27*4882a593Smuzhiyun u32 store_status; 28*4882a593Smuzhiyun u32 trip_mask; 29*4882a593Smuzhiyun u32 trip_count; 30*4882a593Smuzhiyun enum thermal_trip_type trip_types[2]; 31*4882a593Smuzhiyun struct thermal_zone_device *tzone; 32*4882a593Smuzhiyun struct intel_soc_dts_sensors *sensors; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun struct intel_soc_dts_sensors { 36*4882a593Smuzhiyun u32 tj_max; 37*4882a593Smuzhiyun spinlock_t intr_notify_lock; 38*4882a593Smuzhiyun struct mutex dts_update_lock; 39*4882a593Smuzhiyun enum intel_soc_dts_interrupt_type intr_type; 40*4882a593Smuzhiyun struct intel_soc_dts_sensor_entry soc_dts[SOC_MAX_DTS_SENSORS]; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun struct intel_soc_dts_sensors *intel_soc_dts_iosf_init( 44*4882a593Smuzhiyun enum intel_soc_dts_interrupt_type intr_type, int trip_count, 45*4882a593Smuzhiyun int read_only_trip_count); 46*4882a593Smuzhiyun void intel_soc_dts_iosf_exit(struct intel_soc_dts_sensors *sensors); 47*4882a593Smuzhiyun void intel_soc_dts_iosf_interrupt_handler( 48*4882a593Smuzhiyun struct intel_soc_dts_sensors *sensors); 49*4882a593Smuzhiyun int intel_soc_dts_iosf_add_read_only_critical_trip( 50*4882a593Smuzhiyun struct intel_soc_dts_sensors *sensors, int critical_offset); 51*4882a593Smuzhiyun #endif 52