1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * intel_soc_dts_iosf.c
4*4882a593Smuzhiyun * Copyright (c) 2015, Intel Corporation.
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/bitops.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/slab.h>
12*4882a593Smuzhiyun #include <linux/interrupt.h>
13*4882a593Smuzhiyun #include <asm/iosf_mbi.h>
14*4882a593Smuzhiyun #include "intel_soc_dts_iosf.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define SOC_DTS_OFFSET_ENABLE 0xB0
17*4882a593Smuzhiyun #define SOC_DTS_OFFSET_TEMP 0xB1
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define SOC_DTS_OFFSET_PTPS 0xB2
20*4882a593Smuzhiyun #define SOC_DTS_OFFSET_PTTS 0xB3
21*4882a593Smuzhiyun #define SOC_DTS_OFFSET_PTTSS 0xB4
22*4882a593Smuzhiyun #define SOC_DTS_OFFSET_PTMC 0x80
23*4882a593Smuzhiyun #define SOC_DTS_TE_AUX0 0xB5
24*4882a593Smuzhiyun #define SOC_DTS_TE_AUX1 0xB6
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define SOC_DTS_AUX0_ENABLE_BIT BIT(0)
27*4882a593Smuzhiyun #define SOC_DTS_AUX1_ENABLE_BIT BIT(1)
28*4882a593Smuzhiyun #define SOC_DTS_CPU_MODULE0_ENABLE_BIT BIT(16)
29*4882a593Smuzhiyun #define SOC_DTS_CPU_MODULE1_ENABLE_BIT BIT(17)
30*4882a593Smuzhiyun #define SOC_DTS_TE_SCI_ENABLE BIT(9)
31*4882a593Smuzhiyun #define SOC_DTS_TE_SMI_ENABLE BIT(10)
32*4882a593Smuzhiyun #define SOC_DTS_TE_MSI_ENABLE BIT(11)
33*4882a593Smuzhiyun #define SOC_DTS_TE_APICA_ENABLE BIT(14)
34*4882a593Smuzhiyun #define SOC_DTS_PTMC_APIC_DEASSERT_BIT BIT(4)
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* DTS encoding for TJ MAX temperature */
37*4882a593Smuzhiyun #define SOC_DTS_TJMAX_ENCODING 0x7F
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* Only 2 out of 4 is allowed for OSPM */
40*4882a593Smuzhiyun #define SOC_MAX_DTS_TRIPS 2
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /* Mask for two trips in status bits */
43*4882a593Smuzhiyun #define SOC_DTS_TRIP_MASK 0x03
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /* DTS0 and DTS 1 */
46*4882a593Smuzhiyun #define SOC_MAX_DTS_SENSORS 2
47*4882a593Smuzhiyun
get_tj_max(u32 * tj_max)48*4882a593Smuzhiyun static int get_tj_max(u32 *tj_max)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun u32 eax, edx;
51*4882a593Smuzhiyun u32 val;
52*4882a593Smuzhiyun int err;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
55*4882a593Smuzhiyun if (err)
56*4882a593Smuzhiyun goto err_ret;
57*4882a593Smuzhiyun else {
58*4882a593Smuzhiyun val = (eax >> 16) & 0xff;
59*4882a593Smuzhiyun if (val)
60*4882a593Smuzhiyun *tj_max = val * 1000;
61*4882a593Smuzhiyun else {
62*4882a593Smuzhiyun err = -EINVAL;
63*4882a593Smuzhiyun goto err_ret;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun return 0;
68*4882a593Smuzhiyun err_ret:
69*4882a593Smuzhiyun *tj_max = 0;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun return err;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
sys_get_trip_temp(struct thermal_zone_device * tzd,int trip,int * temp)74*4882a593Smuzhiyun static int sys_get_trip_temp(struct thermal_zone_device *tzd, int trip,
75*4882a593Smuzhiyun int *temp)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun int status;
78*4882a593Smuzhiyun u32 out;
79*4882a593Smuzhiyun struct intel_soc_dts_sensor_entry *dts;
80*4882a593Smuzhiyun struct intel_soc_dts_sensors *sensors;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun dts = tzd->devdata;
83*4882a593Smuzhiyun sensors = dts->sensors;
84*4882a593Smuzhiyun mutex_lock(&sensors->dts_update_lock);
85*4882a593Smuzhiyun status = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ,
86*4882a593Smuzhiyun SOC_DTS_OFFSET_PTPS, &out);
87*4882a593Smuzhiyun mutex_unlock(&sensors->dts_update_lock);
88*4882a593Smuzhiyun if (status)
89*4882a593Smuzhiyun return status;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun out = (out >> (trip * 8)) & SOC_DTS_TJMAX_ENCODING;
92*4882a593Smuzhiyun if (!out)
93*4882a593Smuzhiyun *temp = 0;
94*4882a593Smuzhiyun else
95*4882a593Smuzhiyun *temp = sensors->tj_max - out * 1000;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun return 0;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
update_trip_temp(struct intel_soc_dts_sensor_entry * dts,int thres_index,int temp,enum thermal_trip_type trip_type)100*4882a593Smuzhiyun static int update_trip_temp(struct intel_soc_dts_sensor_entry *dts,
101*4882a593Smuzhiyun int thres_index, int temp,
102*4882a593Smuzhiyun enum thermal_trip_type trip_type)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun int status;
105*4882a593Smuzhiyun u32 temp_out;
106*4882a593Smuzhiyun u32 out;
107*4882a593Smuzhiyun unsigned long update_ptps;
108*4882a593Smuzhiyun u32 store_ptps;
109*4882a593Smuzhiyun u32 store_ptmc;
110*4882a593Smuzhiyun u32 store_te_out;
111*4882a593Smuzhiyun u32 te_out;
112*4882a593Smuzhiyun u32 int_enable_bit = SOC_DTS_TE_APICA_ENABLE;
113*4882a593Smuzhiyun struct intel_soc_dts_sensors *sensors = dts->sensors;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun if (sensors->intr_type == INTEL_SOC_DTS_INTERRUPT_MSI)
116*4882a593Smuzhiyun int_enable_bit |= SOC_DTS_TE_MSI_ENABLE;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun temp_out = (sensors->tj_max - temp) / 1000;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun status = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ,
121*4882a593Smuzhiyun SOC_DTS_OFFSET_PTPS, &store_ptps);
122*4882a593Smuzhiyun if (status)
123*4882a593Smuzhiyun return status;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun update_ptps = store_ptps;
126*4882a593Smuzhiyun bitmap_set_value8(&update_ptps, temp_out & 0xFF, thres_index * 8);
127*4882a593Smuzhiyun out = update_ptps;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun status = iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE,
130*4882a593Smuzhiyun SOC_DTS_OFFSET_PTPS, out);
131*4882a593Smuzhiyun if (status)
132*4882a593Smuzhiyun return status;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun pr_debug("update_trip_temp PTPS = %x\n", out);
135*4882a593Smuzhiyun status = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ,
136*4882a593Smuzhiyun SOC_DTS_OFFSET_PTMC, &out);
137*4882a593Smuzhiyun if (status)
138*4882a593Smuzhiyun goto err_restore_ptps;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun store_ptmc = out;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun status = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ,
143*4882a593Smuzhiyun SOC_DTS_TE_AUX0 + thres_index,
144*4882a593Smuzhiyun &te_out);
145*4882a593Smuzhiyun if (status)
146*4882a593Smuzhiyun goto err_restore_ptmc;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun store_te_out = te_out;
149*4882a593Smuzhiyun /* Enable for CPU module 0 and module 1 */
150*4882a593Smuzhiyun out |= (SOC_DTS_CPU_MODULE0_ENABLE_BIT |
151*4882a593Smuzhiyun SOC_DTS_CPU_MODULE1_ENABLE_BIT);
152*4882a593Smuzhiyun if (temp) {
153*4882a593Smuzhiyun if (thres_index)
154*4882a593Smuzhiyun out |= SOC_DTS_AUX1_ENABLE_BIT;
155*4882a593Smuzhiyun else
156*4882a593Smuzhiyun out |= SOC_DTS_AUX0_ENABLE_BIT;
157*4882a593Smuzhiyun te_out |= int_enable_bit;
158*4882a593Smuzhiyun } else {
159*4882a593Smuzhiyun if (thres_index)
160*4882a593Smuzhiyun out &= ~SOC_DTS_AUX1_ENABLE_BIT;
161*4882a593Smuzhiyun else
162*4882a593Smuzhiyun out &= ~SOC_DTS_AUX0_ENABLE_BIT;
163*4882a593Smuzhiyun te_out &= ~int_enable_bit;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun status = iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE,
166*4882a593Smuzhiyun SOC_DTS_OFFSET_PTMC, out);
167*4882a593Smuzhiyun if (status)
168*4882a593Smuzhiyun goto err_restore_te_out;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun status = iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE,
171*4882a593Smuzhiyun SOC_DTS_TE_AUX0 + thres_index,
172*4882a593Smuzhiyun te_out);
173*4882a593Smuzhiyun if (status)
174*4882a593Smuzhiyun goto err_restore_te_out;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun dts->trip_types[thres_index] = trip_type;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun return 0;
179*4882a593Smuzhiyun err_restore_te_out:
180*4882a593Smuzhiyun iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE,
181*4882a593Smuzhiyun SOC_DTS_OFFSET_PTMC, store_te_out);
182*4882a593Smuzhiyun err_restore_ptmc:
183*4882a593Smuzhiyun iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE,
184*4882a593Smuzhiyun SOC_DTS_OFFSET_PTMC, store_ptmc);
185*4882a593Smuzhiyun err_restore_ptps:
186*4882a593Smuzhiyun iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE,
187*4882a593Smuzhiyun SOC_DTS_OFFSET_PTPS, store_ptps);
188*4882a593Smuzhiyun /* Nothing we can do if restore fails */
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun return status;
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun
sys_set_trip_temp(struct thermal_zone_device * tzd,int trip,int temp)193*4882a593Smuzhiyun static int sys_set_trip_temp(struct thermal_zone_device *tzd, int trip,
194*4882a593Smuzhiyun int temp)
195*4882a593Smuzhiyun {
196*4882a593Smuzhiyun struct intel_soc_dts_sensor_entry *dts = tzd->devdata;
197*4882a593Smuzhiyun struct intel_soc_dts_sensors *sensors = dts->sensors;
198*4882a593Smuzhiyun int status;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun if (temp > sensors->tj_max)
201*4882a593Smuzhiyun return -EINVAL;
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun mutex_lock(&sensors->dts_update_lock);
204*4882a593Smuzhiyun status = update_trip_temp(tzd->devdata, trip, temp,
205*4882a593Smuzhiyun dts->trip_types[trip]);
206*4882a593Smuzhiyun mutex_unlock(&sensors->dts_update_lock);
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun return status;
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun
sys_get_trip_type(struct thermal_zone_device * tzd,int trip,enum thermal_trip_type * type)211*4882a593Smuzhiyun static int sys_get_trip_type(struct thermal_zone_device *tzd,
212*4882a593Smuzhiyun int trip, enum thermal_trip_type *type)
213*4882a593Smuzhiyun {
214*4882a593Smuzhiyun struct intel_soc_dts_sensor_entry *dts;
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun dts = tzd->devdata;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun *type = dts->trip_types[trip];
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun return 0;
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun
sys_get_curr_temp(struct thermal_zone_device * tzd,int * temp)223*4882a593Smuzhiyun static int sys_get_curr_temp(struct thermal_zone_device *tzd,
224*4882a593Smuzhiyun int *temp)
225*4882a593Smuzhiyun {
226*4882a593Smuzhiyun int status;
227*4882a593Smuzhiyun u32 out;
228*4882a593Smuzhiyun struct intel_soc_dts_sensor_entry *dts;
229*4882a593Smuzhiyun struct intel_soc_dts_sensors *sensors;
230*4882a593Smuzhiyun unsigned long raw;
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun dts = tzd->devdata;
233*4882a593Smuzhiyun sensors = dts->sensors;
234*4882a593Smuzhiyun status = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ,
235*4882a593Smuzhiyun SOC_DTS_OFFSET_TEMP, &out);
236*4882a593Smuzhiyun if (status)
237*4882a593Smuzhiyun return status;
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun raw = out;
240*4882a593Smuzhiyun out = bitmap_get_value8(&raw, dts->id * 8) - SOC_DTS_TJMAX_ENCODING;
241*4882a593Smuzhiyun *temp = sensors->tj_max - out * 1000;
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun return 0;
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun static struct thermal_zone_device_ops tzone_ops = {
247*4882a593Smuzhiyun .get_temp = sys_get_curr_temp,
248*4882a593Smuzhiyun .get_trip_temp = sys_get_trip_temp,
249*4882a593Smuzhiyun .get_trip_type = sys_get_trip_type,
250*4882a593Smuzhiyun .set_trip_temp = sys_set_trip_temp,
251*4882a593Smuzhiyun };
252*4882a593Smuzhiyun
soc_dts_enable(int id)253*4882a593Smuzhiyun static int soc_dts_enable(int id)
254*4882a593Smuzhiyun {
255*4882a593Smuzhiyun u32 out;
256*4882a593Smuzhiyun int ret;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun ret = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ,
259*4882a593Smuzhiyun SOC_DTS_OFFSET_ENABLE, &out);
260*4882a593Smuzhiyun if (ret)
261*4882a593Smuzhiyun return ret;
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun if (!(out & BIT(id))) {
264*4882a593Smuzhiyun out |= BIT(id);
265*4882a593Smuzhiyun ret = iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE,
266*4882a593Smuzhiyun SOC_DTS_OFFSET_ENABLE, out);
267*4882a593Smuzhiyun if (ret)
268*4882a593Smuzhiyun return ret;
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun return ret;
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun
remove_dts_thermal_zone(struct intel_soc_dts_sensor_entry * dts)274*4882a593Smuzhiyun static void remove_dts_thermal_zone(struct intel_soc_dts_sensor_entry *dts)
275*4882a593Smuzhiyun {
276*4882a593Smuzhiyun if (dts) {
277*4882a593Smuzhiyun iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE,
278*4882a593Smuzhiyun SOC_DTS_OFFSET_ENABLE, dts->store_status);
279*4882a593Smuzhiyun thermal_zone_device_unregister(dts->tzone);
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun
add_dts_thermal_zone(int id,struct intel_soc_dts_sensor_entry * dts,bool notification_support,int trip_cnt,int read_only_trip_cnt)283*4882a593Smuzhiyun static int add_dts_thermal_zone(int id, struct intel_soc_dts_sensor_entry *dts,
284*4882a593Smuzhiyun bool notification_support, int trip_cnt,
285*4882a593Smuzhiyun int read_only_trip_cnt)
286*4882a593Smuzhiyun {
287*4882a593Smuzhiyun char name[10];
288*4882a593Smuzhiyun unsigned long trip;
289*4882a593Smuzhiyun int trip_count = 0;
290*4882a593Smuzhiyun int trip_mask = 0;
291*4882a593Smuzhiyun int writable_trip_cnt = 0;
292*4882a593Smuzhiyun unsigned long ptps;
293*4882a593Smuzhiyun u32 store_ptps;
294*4882a593Smuzhiyun unsigned long i;
295*4882a593Smuzhiyun int ret;
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun /* Store status to restor on exit */
298*4882a593Smuzhiyun ret = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ,
299*4882a593Smuzhiyun SOC_DTS_OFFSET_ENABLE, &dts->store_status);
300*4882a593Smuzhiyun if (ret)
301*4882a593Smuzhiyun goto err_ret;
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun dts->id = id;
304*4882a593Smuzhiyun if (notification_support) {
305*4882a593Smuzhiyun trip_count = min(SOC_MAX_DTS_TRIPS, trip_cnt);
306*4882a593Smuzhiyun writable_trip_cnt = trip_count - read_only_trip_cnt;
307*4882a593Smuzhiyun trip_mask = GENMASK(writable_trip_cnt - 1, 0);
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun /* Check if the writable trip we provide is not used by BIOS */
311*4882a593Smuzhiyun ret = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ,
312*4882a593Smuzhiyun SOC_DTS_OFFSET_PTPS, &store_ptps);
313*4882a593Smuzhiyun if (ret)
314*4882a593Smuzhiyun trip_mask = 0;
315*4882a593Smuzhiyun else {
316*4882a593Smuzhiyun ptps = store_ptps;
317*4882a593Smuzhiyun for_each_set_clump8(i, trip, &ptps, writable_trip_cnt * 8)
318*4882a593Smuzhiyun trip_mask &= ~BIT(i / 8);
319*4882a593Smuzhiyun }
320*4882a593Smuzhiyun dts->trip_mask = trip_mask;
321*4882a593Smuzhiyun dts->trip_count = trip_count;
322*4882a593Smuzhiyun snprintf(name, sizeof(name), "soc_dts%d", id);
323*4882a593Smuzhiyun dts->tzone = thermal_zone_device_register(name,
324*4882a593Smuzhiyun trip_count,
325*4882a593Smuzhiyun trip_mask,
326*4882a593Smuzhiyun dts, &tzone_ops,
327*4882a593Smuzhiyun NULL, 0, 0);
328*4882a593Smuzhiyun if (IS_ERR(dts->tzone)) {
329*4882a593Smuzhiyun ret = PTR_ERR(dts->tzone);
330*4882a593Smuzhiyun goto err_ret;
331*4882a593Smuzhiyun }
332*4882a593Smuzhiyun ret = thermal_zone_device_enable(dts->tzone);
333*4882a593Smuzhiyun if (ret)
334*4882a593Smuzhiyun goto err_enable;
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun ret = soc_dts_enable(id);
337*4882a593Smuzhiyun if (ret)
338*4882a593Smuzhiyun goto err_enable;
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun return 0;
341*4882a593Smuzhiyun err_enable:
342*4882a593Smuzhiyun thermal_zone_device_unregister(dts->tzone);
343*4882a593Smuzhiyun err_ret:
344*4882a593Smuzhiyun return ret;
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun
intel_soc_dts_iosf_add_read_only_critical_trip(struct intel_soc_dts_sensors * sensors,int critical_offset)347*4882a593Smuzhiyun int intel_soc_dts_iosf_add_read_only_critical_trip(
348*4882a593Smuzhiyun struct intel_soc_dts_sensors *sensors, int critical_offset)
349*4882a593Smuzhiyun {
350*4882a593Smuzhiyun int i, j;
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i) {
353*4882a593Smuzhiyun for (j = 0; j < sensors->soc_dts[i].trip_count; ++j) {
354*4882a593Smuzhiyun if (!(sensors->soc_dts[i].trip_mask & BIT(j))) {
355*4882a593Smuzhiyun return update_trip_temp(&sensors->soc_dts[i], j,
356*4882a593Smuzhiyun sensors->tj_max - critical_offset,
357*4882a593Smuzhiyun THERMAL_TRIP_CRITICAL);
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun }
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun return -EINVAL;
363*4882a593Smuzhiyun }
364*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(intel_soc_dts_iosf_add_read_only_critical_trip);
365*4882a593Smuzhiyun
intel_soc_dts_iosf_interrupt_handler(struct intel_soc_dts_sensors * sensors)366*4882a593Smuzhiyun void intel_soc_dts_iosf_interrupt_handler(struct intel_soc_dts_sensors *sensors)
367*4882a593Smuzhiyun {
368*4882a593Smuzhiyun u32 sticky_out;
369*4882a593Smuzhiyun int status;
370*4882a593Smuzhiyun u32 ptmc_out;
371*4882a593Smuzhiyun unsigned long flags;
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun spin_lock_irqsave(&sensors->intr_notify_lock, flags);
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun status = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ,
376*4882a593Smuzhiyun SOC_DTS_OFFSET_PTMC, &ptmc_out);
377*4882a593Smuzhiyun ptmc_out |= SOC_DTS_PTMC_APIC_DEASSERT_BIT;
378*4882a593Smuzhiyun status = iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE,
379*4882a593Smuzhiyun SOC_DTS_OFFSET_PTMC, ptmc_out);
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun status = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ,
382*4882a593Smuzhiyun SOC_DTS_OFFSET_PTTSS, &sticky_out);
383*4882a593Smuzhiyun pr_debug("status %d PTTSS %x\n", status, sticky_out);
384*4882a593Smuzhiyun if (sticky_out & SOC_DTS_TRIP_MASK) {
385*4882a593Smuzhiyun int i;
386*4882a593Smuzhiyun /* reset sticky bit */
387*4882a593Smuzhiyun status = iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE,
388*4882a593Smuzhiyun SOC_DTS_OFFSET_PTTSS, sticky_out);
389*4882a593Smuzhiyun spin_unlock_irqrestore(&sensors->intr_notify_lock, flags);
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i) {
392*4882a593Smuzhiyun pr_debug("TZD update for zone %d\n", i);
393*4882a593Smuzhiyun thermal_zone_device_update(sensors->soc_dts[i].tzone,
394*4882a593Smuzhiyun THERMAL_EVENT_UNSPECIFIED);
395*4882a593Smuzhiyun }
396*4882a593Smuzhiyun } else
397*4882a593Smuzhiyun spin_unlock_irqrestore(&sensors->intr_notify_lock, flags);
398*4882a593Smuzhiyun }
399*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(intel_soc_dts_iosf_interrupt_handler);
400*4882a593Smuzhiyun
intel_soc_dts_iosf_init(enum intel_soc_dts_interrupt_type intr_type,int trip_count,int read_only_trip_count)401*4882a593Smuzhiyun struct intel_soc_dts_sensors *intel_soc_dts_iosf_init(
402*4882a593Smuzhiyun enum intel_soc_dts_interrupt_type intr_type, int trip_count,
403*4882a593Smuzhiyun int read_only_trip_count)
404*4882a593Smuzhiyun {
405*4882a593Smuzhiyun struct intel_soc_dts_sensors *sensors;
406*4882a593Smuzhiyun bool notification;
407*4882a593Smuzhiyun u32 tj_max;
408*4882a593Smuzhiyun int ret;
409*4882a593Smuzhiyun int i;
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun if (!iosf_mbi_available())
412*4882a593Smuzhiyun return ERR_PTR(-ENODEV);
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun if (!trip_count || read_only_trip_count > trip_count)
415*4882a593Smuzhiyun return ERR_PTR(-EINVAL);
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun if (get_tj_max(&tj_max))
418*4882a593Smuzhiyun return ERR_PTR(-EINVAL);
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun sensors = kzalloc(sizeof(*sensors), GFP_KERNEL);
421*4882a593Smuzhiyun if (!sensors)
422*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun spin_lock_init(&sensors->intr_notify_lock);
425*4882a593Smuzhiyun mutex_init(&sensors->dts_update_lock);
426*4882a593Smuzhiyun sensors->intr_type = intr_type;
427*4882a593Smuzhiyun sensors->tj_max = tj_max;
428*4882a593Smuzhiyun if (intr_type == INTEL_SOC_DTS_INTERRUPT_NONE)
429*4882a593Smuzhiyun notification = false;
430*4882a593Smuzhiyun else
431*4882a593Smuzhiyun notification = true;
432*4882a593Smuzhiyun for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i) {
433*4882a593Smuzhiyun sensors->soc_dts[i].sensors = sensors;
434*4882a593Smuzhiyun ret = add_dts_thermal_zone(i, &sensors->soc_dts[i],
435*4882a593Smuzhiyun notification, trip_count,
436*4882a593Smuzhiyun read_only_trip_count);
437*4882a593Smuzhiyun if (ret)
438*4882a593Smuzhiyun goto err_free;
439*4882a593Smuzhiyun }
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i) {
442*4882a593Smuzhiyun ret = update_trip_temp(&sensors->soc_dts[i], 0, 0,
443*4882a593Smuzhiyun THERMAL_TRIP_PASSIVE);
444*4882a593Smuzhiyun if (ret)
445*4882a593Smuzhiyun goto err_remove_zone;
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun ret = update_trip_temp(&sensors->soc_dts[i], 1, 0,
448*4882a593Smuzhiyun THERMAL_TRIP_PASSIVE);
449*4882a593Smuzhiyun if (ret)
450*4882a593Smuzhiyun goto err_remove_zone;
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun return sensors;
454*4882a593Smuzhiyun err_remove_zone:
455*4882a593Smuzhiyun for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i)
456*4882a593Smuzhiyun remove_dts_thermal_zone(&sensors->soc_dts[i]);
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun err_free:
459*4882a593Smuzhiyun kfree(sensors);
460*4882a593Smuzhiyun return ERR_PTR(ret);
461*4882a593Smuzhiyun }
462*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(intel_soc_dts_iosf_init);
463*4882a593Smuzhiyun
intel_soc_dts_iosf_exit(struct intel_soc_dts_sensors * sensors)464*4882a593Smuzhiyun void intel_soc_dts_iosf_exit(struct intel_soc_dts_sensors *sensors)
465*4882a593Smuzhiyun {
466*4882a593Smuzhiyun int i;
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i) {
469*4882a593Smuzhiyun update_trip_temp(&sensors->soc_dts[i], 0, 0, 0);
470*4882a593Smuzhiyun update_trip_temp(&sensors->soc_dts[i], 1, 0, 0);
471*4882a593Smuzhiyun remove_dts_thermal_zone(&sensors->soc_dts[i]);
472*4882a593Smuzhiyun }
473*4882a593Smuzhiyun kfree(sensors);
474*4882a593Smuzhiyun }
475*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(intel_soc_dts_iosf_exit);
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
478