1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2020 NXP.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Anson Huang <Anson.Huang@nxp.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/bitfield.h>
9*4882a593Smuzhiyun #include <linux/clk.h>
10*4882a593Smuzhiyun #include <linux/err.h>
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/of.h>
14*4882a593Smuzhiyun #include <linux/of_device.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/thermal.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include "thermal_core.h"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define TER 0x0 /* TMU enable */
21*4882a593Smuzhiyun #define TPS 0x4
22*4882a593Smuzhiyun #define TRITSR 0x20 /* TMU immediate temp */
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define TER_ADC_PD BIT(30)
25*4882a593Smuzhiyun #define TER_EN BIT(31)
26*4882a593Smuzhiyun #define TRITSR_TEMP0_VAL_MASK 0xff
27*4882a593Smuzhiyun #define TRITSR_TEMP1_VAL_MASK 0xff0000
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define PROBE_SEL_ALL GENMASK(31, 30)
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define probe_status_offset(x) (30 + x)
32*4882a593Smuzhiyun #define SIGN_BIT BIT(7)
33*4882a593Smuzhiyun #define TEMP_VAL_MASK GENMASK(6, 0)
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #define VER1_TEMP_LOW_LIMIT 10000
36*4882a593Smuzhiyun #define VER2_TEMP_LOW_LIMIT -40000
37*4882a593Smuzhiyun #define VER2_TEMP_HIGH_LIMIT 125000
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define TMU_VER1 0x1
40*4882a593Smuzhiyun #define TMU_VER2 0x2
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun struct thermal_soc_data {
43*4882a593Smuzhiyun u32 num_sensors;
44*4882a593Smuzhiyun u32 version;
45*4882a593Smuzhiyun int (*get_temp)(void *, int *);
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun struct tmu_sensor {
49*4882a593Smuzhiyun struct imx8mm_tmu *priv;
50*4882a593Smuzhiyun u32 hw_id;
51*4882a593Smuzhiyun struct thermal_zone_device *tzd;
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun struct imx8mm_tmu {
55*4882a593Smuzhiyun void __iomem *base;
56*4882a593Smuzhiyun struct clk *clk;
57*4882a593Smuzhiyun const struct thermal_soc_data *socdata;
58*4882a593Smuzhiyun struct tmu_sensor sensors[];
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
imx8mm_tmu_get_temp(void * data,int * temp)61*4882a593Smuzhiyun static int imx8mm_tmu_get_temp(void *data, int *temp)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun struct tmu_sensor *sensor = data;
64*4882a593Smuzhiyun struct imx8mm_tmu *tmu = sensor->priv;
65*4882a593Smuzhiyun u32 val;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun val = readl_relaxed(tmu->base + TRITSR) & TRITSR_TEMP0_VAL_MASK;
68*4882a593Smuzhiyun *temp = val * 1000;
69*4882a593Smuzhiyun if (*temp < VER1_TEMP_LOW_LIMIT)
70*4882a593Smuzhiyun return -EAGAIN;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun return 0;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
imx8mp_tmu_get_temp(void * data,int * temp)75*4882a593Smuzhiyun static int imx8mp_tmu_get_temp(void *data, int *temp)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun struct tmu_sensor *sensor = data;
78*4882a593Smuzhiyun struct imx8mm_tmu *tmu = sensor->priv;
79*4882a593Smuzhiyun unsigned long val;
80*4882a593Smuzhiyun bool ready;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun val = readl_relaxed(tmu->base + TRITSR);
83*4882a593Smuzhiyun ready = test_bit(probe_status_offset(sensor->hw_id), &val);
84*4882a593Smuzhiyun if (!ready)
85*4882a593Smuzhiyun return -EAGAIN;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun val = sensor->hw_id ? FIELD_GET(TRITSR_TEMP1_VAL_MASK, val) :
88*4882a593Smuzhiyun FIELD_GET(TRITSR_TEMP0_VAL_MASK, val);
89*4882a593Smuzhiyun if (val & SIGN_BIT) /* negative */
90*4882a593Smuzhiyun val = (~(val & TEMP_VAL_MASK) + 1);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun *temp = val * 1000;
93*4882a593Smuzhiyun if (*temp < VER2_TEMP_LOW_LIMIT || *temp > VER2_TEMP_HIGH_LIMIT)
94*4882a593Smuzhiyun return -EAGAIN;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun return 0;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
tmu_get_temp(void * data,int * temp)99*4882a593Smuzhiyun static int tmu_get_temp(void *data, int *temp)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun struct tmu_sensor *sensor = data;
102*4882a593Smuzhiyun struct imx8mm_tmu *tmu = sensor->priv;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun return tmu->socdata->get_temp(data, temp);
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun static struct thermal_zone_of_device_ops tmu_tz_ops = {
108*4882a593Smuzhiyun .get_temp = tmu_get_temp,
109*4882a593Smuzhiyun };
110*4882a593Smuzhiyun
imx8mm_tmu_enable(struct imx8mm_tmu * tmu,bool enable)111*4882a593Smuzhiyun static void imx8mm_tmu_enable(struct imx8mm_tmu *tmu, bool enable)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun u32 val;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun val = readl_relaxed(tmu->base + TER);
116*4882a593Smuzhiyun val = enable ? (val | TER_EN) : (val & ~TER_EN);
117*4882a593Smuzhiyun if (tmu->socdata->version == TMU_VER2)
118*4882a593Smuzhiyun val = enable ? (val & ~TER_ADC_PD) : (val | TER_ADC_PD);
119*4882a593Smuzhiyun writel_relaxed(val, tmu->base + TER);
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
imx8mm_tmu_probe_sel_all(struct imx8mm_tmu * tmu)122*4882a593Smuzhiyun static void imx8mm_tmu_probe_sel_all(struct imx8mm_tmu *tmu)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun u32 val;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun val = readl_relaxed(tmu->base + TPS);
127*4882a593Smuzhiyun val |= PROBE_SEL_ALL;
128*4882a593Smuzhiyun writel_relaxed(val, tmu->base + TPS);
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
imx8mm_tmu_probe(struct platform_device * pdev)131*4882a593Smuzhiyun static int imx8mm_tmu_probe(struct platform_device *pdev)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun const struct thermal_soc_data *data;
134*4882a593Smuzhiyun struct imx8mm_tmu *tmu;
135*4882a593Smuzhiyun int ret;
136*4882a593Smuzhiyun int i;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun data = of_device_get_match_data(&pdev->dev);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun tmu = devm_kzalloc(&pdev->dev, struct_size(tmu, sensors,
141*4882a593Smuzhiyun data->num_sensors), GFP_KERNEL);
142*4882a593Smuzhiyun if (!tmu)
143*4882a593Smuzhiyun return -ENOMEM;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun tmu->socdata = data;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun tmu->base = devm_platform_ioremap_resource(pdev, 0);
148*4882a593Smuzhiyun if (IS_ERR(tmu->base))
149*4882a593Smuzhiyun return PTR_ERR(tmu->base);
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun tmu->clk = devm_clk_get(&pdev->dev, NULL);
152*4882a593Smuzhiyun if (IS_ERR(tmu->clk))
153*4882a593Smuzhiyun return dev_err_probe(&pdev->dev, PTR_ERR(tmu->clk),
154*4882a593Smuzhiyun "failed to get tmu clock\n");
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun ret = clk_prepare_enable(tmu->clk);
157*4882a593Smuzhiyun if (ret) {
158*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to enable tmu clock: %d\n", ret);
159*4882a593Smuzhiyun return ret;
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun /* disable the monitor during initialization */
163*4882a593Smuzhiyun imx8mm_tmu_enable(tmu, false);
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun for (i = 0; i < data->num_sensors; i++) {
166*4882a593Smuzhiyun tmu->sensors[i].priv = tmu;
167*4882a593Smuzhiyun tmu->sensors[i].tzd =
168*4882a593Smuzhiyun devm_thermal_zone_of_sensor_register(&pdev->dev, i,
169*4882a593Smuzhiyun &tmu->sensors[i],
170*4882a593Smuzhiyun &tmu_tz_ops);
171*4882a593Smuzhiyun if (IS_ERR(tmu->sensors[i].tzd)) {
172*4882a593Smuzhiyun dev_err(&pdev->dev,
173*4882a593Smuzhiyun "failed to register thermal zone sensor[%d]: %d\n",
174*4882a593Smuzhiyun i, ret);
175*4882a593Smuzhiyun return PTR_ERR(tmu->sensors[i].tzd);
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun tmu->sensors[i].hw_id = i;
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun platform_set_drvdata(pdev, tmu);
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun /* enable all the probes for V2 TMU */
183*4882a593Smuzhiyun if (tmu->socdata->version == TMU_VER2)
184*4882a593Smuzhiyun imx8mm_tmu_probe_sel_all(tmu);
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun /* enable the monitor */
187*4882a593Smuzhiyun imx8mm_tmu_enable(tmu, true);
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun return 0;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
imx8mm_tmu_remove(struct platform_device * pdev)192*4882a593Smuzhiyun static int imx8mm_tmu_remove(struct platform_device *pdev)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun struct imx8mm_tmu *tmu = platform_get_drvdata(pdev);
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun /* disable TMU */
197*4882a593Smuzhiyun imx8mm_tmu_enable(tmu, false);
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun clk_disable_unprepare(tmu->clk);
200*4882a593Smuzhiyun platform_set_drvdata(pdev, NULL);
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun return 0;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun static struct thermal_soc_data imx8mm_tmu_data = {
206*4882a593Smuzhiyun .num_sensors = 1,
207*4882a593Smuzhiyun .version = TMU_VER1,
208*4882a593Smuzhiyun .get_temp = imx8mm_tmu_get_temp,
209*4882a593Smuzhiyun };
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun static struct thermal_soc_data imx8mp_tmu_data = {
212*4882a593Smuzhiyun .num_sensors = 2,
213*4882a593Smuzhiyun .version = TMU_VER2,
214*4882a593Smuzhiyun .get_temp = imx8mp_tmu_get_temp,
215*4882a593Smuzhiyun };
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun static const struct of_device_id imx8mm_tmu_table[] = {
218*4882a593Smuzhiyun { .compatible = "fsl,imx8mm-tmu", .data = &imx8mm_tmu_data, },
219*4882a593Smuzhiyun { .compatible = "fsl,imx8mp-tmu", .data = &imx8mp_tmu_data, },
220*4882a593Smuzhiyun { },
221*4882a593Smuzhiyun };
222*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, imx8mm_tmu_table);
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun static struct platform_driver imx8mm_tmu = {
225*4882a593Smuzhiyun .driver = {
226*4882a593Smuzhiyun .name = "i.mx8mm_thermal",
227*4882a593Smuzhiyun .of_match_table = imx8mm_tmu_table,
228*4882a593Smuzhiyun },
229*4882a593Smuzhiyun .probe = imx8mm_tmu_probe,
230*4882a593Smuzhiyun .remove = imx8mm_tmu_remove,
231*4882a593Smuzhiyun };
232*4882a593Smuzhiyun module_platform_driver(imx8mm_tmu);
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
235*4882a593Smuzhiyun MODULE_DESCRIPTION("i.MX8MM Thermal Monitor Unit driver");
236*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
237