1*4882a593Smuzhiyun // SPDX-License-Identifier: MIT
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2019 Advanced Micro Devices, Inc.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/slab.h>
7*4882a593Smuzhiyun #include <linux/tee_drv.h>
8*4882a593Smuzhiyun #include <linux/psp-sev.h>
9*4882a593Smuzhiyun #include "amdtee_private.h"
10*4882a593Smuzhiyun
pool_op_alloc(struct tee_shm_pool_mgr * poolm,struct tee_shm * shm,size_t size)11*4882a593Smuzhiyun static int pool_op_alloc(struct tee_shm_pool_mgr *poolm, struct tee_shm *shm,
12*4882a593Smuzhiyun size_t size)
13*4882a593Smuzhiyun {
14*4882a593Smuzhiyun unsigned int order = get_order(size);
15*4882a593Smuzhiyun unsigned long va;
16*4882a593Smuzhiyun int rc;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun va = __get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
19*4882a593Smuzhiyun if (!va)
20*4882a593Smuzhiyun return -ENOMEM;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun shm->kaddr = (void *)va;
23*4882a593Smuzhiyun shm->paddr = __psp_pa((void *)va);
24*4882a593Smuzhiyun shm->size = PAGE_SIZE << order;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* Map the allocated memory in to TEE */
27*4882a593Smuzhiyun rc = amdtee_map_shmem(shm);
28*4882a593Smuzhiyun if (rc) {
29*4882a593Smuzhiyun free_pages(va, order);
30*4882a593Smuzhiyun shm->kaddr = NULL;
31*4882a593Smuzhiyun return rc;
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun return 0;
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
pool_op_free(struct tee_shm_pool_mgr * poolm,struct tee_shm * shm)37*4882a593Smuzhiyun static void pool_op_free(struct tee_shm_pool_mgr *poolm, struct tee_shm *shm)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun /* Unmap the shared memory from TEE */
40*4882a593Smuzhiyun amdtee_unmap_shmem(shm);
41*4882a593Smuzhiyun free_pages((unsigned long)shm->kaddr, get_order(shm->size));
42*4882a593Smuzhiyun shm->kaddr = NULL;
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
pool_op_destroy_poolmgr(struct tee_shm_pool_mgr * poolm)45*4882a593Smuzhiyun static void pool_op_destroy_poolmgr(struct tee_shm_pool_mgr *poolm)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun kfree(poolm);
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun static const struct tee_shm_pool_mgr_ops pool_ops = {
51*4882a593Smuzhiyun .alloc = pool_op_alloc,
52*4882a593Smuzhiyun .free = pool_op_free,
53*4882a593Smuzhiyun .destroy_poolmgr = pool_op_destroy_poolmgr,
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun
pool_mem_mgr_alloc(void)56*4882a593Smuzhiyun static struct tee_shm_pool_mgr *pool_mem_mgr_alloc(void)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun struct tee_shm_pool_mgr *mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun if (!mgr)
61*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun mgr->ops = &pool_ops;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun return mgr;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
amdtee_config_shm(void)68*4882a593Smuzhiyun struct tee_shm_pool *amdtee_config_shm(void)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun struct tee_shm_pool_mgr *priv_mgr;
71*4882a593Smuzhiyun struct tee_shm_pool_mgr *dmabuf_mgr;
72*4882a593Smuzhiyun void *rc;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun rc = pool_mem_mgr_alloc();
75*4882a593Smuzhiyun if (IS_ERR(rc))
76*4882a593Smuzhiyun return rc;
77*4882a593Smuzhiyun priv_mgr = rc;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun rc = pool_mem_mgr_alloc();
80*4882a593Smuzhiyun if (IS_ERR(rc)) {
81*4882a593Smuzhiyun tee_shm_pool_mgr_destroy(priv_mgr);
82*4882a593Smuzhiyun return rc;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun dmabuf_mgr = rc;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun rc = tee_shm_pool_alloc(priv_mgr, dmabuf_mgr);
87*4882a593Smuzhiyun if (IS_ERR(rc)) {
88*4882a593Smuzhiyun tee_shm_pool_mgr_destroy(priv_mgr);
89*4882a593Smuzhiyun tee_shm_pool_mgr_destroy(dmabuf_mgr);
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun return rc;
93*4882a593Smuzhiyun }
94