1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * NXP SC18IS602/603 SPI driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) Guenter Roeck <linux@roeck-us.net>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/err.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/spi/spi.h>
12*4882a593Smuzhiyun #include <linux/i2c.h>
13*4882a593Smuzhiyun #include <linux/delay.h>
14*4882a593Smuzhiyun #include <linux/pm_runtime.h>
15*4882a593Smuzhiyun #include <linux/of_device.h>
16*4882a593Smuzhiyun #include <linux/of.h>
17*4882a593Smuzhiyun #include <linux/platform_data/sc18is602.h>
18*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun enum chips { sc18is602, sc18is602b, sc18is603 };
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define SC18IS602_BUFSIZ 200
23*4882a593Smuzhiyun #define SC18IS602_CLOCK 7372000
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define SC18IS602_MODE_CPHA BIT(2)
26*4882a593Smuzhiyun #define SC18IS602_MODE_CPOL BIT(3)
27*4882a593Smuzhiyun #define SC18IS602_MODE_LSB_FIRST BIT(5)
28*4882a593Smuzhiyun #define SC18IS602_MODE_CLOCK_DIV_4 0x0
29*4882a593Smuzhiyun #define SC18IS602_MODE_CLOCK_DIV_16 0x1
30*4882a593Smuzhiyun #define SC18IS602_MODE_CLOCK_DIV_64 0x2
31*4882a593Smuzhiyun #define SC18IS602_MODE_CLOCK_DIV_128 0x3
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun struct sc18is602 {
34*4882a593Smuzhiyun struct spi_master *master;
35*4882a593Smuzhiyun struct device *dev;
36*4882a593Smuzhiyun u8 ctrl;
37*4882a593Smuzhiyun u32 freq;
38*4882a593Smuzhiyun u32 speed;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* I2C data */
41*4882a593Smuzhiyun struct i2c_client *client;
42*4882a593Smuzhiyun enum chips id;
43*4882a593Smuzhiyun u8 buffer[SC18IS602_BUFSIZ + 1];
44*4882a593Smuzhiyun int tlen; /* Data queued for tx in buffer */
45*4882a593Smuzhiyun int rindex; /* Receive data index in buffer */
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun struct gpio_desc *reset;
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
sc18is602_wait_ready(struct sc18is602 * hw,int len)50*4882a593Smuzhiyun static int sc18is602_wait_ready(struct sc18is602 *hw, int len)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun int i, err;
53*4882a593Smuzhiyun int usecs = 1000000 * len / hw->speed + 1;
54*4882a593Smuzhiyun u8 dummy[1];
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun for (i = 0; i < 10; i++) {
57*4882a593Smuzhiyun err = i2c_master_recv(hw->client, dummy, 1);
58*4882a593Smuzhiyun if (err >= 0)
59*4882a593Smuzhiyun return 0;
60*4882a593Smuzhiyun usleep_range(usecs, usecs * 2);
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun return -ETIMEDOUT;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
sc18is602_txrx(struct sc18is602 * hw,struct spi_message * msg,struct spi_transfer * t,bool do_transfer)65*4882a593Smuzhiyun static int sc18is602_txrx(struct sc18is602 *hw, struct spi_message *msg,
66*4882a593Smuzhiyun struct spi_transfer *t, bool do_transfer)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun unsigned int len = t->len;
69*4882a593Smuzhiyun int ret;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun if (hw->tlen == 0) {
72*4882a593Smuzhiyun /* First byte (I2C command) is chip select */
73*4882a593Smuzhiyun hw->buffer[0] = 1 << msg->spi->chip_select;
74*4882a593Smuzhiyun hw->tlen = 1;
75*4882a593Smuzhiyun hw->rindex = 0;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun /*
78*4882a593Smuzhiyun * We can not immediately send data to the chip, since each I2C message
79*4882a593Smuzhiyun * resembles a full SPI message (from CS active to CS inactive).
80*4882a593Smuzhiyun * Enqueue messages up to the first read or until do_transfer is true.
81*4882a593Smuzhiyun */
82*4882a593Smuzhiyun if (t->tx_buf) {
83*4882a593Smuzhiyun memcpy(&hw->buffer[hw->tlen], t->tx_buf, len);
84*4882a593Smuzhiyun hw->tlen += len;
85*4882a593Smuzhiyun if (t->rx_buf)
86*4882a593Smuzhiyun do_transfer = true;
87*4882a593Smuzhiyun else
88*4882a593Smuzhiyun hw->rindex = hw->tlen - 1;
89*4882a593Smuzhiyun } else if (t->rx_buf) {
90*4882a593Smuzhiyun /*
91*4882a593Smuzhiyun * For receive-only transfers we still need to perform a dummy
92*4882a593Smuzhiyun * write to receive data from the SPI chip.
93*4882a593Smuzhiyun * Read data starts at the end of transmit data (minus 1 to
94*4882a593Smuzhiyun * account for CS).
95*4882a593Smuzhiyun */
96*4882a593Smuzhiyun hw->rindex = hw->tlen - 1;
97*4882a593Smuzhiyun memset(&hw->buffer[hw->tlen], 0, len);
98*4882a593Smuzhiyun hw->tlen += len;
99*4882a593Smuzhiyun do_transfer = true;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun if (do_transfer && hw->tlen > 1) {
103*4882a593Smuzhiyun ret = sc18is602_wait_ready(hw, SC18IS602_BUFSIZ);
104*4882a593Smuzhiyun if (ret < 0)
105*4882a593Smuzhiyun return ret;
106*4882a593Smuzhiyun ret = i2c_master_send(hw->client, hw->buffer, hw->tlen);
107*4882a593Smuzhiyun if (ret < 0)
108*4882a593Smuzhiyun return ret;
109*4882a593Smuzhiyun if (ret != hw->tlen)
110*4882a593Smuzhiyun return -EIO;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun if (t->rx_buf) {
113*4882a593Smuzhiyun int rlen = hw->rindex + len;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun ret = sc18is602_wait_ready(hw, hw->tlen);
116*4882a593Smuzhiyun if (ret < 0)
117*4882a593Smuzhiyun return ret;
118*4882a593Smuzhiyun ret = i2c_master_recv(hw->client, hw->buffer, rlen);
119*4882a593Smuzhiyun if (ret < 0)
120*4882a593Smuzhiyun return ret;
121*4882a593Smuzhiyun if (ret != rlen)
122*4882a593Smuzhiyun return -EIO;
123*4882a593Smuzhiyun memcpy(t->rx_buf, &hw->buffer[hw->rindex], len);
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun hw->tlen = 0;
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun return len;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
sc18is602_setup_transfer(struct sc18is602 * hw,u32 hz,u8 mode)130*4882a593Smuzhiyun static int sc18is602_setup_transfer(struct sc18is602 *hw, u32 hz, u8 mode)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun u8 ctrl = 0;
133*4882a593Smuzhiyun int ret;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun if (mode & SPI_CPHA)
136*4882a593Smuzhiyun ctrl |= SC18IS602_MODE_CPHA;
137*4882a593Smuzhiyun if (mode & SPI_CPOL)
138*4882a593Smuzhiyun ctrl |= SC18IS602_MODE_CPOL;
139*4882a593Smuzhiyun if (mode & SPI_LSB_FIRST)
140*4882a593Smuzhiyun ctrl |= SC18IS602_MODE_LSB_FIRST;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun /* Find the closest clock speed */
143*4882a593Smuzhiyun if (hz >= hw->freq / 4) {
144*4882a593Smuzhiyun ctrl |= SC18IS602_MODE_CLOCK_DIV_4;
145*4882a593Smuzhiyun hw->speed = hw->freq / 4;
146*4882a593Smuzhiyun } else if (hz >= hw->freq / 16) {
147*4882a593Smuzhiyun ctrl |= SC18IS602_MODE_CLOCK_DIV_16;
148*4882a593Smuzhiyun hw->speed = hw->freq / 16;
149*4882a593Smuzhiyun } else if (hz >= hw->freq / 64) {
150*4882a593Smuzhiyun ctrl |= SC18IS602_MODE_CLOCK_DIV_64;
151*4882a593Smuzhiyun hw->speed = hw->freq / 64;
152*4882a593Smuzhiyun } else {
153*4882a593Smuzhiyun ctrl |= SC18IS602_MODE_CLOCK_DIV_128;
154*4882a593Smuzhiyun hw->speed = hw->freq / 128;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun /*
158*4882a593Smuzhiyun * Don't do anything if the control value did not change. The initial
159*4882a593Smuzhiyun * value of 0xff for hw->ctrl ensures that the correct mode will be set
160*4882a593Smuzhiyun * with the first call to this function.
161*4882a593Smuzhiyun */
162*4882a593Smuzhiyun if (ctrl == hw->ctrl)
163*4882a593Smuzhiyun return 0;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(hw->client, 0xf0, ctrl);
166*4882a593Smuzhiyun if (ret < 0)
167*4882a593Smuzhiyun return ret;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun hw->ctrl = ctrl;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun return 0;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
sc18is602_check_transfer(struct spi_device * spi,struct spi_transfer * t,int tlen)174*4882a593Smuzhiyun static int sc18is602_check_transfer(struct spi_device *spi,
175*4882a593Smuzhiyun struct spi_transfer *t, int tlen)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun if (t && t->len + tlen > SC18IS602_BUFSIZ)
178*4882a593Smuzhiyun return -EINVAL;
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun return 0;
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun
sc18is602_transfer_one(struct spi_master * master,struct spi_message * m)183*4882a593Smuzhiyun static int sc18is602_transfer_one(struct spi_master *master,
184*4882a593Smuzhiyun struct spi_message *m)
185*4882a593Smuzhiyun {
186*4882a593Smuzhiyun struct sc18is602 *hw = spi_master_get_devdata(master);
187*4882a593Smuzhiyun struct spi_device *spi = m->spi;
188*4882a593Smuzhiyun struct spi_transfer *t;
189*4882a593Smuzhiyun int status = 0;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun hw->tlen = 0;
192*4882a593Smuzhiyun list_for_each_entry(t, &m->transfers, transfer_list) {
193*4882a593Smuzhiyun bool do_transfer;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun status = sc18is602_check_transfer(spi, t, hw->tlen);
196*4882a593Smuzhiyun if (status < 0)
197*4882a593Smuzhiyun break;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun status = sc18is602_setup_transfer(hw, t->speed_hz, spi->mode);
200*4882a593Smuzhiyun if (status < 0)
201*4882a593Smuzhiyun break;
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun do_transfer = t->cs_change || list_is_last(&t->transfer_list,
204*4882a593Smuzhiyun &m->transfers);
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun if (t->len) {
207*4882a593Smuzhiyun status = sc18is602_txrx(hw, m, t, do_transfer);
208*4882a593Smuzhiyun if (status < 0)
209*4882a593Smuzhiyun break;
210*4882a593Smuzhiyun m->actual_length += status;
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun status = 0;
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun spi_transfer_delay_exec(t);
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun m->status = status;
217*4882a593Smuzhiyun spi_finalize_current_message(master);
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun return status;
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun
sc18is602_setup(struct spi_device * spi)222*4882a593Smuzhiyun static int sc18is602_setup(struct spi_device *spi)
223*4882a593Smuzhiyun {
224*4882a593Smuzhiyun struct sc18is602 *hw = spi_master_get_devdata(spi->master);
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun /* SC18IS602 does not support CS2 */
227*4882a593Smuzhiyun if (hw->id == sc18is602 && spi->chip_select == 2)
228*4882a593Smuzhiyun return -ENXIO;
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun return 0;
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun
sc18is602_probe(struct i2c_client * client,const struct i2c_device_id * id)233*4882a593Smuzhiyun static int sc18is602_probe(struct i2c_client *client,
234*4882a593Smuzhiyun const struct i2c_device_id *id)
235*4882a593Smuzhiyun {
236*4882a593Smuzhiyun struct device *dev = &client->dev;
237*4882a593Smuzhiyun struct device_node *np = dev->of_node;
238*4882a593Smuzhiyun struct sc18is602_platform_data *pdata = dev_get_platdata(dev);
239*4882a593Smuzhiyun struct sc18is602 *hw;
240*4882a593Smuzhiyun struct spi_master *master;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
243*4882a593Smuzhiyun I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
244*4882a593Smuzhiyun return -EINVAL;
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun master = devm_spi_alloc_master(dev, sizeof(struct sc18is602));
247*4882a593Smuzhiyun if (!master)
248*4882a593Smuzhiyun return -ENOMEM;
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun hw = spi_master_get_devdata(master);
251*4882a593Smuzhiyun i2c_set_clientdata(client, hw);
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun /* assert reset and then release */
254*4882a593Smuzhiyun hw->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
255*4882a593Smuzhiyun if (IS_ERR(hw->reset))
256*4882a593Smuzhiyun return PTR_ERR(hw->reset);
257*4882a593Smuzhiyun gpiod_set_value_cansleep(hw->reset, 0);
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun hw->master = master;
260*4882a593Smuzhiyun hw->client = client;
261*4882a593Smuzhiyun hw->dev = dev;
262*4882a593Smuzhiyun hw->ctrl = 0xff;
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun if (client->dev.of_node)
265*4882a593Smuzhiyun hw->id = (enum chips)of_device_get_match_data(&client->dev);
266*4882a593Smuzhiyun else
267*4882a593Smuzhiyun hw->id = id->driver_data;
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun switch (hw->id) {
270*4882a593Smuzhiyun case sc18is602:
271*4882a593Smuzhiyun case sc18is602b:
272*4882a593Smuzhiyun master->num_chipselect = 4;
273*4882a593Smuzhiyun hw->freq = SC18IS602_CLOCK;
274*4882a593Smuzhiyun break;
275*4882a593Smuzhiyun case sc18is603:
276*4882a593Smuzhiyun master->num_chipselect = 2;
277*4882a593Smuzhiyun if (pdata) {
278*4882a593Smuzhiyun hw->freq = pdata->clock_frequency;
279*4882a593Smuzhiyun } else {
280*4882a593Smuzhiyun const __be32 *val;
281*4882a593Smuzhiyun int len;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun val = of_get_property(np, "clock-frequency", &len);
284*4882a593Smuzhiyun if (val && len >= sizeof(__be32))
285*4882a593Smuzhiyun hw->freq = be32_to_cpup(val);
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun if (!hw->freq)
288*4882a593Smuzhiyun hw->freq = SC18IS602_CLOCK;
289*4882a593Smuzhiyun break;
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun master->bus_num = np ? -1 : client->adapter->nr;
292*4882a593Smuzhiyun master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST;
293*4882a593Smuzhiyun master->bits_per_word_mask = SPI_BPW_MASK(8);
294*4882a593Smuzhiyun master->setup = sc18is602_setup;
295*4882a593Smuzhiyun master->transfer_one_message = sc18is602_transfer_one;
296*4882a593Smuzhiyun master->dev.of_node = np;
297*4882a593Smuzhiyun master->min_speed_hz = hw->freq / 128;
298*4882a593Smuzhiyun master->max_speed_hz = hw->freq / 4;
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun return devm_spi_register_master(dev, master);
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun static const struct i2c_device_id sc18is602_id[] = {
304*4882a593Smuzhiyun { "sc18is602", sc18is602 },
305*4882a593Smuzhiyun { "sc18is602b", sc18is602b },
306*4882a593Smuzhiyun { "sc18is603", sc18is603 },
307*4882a593Smuzhiyun { }
308*4882a593Smuzhiyun };
309*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, sc18is602_id);
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun static const struct of_device_id sc18is602_of_match[] = {
312*4882a593Smuzhiyun {
313*4882a593Smuzhiyun .compatible = "nxp,sc18is602",
314*4882a593Smuzhiyun .data = (void *)sc18is602
315*4882a593Smuzhiyun },
316*4882a593Smuzhiyun {
317*4882a593Smuzhiyun .compatible = "nxp,sc18is602b",
318*4882a593Smuzhiyun .data = (void *)sc18is602b
319*4882a593Smuzhiyun },
320*4882a593Smuzhiyun {
321*4882a593Smuzhiyun .compatible = "nxp,sc18is603",
322*4882a593Smuzhiyun .data = (void *)sc18is603
323*4882a593Smuzhiyun },
324*4882a593Smuzhiyun { },
325*4882a593Smuzhiyun };
326*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, sc18is602_of_match);
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun static struct i2c_driver sc18is602_driver = {
329*4882a593Smuzhiyun .driver = {
330*4882a593Smuzhiyun .name = "sc18is602",
331*4882a593Smuzhiyun .of_match_table = of_match_ptr(sc18is602_of_match),
332*4882a593Smuzhiyun },
333*4882a593Smuzhiyun .probe = sc18is602_probe,
334*4882a593Smuzhiyun .id_table = sc18is602_id,
335*4882a593Smuzhiyun };
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun module_i2c_driver(sc18is602_driver);
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun MODULE_DESCRIPTION("SC18IS602/603 SPI Master Driver");
340*4882a593Smuzhiyun MODULE_AUTHOR("Guenter Roeck");
341*4882a593Smuzhiyun MODULE_LICENSE("GPL");
342