1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2004 Fetron GmbH 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * S3C2410 SPI register definition 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __SPI_S3C2410_H 9*4882a593Smuzhiyun #define __SPI_S3C2410_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define S3C2410_SPCON (0x00) 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define S3C2410_SPCON_SMOD_DMA (2 << 5) /* DMA mode */ 14*4882a593Smuzhiyun #define S3C2410_SPCON_SMOD_INT (1 << 5) /* interrupt mode */ 15*4882a593Smuzhiyun #define S3C2410_SPCON_SMOD_POLL (0 << 5) /* polling mode */ 16*4882a593Smuzhiyun #define S3C2410_SPCON_ENSCK (1 << 4) /* Enable SCK */ 17*4882a593Smuzhiyun #define S3C2410_SPCON_MSTR (1 << 3) /* Master:1, Slave:0 select */ 18*4882a593Smuzhiyun #define S3C2410_SPCON_CPOL_HIGH (1 << 2) /* Clock polarity select */ 19*4882a593Smuzhiyun #define S3C2410_SPCON_CPOL_LOW (0 << 2) /* Clock polarity select */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define S3C2410_SPCON_CPHA_FMTB (1 << 1) /* Clock Phase Select */ 22*4882a593Smuzhiyun #define S3C2410_SPCON_CPHA_FMTA (0 << 1) /* Clock Phase Select */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define S3C2410_SPSTA (0x04) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define S3C2410_SPSTA_DCOL (1 << 2) /* Data Collision Error */ 27*4882a593Smuzhiyun #define S3C2410_SPSTA_MULD (1 << 1) /* Multi Master Error */ 28*4882a593Smuzhiyun #define S3C2410_SPSTA_READY (1 << 0) /* Data Tx/Rx ready */ 29*4882a593Smuzhiyun #define S3C2412_SPSTA_READY_ORG (1 << 3) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define S3C2410_SPPIN (0x08) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define S3C2410_SPPIN_ENMUL (1 << 2) /* Multi Master Error detect */ 34*4882a593Smuzhiyun #define S3C2410_SPPIN_RESERVED (1 << 1) 35*4882a593Smuzhiyun #define S3C2410_SPPIN_KEEP (1 << 0) /* Master Out keep */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define S3C2410_SPPRE (0x0C) 38*4882a593Smuzhiyun #define S3C2410_SPTDAT (0x10) 39*4882a593Smuzhiyun #define S3C2410_SPRDAT (0x14) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #endif /* __SPI_S3C2410_H */ 42