1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
4 * Author: Addy Ke <addy.ke@rock-chips.com>
5 */
6
7 #include <linux/acpi.h>
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/dmaengine.h>
11 #include <linux/interrupt.h>
12 #include <linux/miscdevice.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/pinctrl/consumer.h>
16 #include <linux/pinctrl/devinfo.h>
17 #include <linux/platform_device.h>
18 #include <linux/spi/spi.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/scatterlist.h>
21
22 #define DRIVER_NAME "rockchip-spi"
23
24 #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \
25 writel_relaxed(readl_relaxed(reg) & ~(bits), reg)
26 #define ROCKCHIP_SPI_SET_BITS(reg, bits) \
27 writel_relaxed(readl_relaxed(reg) | (bits), reg)
28
29 /* SPI register offsets */
30 #define ROCKCHIP_SPI_CTRLR0 0x0000
31 #define ROCKCHIP_SPI_CTRLR1 0x0004
32 #define ROCKCHIP_SPI_SSIENR 0x0008
33 #define ROCKCHIP_SPI_SER 0x000c
34 #define ROCKCHIP_SPI_BAUDR 0x0010
35 #define ROCKCHIP_SPI_TXFTLR 0x0014
36 #define ROCKCHIP_SPI_RXFTLR 0x0018
37 #define ROCKCHIP_SPI_TXFLR 0x001c
38 #define ROCKCHIP_SPI_RXFLR 0x0020
39 #define ROCKCHIP_SPI_SR 0x0024
40 #define ROCKCHIP_SPI_IPR 0x0028
41 #define ROCKCHIP_SPI_IMR 0x002c
42 #define ROCKCHIP_SPI_ISR 0x0030
43 #define ROCKCHIP_SPI_RISR 0x0034
44 #define ROCKCHIP_SPI_ICR 0x0038
45 #define ROCKCHIP_SPI_DMACR 0x003c
46 #define ROCKCHIP_SPI_DMATDLR 0x0040
47 #define ROCKCHIP_SPI_DMARDLR 0x0044
48 #define ROCKCHIP_SPI_VERSION 0x0048
49 #define ROCKCHIP_SPI_TXDR 0x0400
50 #define ROCKCHIP_SPI_RXDR 0x0800
51
52 /* Bit fields in CTRLR0 */
53 #define CR0_DFS_OFFSET 0
54 #define CR0_DFS_4BIT 0x0
55 #define CR0_DFS_8BIT 0x1
56 #define CR0_DFS_16BIT 0x2
57
58 #define CR0_CFS_OFFSET 2
59
60 #define CR0_SCPH_OFFSET 6
61
62 #define CR0_SCPOL_OFFSET 7
63
64 #define CR0_CSM_OFFSET 8
65 #define CR0_CSM_KEEP 0x0
66 /* ss_n be high for half sclk_out cycles */
67 #define CR0_CSM_HALF 0X1
68 /* ss_n be high for one sclk_out cycle */
69 #define CR0_CSM_ONE 0x2
70
71 /* ss_n to sclk_out delay */
72 #define CR0_SSD_OFFSET 10
73 /*
74 * The period between ss_n active and
75 * sclk_out active is half sclk_out cycles
76 */
77 #define CR0_SSD_HALF 0x0
78 /*
79 * The period between ss_n active and
80 * sclk_out active is one sclk_out cycle
81 */
82 #define CR0_SSD_ONE 0x1
83
84 #define CR0_EM_OFFSET 11
85 #define CR0_EM_LITTLE 0x0
86 #define CR0_EM_BIG 0x1
87
88 #define CR0_FBM_OFFSET 12
89 #define CR0_FBM_MSB 0x0
90 #define CR0_FBM_LSB 0x1
91
92 #define CR0_BHT_OFFSET 13
93 #define CR0_BHT_16BIT 0x0
94 #define CR0_BHT_8BIT 0x1
95
96 #define CR0_RSD_OFFSET 14
97 #define CR0_RSD_MAX 0x3
98
99 #define CR0_FRF_OFFSET 16
100 #define CR0_FRF_SPI 0x0
101 #define CR0_FRF_SSP 0x1
102 #define CR0_FRF_MICROWIRE 0x2
103
104 #define CR0_XFM_OFFSET 18
105 #define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET)
106 #define CR0_XFM_TR 0x0
107 #define CR0_XFM_TO 0x1
108 #define CR0_XFM_RO 0x2
109
110 #define CR0_OPM_OFFSET 20
111 #define CR0_OPM_MASTER 0x0
112 #define CR0_OPM_SLAVE 0x1
113
114 #define CR0_SOI_OFFSET 23
115
116 #define CR0_MTM_OFFSET 0x21
117
118 /* Bit fields in SER, 2bit */
119 #define SER_MASK 0x3
120
121 /* Bit fields in BAUDR */
122 #define BAUDR_SCKDV_MIN 2
123 #define BAUDR_SCKDV_MAX 65534
124
125 /* Bit fields in SR, 6bit */
126 #define SR_MASK 0x3f
127 #define SR_BUSY (1 << 0)
128 #define SR_TF_FULL (1 << 1)
129 #define SR_TF_EMPTY (1 << 2)
130 #define SR_RF_EMPTY (1 << 3)
131 #define SR_RF_FULL (1 << 4)
132 #define SR_SLAVE_TX_BUSY (1 << 5)
133
134 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */
135 #define INT_MASK 0x1f
136 #define INT_TF_EMPTY (1 << 0)
137 #define INT_TF_OVERFLOW (1 << 1)
138 #define INT_RF_UNDERFLOW (1 << 2)
139 #define INT_RF_OVERFLOW (1 << 3)
140 #define INT_RF_FULL (1 << 4)
141 #define INT_CS_INACTIVE (1 << 6)
142
143 /* Bit fields in ICR, 4bit */
144 #define ICR_MASK 0x0f
145 #define ICR_ALL (1 << 0)
146 #define ICR_RF_UNDERFLOW (1 << 1)
147 #define ICR_RF_OVERFLOW (1 << 2)
148 #define ICR_TF_OVERFLOW (1 << 3)
149
150 /* Bit fields in DMACR */
151 #define RF_DMA_EN (1 << 0)
152 #define TF_DMA_EN (1 << 1)
153
154 /* Driver state flags */
155 #define RXDMA (1 << 0)
156 #define TXDMA (1 << 1)
157
158 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
159 #define MAX_SCLK_OUT 50000000U
160 /* max sclk of driver strength 4mA */
161 #define IO_DRIVER_4MA_MAX_SCLK_OUT 24000000U
162
163 /*
164 * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
165 * the controller seems to hang when given 0x10000, so stick with this for now.
166 */
167 #define ROCKCHIP_SPI_MAX_TRANLEN 0xffff
168
169 /* 2 for native cs, 2 for cs-gpio */
170 #define ROCKCHIP_SPI_MAX_CS_NUM 4
171 #define ROCKCHIP_SPI_VER2_TYPE1 0x05EC0002
172 #define ROCKCHIP_SPI_VER2_TYPE2 0x00110002
173
174 #define ROCKCHIP_SPI_REGISTER_SIZE 0x1000
175
176 enum rockchip_spi_xfer_mode {
177 ROCKCHIP_SPI_DMA,
178 ROCKCHIP_SPI_IRQ,
179 ROCKCHIP_SPI_POLL,
180 };
181
182 struct rockchip_spi_quirks {
183 u32 max_baud_div_in_cpha;
184 };
185
186 struct rockchip_spi {
187 struct device *dev;
188
189 struct clk *spiclk;
190 struct clk *apb_pclk;
191 struct clk *sclk_in;
192
193 void __iomem *regs;
194 dma_addr_t dma_addr_rx;
195 dma_addr_t dma_addr_tx;
196
197 const void *tx;
198 void *rx;
199 unsigned int tx_left;
200 unsigned int rx_left;
201
202 atomic_t state;
203 struct completion xfer_done;
204
205 u32 version;
206 /*depth of the FIFO buffer */
207 u32 fifo_len;
208 /* frequency of spiclk */
209 u32 freq;
210 /* speed of io rate */
211 u32 speed_hz;
212
213 u8 n_bytes;
214 u8 rsd;
215 u8 csm;
216 bool poll; /* only support transfer data by cpu polling */
217
218 bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
219
220 struct pinctrl_state *high_speed_state;
221 bool slave_aborted;
222 bool cs_inactive; /* spi slave tansmition stop when cs inactive */
223 bool cs_high_supported; /* native CS supports active-high polarity */
224 struct gpio_desc *ready; /* spi slave transmission ready */
225
226 struct spi_transfer *xfer; /* Store xfer temporarily */
227 phys_addr_t base_addr_phy;
228 struct miscdevice miscdev;
229
230 /* quirks */
231 u32 max_baud_div_in_cpha;
232 };
233
spi_enable_chip(struct rockchip_spi * rs,bool enable)234 static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
235 {
236 writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
237 }
238
wait_for_tx_idle(struct rockchip_spi * rs,bool slave_mode)239 static inline void wait_for_tx_idle(struct rockchip_spi *rs, bool slave_mode)
240 {
241 unsigned long timeout = jiffies + msecs_to_jiffies(5);
242 u32 bit_filed = SR_BUSY;
243 u32 idle_val = 0;
244 uint32_t speed, us;
245
246 if (slave_mode && rs->version == ROCKCHIP_SPI_VER2_TYPE2) {
247 bit_filed = SR_SLAVE_TX_BUSY;
248 idle_val = 0;
249 } else if (slave_mode) {
250 bit_filed = SR_TF_EMPTY;
251 idle_val = 1;
252 }
253
254 do {
255 if ((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & bit_filed) == idle_val) {
256 if (bit_filed == SR_TF_EMPTY) {
257 speed = rs->speed_hz;
258 us = (8 * 1000000 / speed) * 2;
259 udelay(us);
260 }
261 return;
262 }
263 } while (!time_after(jiffies, timeout));
264
265 dev_warn(rs->dev, "spi controller is in busy state!\n");
266 }
267
get_fifo_len(struct rockchip_spi * rs)268 static u32 get_fifo_len(struct rockchip_spi *rs)
269 {
270 switch (rs->version) {
271 case ROCKCHIP_SPI_VER2_TYPE1:
272 case ROCKCHIP_SPI_VER2_TYPE2:
273 return 64;
274 default:
275 return 32;
276 }
277 }
278
rockchip_spi_set_cs(struct spi_device * spi,bool enable)279 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
280 {
281 struct spi_controller *ctlr = spi->controller;
282 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
283 bool cs_asserted = spi->mode & SPI_CS_HIGH ? enable : !enable;
284
285 /* Return immediately for no-op */
286 if (cs_asserted == rs->cs_asserted[spi->chip_select])
287 return;
288
289 if (cs_asserted) {
290 /* Keep things powered as long as CS is asserted */
291 pm_runtime_get_sync(rs->dev);
292
293 if (spi->cs_gpiod)
294 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
295 else
296 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
297 } else {
298 if (spi->cs_gpiod)
299 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
300 else
301 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
302
303 /* Drop reference from when we first asserted CS */
304 pm_runtime_put(rs->dev);
305 }
306
307 rs->cs_asserted[spi->chip_select] = cs_asserted;
308 }
309
rockchip_spi_handle_err(struct spi_controller * ctlr,struct spi_message * msg)310 static void rockchip_spi_handle_err(struct spi_controller *ctlr,
311 struct spi_message *msg)
312 {
313 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
314
315 dev_err(rs->dev, "state=%x\n", atomic_read(&rs->state));
316 dev_err(rs->dev, "tx_left=%x\n", rs->tx_left);
317 dev_err(rs->dev, "rx_left=%x\n", rs->rx_left);
318 print_hex_dump(KERN_ERR, "regs ", DUMP_PREFIX_OFFSET, 4, 4, rs->regs, 0x4c, 0);
319
320 /* stop running spi transfer
321 * this also flushes both rx and tx fifos
322 */
323 spi_enable_chip(rs, false);
324
325 /* make sure all interrupts are masked and status cleared */
326 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
327 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
328
329 if (atomic_read(&rs->state) & TXDMA)
330 dmaengine_terminate_async(ctlr->dma_tx);
331
332 if (atomic_read(&rs->state) & RXDMA)
333 dmaengine_terminate_async(ctlr->dma_rx);
334 atomic_set(&rs->state, 0);
335 }
336
rockchip_spi_pio_writer(struct rockchip_spi * rs)337 static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
338 {
339 u32 tx_free = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
340 u32 words = min(rs->tx_left, tx_free);
341
342 rs->tx_left -= words;
343 for (; words; words--) {
344 u32 txw;
345
346 if (rs->n_bytes == 1)
347 txw = *(u8 *)rs->tx;
348 else
349 txw = *(u16 *)rs->tx;
350
351 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
352 rs->tx += rs->n_bytes;
353 }
354 }
355
rockchip_spi_pio_reader(struct rockchip_spi * rs)356 static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
357 {
358 u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
359 u32 rx_left = (rs->rx_left > words) ? rs->rx_left - words : 0;
360
361 /* the hardware doesn't allow us to change fifo threshold
362 * level while spi is enabled, so instead make sure to leave
363 * enough words in the rx fifo to get the last interrupt
364 * exactly when all words have been received
365 */
366 if (rx_left) {
367 u32 ftl = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFTLR) + 1;
368
369 if (rx_left < ftl) {
370 rx_left = ftl;
371 words = rs->rx_left - rx_left;
372 }
373 }
374
375 rs->rx_left = rx_left;
376 for (; words; words--) {
377 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
378
379 if (!rs->rx)
380 continue;
381
382 if (rs->n_bytes == 1)
383 *(u8 *)rs->rx = (u8)rxw;
384 else
385 *(u16 *)rs->rx = (u16)rxw;
386 rs->rx += rs->n_bytes;
387 }
388 }
389
rockchip_spi_isr(int irq,void * dev_id)390 static irqreturn_t rockchip_spi_isr(int irq, void *dev_id)
391 {
392 struct spi_controller *ctlr = dev_id;
393 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
394
395 /* When int_cs_inactive comes, spi slave abort */
396 if (rs->cs_inactive && readl_relaxed(rs->regs + ROCKCHIP_SPI_ISR) & INT_CS_INACTIVE) {
397 ctlr->slave_abort(ctlr);
398 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
399 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
400
401 return IRQ_HANDLED;
402 }
403
404 if (rs->tx_left)
405 rockchip_spi_pio_writer(rs);
406
407 rockchip_spi_pio_reader(rs);
408 if (!rs->rx_left) {
409 spi_enable_chip(rs, false);
410 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
411 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
412 complete(&rs->xfer_done);
413 }
414
415 return IRQ_HANDLED;
416 }
417
rockchip_spi_prepare_irq(struct rockchip_spi * rs,struct spi_controller * ctlr,struct spi_transfer * xfer)418 static int rockchip_spi_prepare_irq(struct rockchip_spi *rs,
419 struct spi_controller *ctlr,
420 struct spi_transfer *xfer)
421 {
422 rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
423 rs->rx_left = xfer->len / rs->n_bytes;
424
425 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
426
427 spi_enable_chip(rs, true);
428
429 if (rs->tx_left)
430 rockchip_spi_pio_writer(rs);
431
432 if (rs->cs_inactive)
433 writel_relaxed(INT_RF_FULL | INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
434 else
435 writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR);
436
437 /* 1 means the transfer is in progress */
438 return 1;
439 }
440
rockchip_spi_dma_rxcb(void * data)441 static void rockchip_spi_dma_rxcb(void *data)
442 {
443 struct spi_controller *ctlr = data;
444 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
445 int state = atomic_fetch_andnot(RXDMA, &rs->state);
446
447 if (state & TXDMA && !rs->slave_aborted)
448 return;
449
450 if (rs->cs_inactive)
451 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
452
453 spi_enable_chip(rs, false);
454 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
455 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
456 complete(&rs->xfer_done);
457 }
458
rockchip_spi_dma_txcb(void * data)459 static void rockchip_spi_dma_txcb(void *data)
460 {
461 struct spi_controller *ctlr = data;
462 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
463 int state = atomic_fetch_andnot(TXDMA, &rs->state);
464
465 if (state & RXDMA && !rs->slave_aborted)
466 return;
467
468 /* Wait until the FIFO data completely. */
469 wait_for_tx_idle(rs, ctlr->slave);
470
471 spi_enable_chip(rs, false);
472 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
473 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
474 complete(&rs->xfer_done);
475 }
476
rockchip_spi_calc_burst_size(u32 data_len)477 static u32 rockchip_spi_calc_burst_size(u32 data_len)
478 {
479 u32 i;
480
481 /* burst size: 1, 2, 4, 8 */
482 for (i = 1; i < 8; i <<= 1) {
483 if (data_len & i)
484 break;
485 }
486
487 return i;
488 }
489
rockchip_spi_prepare_dma(struct rockchip_spi * rs,struct spi_controller * ctlr,struct spi_transfer * xfer)490 static int rockchip_spi_prepare_dma(struct rockchip_spi *rs,
491 struct spi_controller *ctlr, struct spi_transfer *xfer)
492 {
493 struct dma_async_tx_descriptor *rxdesc, *txdesc;
494
495 atomic_set(&rs->state, 0);
496
497 rxdesc = NULL;
498 if (xfer->rx_buf) {
499 struct dma_slave_config rxconf = {
500 .direction = DMA_DEV_TO_MEM,
501 .src_addr = rs->dma_addr_rx,
502 .src_addr_width = rs->n_bytes,
503 .src_maxburst = rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes),
504 };
505
506 dmaengine_slave_config(ctlr->dma_rx, &rxconf);
507
508 rxdesc = dmaengine_prep_slave_sg(
509 ctlr->dma_rx,
510 xfer->rx_sg.sgl, xfer->rx_sg.nents,
511 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
512 if (!rxdesc)
513 return -EINVAL;
514
515 rxdesc->callback = rockchip_spi_dma_rxcb;
516 rxdesc->callback_param = ctlr;
517 }
518
519 txdesc = NULL;
520 if (xfer->tx_buf) {
521 struct dma_slave_config txconf = {
522 .direction = DMA_MEM_TO_DEV,
523 .dst_addr = rs->dma_addr_tx,
524 .dst_addr_width = rs->n_bytes,
525 .dst_maxburst = rs->fifo_len / 4,
526 };
527
528 dmaengine_slave_config(ctlr->dma_tx, &txconf);
529
530 txdesc = dmaengine_prep_slave_sg(
531 ctlr->dma_tx,
532 xfer->tx_sg.sgl, xfer->tx_sg.nents,
533 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
534 if (!txdesc) {
535 if (rxdesc)
536 dmaengine_terminate_sync(ctlr->dma_rx);
537 return -EINVAL;
538 }
539
540 txdesc->callback = rockchip_spi_dma_txcb;
541 txdesc->callback_param = ctlr;
542 }
543
544 /* rx must be started before tx due to spi instinct */
545 if (rxdesc) {
546 atomic_or(RXDMA, &rs->state);
547 ctlr->dma_rx->cookie = dmaengine_submit(rxdesc);
548 dma_async_issue_pending(ctlr->dma_rx);
549 }
550
551 if (rs->cs_inactive)
552 writel_relaxed(INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
553
554 spi_enable_chip(rs, true);
555
556 if (txdesc) {
557 atomic_or(TXDMA, &rs->state);
558 dmaengine_submit(txdesc);
559 dma_async_issue_pending(ctlr->dma_tx);
560 }
561
562 /* 1 means the transfer is in progress */
563 return 1;
564 }
565
rockchip_spi_pio_transfer(struct rockchip_spi * rs,struct spi_controller * ctlr,struct spi_transfer * xfer)566 static int rockchip_spi_pio_transfer(struct rockchip_spi *rs,
567 struct spi_controller *ctlr, struct spi_transfer *xfer)
568 {
569 unsigned long time, timeout;
570 u32 speed_hz = xfer->speed_hz;
571 unsigned long long ms;
572 int ret = 0;
573
574 if (!speed_hz)
575 speed_hz = 100000;
576
577 ms = 8LL * 1000LL * xfer->len;
578 do_div(ms, speed_hz);
579 ms += ms + 200; /* some tolerance */
580
581 if (ms > UINT_MAX || ctlr->slave)
582 ms = UINT_MAX;
583
584 timeout = jiffies + msecs_to_jiffies(ms);
585 time = jiffies;
586 rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
587 rs->rx_left = rs->rx ? xfer->len / rs->n_bytes : 0;
588
589 spi_enable_chip(rs, true);
590
591 while (rs->tx_left || rs->rx_left) {
592 if (rs->tx)
593 rockchip_spi_pio_writer(rs);
594
595 if (rs->rx)
596 rockchip_spi_pio_reader(rs);
597
598 cpu_relax();
599
600 if (time_after(time, timeout)) {
601 ret = -EIO;
602 goto out;
603 }
604 };
605
606 /* If tx, wait until the FIFO data completely. */
607 if (rs->tx)
608 wait_for_tx_idle(rs, ctlr->slave);
609
610 out:
611 spi_enable_chip(rs, false);
612
613 return ret;
614 }
615
rockchip_spi_config(struct rockchip_spi * rs,struct spi_device * spi,struct spi_transfer * xfer,enum rockchip_spi_xfer_mode xfer_mode,bool slave_mode)616 static int rockchip_spi_config(struct rockchip_spi *rs,
617 struct spi_device *spi, struct spi_transfer *xfer,
618 enum rockchip_spi_xfer_mode xfer_mode, bool slave_mode)
619 {
620 u32 cr0 = CR0_FRF_SPI << CR0_FRF_OFFSET
621 | CR0_BHT_8BIT << CR0_BHT_OFFSET
622 | CR0_SSD_ONE << CR0_SSD_OFFSET
623 | CR0_EM_BIG << CR0_EM_OFFSET;
624 u32 cr1;
625 u32 dmacr = 0;
626
627 if (slave_mode)
628 cr0 |= CR0_OPM_SLAVE << CR0_OPM_OFFSET;
629 rs->slave_aborted = false;
630
631 cr0 |= rs->rsd << CR0_RSD_OFFSET;
632 cr0 |= rs->csm << CR0_CSM_OFFSET;
633 cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET;
634 if (spi->mode & SPI_LSB_FIRST)
635 cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET;
636 if (spi->mode & SPI_CS_HIGH)
637 cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;
638
639 if (xfer->rx_buf && xfer->tx_buf) {
640 cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET;
641 } else if (xfer->rx_buf) {
642 cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET;
643 } else if (xfer->tx_buf) {
644 /*
645 * Use the water line of rx fifo in full duplex mode to trigger
646 * the interruption of tx irq transmission completion.
647 */
648 if (xfer_mode == ROCKCHIP_SPI_IRQ)
649 cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET;
650 else
651 cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET;
652 } else {
653 dev_err(rs->dev, "no transmission buffer\n");
654 return -EINVAL;
655 }
656
657 switch (xfer->bits_per_word) {
658 case 4:
659 cr0 |= CR0_DFS_4BIT << CR0_DFS_OFFSET;
660 cr1 = xfer->len - 1;
661 break;
662 case 8:
663 cr0 |= CR0_DFS_8BIT << CR0_DFS_OFFSET;
664 cr1 = xfer->len - 1;
665 break;
666 case 16:
667 cr0 |= CR0_DFS_16BIT << CR0_DFS_OFFSET;
668 cr1 = xfer->len / 2 - 1;
669 break;
670 default:
671 /* we only whitelist 4, 8 and 16 bit words in
672 * ctlr->bits_per_word_mask, so this shouldn't
673 * happen
674 */
675 dev_err(rs->dev, "unknown bits per word: %d\n",
676 xfer->bits_per_word);
677 return -EINVAL;
678 }
679
680 if (xfer_mode == ROCKCHIP_SPI_DMA) {
681 if (xfer->tx_buf)
682 dmacr |= TF_DMA_EN;
683 if (xfer->rx_buf)
684 dmacr |= RF_DMA_EN;
685 }
686
687 /*
688 * If speed is larger than IO_DRIVER_4MA_MAX_SCLK_OUT,
689 * set higher driver strength.
690 */
691 if (rs->high_speed_state) {
692 if (rs->freq > IO_DRIVER_4MA_MAX_SCLK_OUT)
693 pinctrl_select_state(rs->dev->pins->p,
694 rs->high_speed_state);
695 else
696 pinctrl_select_state(rs->dev->pins->p,
697 rs->dev->pins->default_state);
698 }
699
700 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
701 writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1);
702
703 /* unfortunately setting the fifo threshold level to generate an
704 * interrupt exactly when the fifo is full doesn't seem to work,
705 * so we need the strict inequality here
706 */
707 if ((xfer->len / rs->n_bytes) < rs->fifo_len)
708 writel_relaxed(xfer->len / rs->n_bytes - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
709 else
710 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
711
712 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_DMATDLR);
713 writel_relaxed(rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes) - 1,
714 rs->regs + ROCKCHIP_SPI_DMARDLR);
715 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
716
717 if (rs->max_baud_div_in_cpha && xfer->speed_hz != rs->speed_hz) {
718 /* the minimum divisor is 2 */
719 if (rs->freq < 2 * xfer->speed_hz) {
720 clk_set_rate(rs->spiclk, 2 * xfer->speed_hz);
721 rs->freq = clk_get_rate(rs->spiclk);
722 }
723
724 if ((spi->mode & SPI_CPHA) && (DIV_ROUND_UP(rs->freq, xfer->speed_hz) > rs->max_baud_div_in_cpha)) {
725 clk_set_rate(rs->spiclk, rs->max_baud_div_in_cpha * xfer->speed_hz);
726 rs->freq = clk_get_rate(rs->spiclk);
727 }
728 }
729
730 /* the hardware only supports an even clock divisor, so
731 * round divisor = spiclk / speed up to nearest even number
732 * so that the resulting speed is <= the requested speed
733 */
734 writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz),
735 rs->regs + ROCKCHIP_SPI_BAUDR);
736 rs->speed_hz = xfer->speed_hz;
737
738 return 0;
739 }
740
rockchip_spi_max_transfer_size(struct spi_device * spi)741 static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
742 {
743 return ROCKCHIP_SPI_MAX_TRANLEN;
744 }
745
rockchip_spi_slave_abort(struct spi_controller * ctlr)746 static int rockchip_spi_slave_abort(struct spi_controller *ctlr)
747 {
748 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
749 u32 rx_fifo_left;
750
751 /* Flush rx fifo */
752 rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
753 for (; rx_fifo_left; rx_fifo_left--)
754 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
755
756 rs->slave_aborted = true;
757 complete(&rs->xfer_done);
758
759 return 0;
760 }
761
rockchip_spi_transfer_wait(struct spi_controller * ctlr,struct spi_transfer * xfer)762 static int rockchip_spi_transfer_wait(struct spi_controller *ctlr,
763 struct spi_transfer *xfer)
764 {
765 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
766 u32 speed_hz = xfer->speed_hz;
767 unsigned long long ms;
768
769 if (spi_controller_is_slave(ctlr)) {
770 if (wait_for_completion_interruptible(&rs->xfer_done)) {
771 dev_dbg(rs->dev, "RK SPI transfer interrupted\n");
772 return -EINTR;
773 }
774
775 if (rs->slave_aborted) {
776 dev_err(rs->dev, "RK SPI transfer slave abort\n");
777 return -EIO;
778 }
779 } else {
780 if (!speed_hz)
781 speed_hz = 100000;
782
783 ms = 8LL * 1000LL * xfer->len;
784 do_div(ms, speed_hz);
785 ms += ms + 200; /* some tolerance */
786
787 if (ms > UINT_MAX)
788 ms = UINT_MAX;
789
790 ms = wait_for_completion_timeout(&rs->xfer_done,
791 msecs_to_jiffies(ms));
792
793 if (ms == 0) {
794 dev_err(rs->dev, "RK SPI transfer timed out\n");
795 return -ETIMEDOUT;
796 }
797 }
798
799 return 0;
800 }
801
rockchip_spi_transfer_one(struct spi_controller * ctlr,struct spi_device * spi,struct spi_transfer * xfer)802 static int rockchip_spi_transfer_one(
803 struct spi_controller *ctlr,
804 struct spi_device *spi,
805 struct spi_transfer *xfer)
806 {
807 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
808 int ret;
809 bool use_dma;
810 enum rockchip_spi_xfer_mode xfer_mode;
811
812 /* Zero length transfers won't trigger an interrupt on completion */
813 if (!xfer->len) {
814 complete(&rs->xfer_done);
815 return 1;
816 }
817
818 WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
819 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
820
821 if (!xfer->tx_buf && !xfer->rx_buf) {
822 dev_err(rs->dev, "No buffer for transfer\n");
823 return -EINVAL;
824 }
825
826 if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) {
827 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len);
828 return -EINVAL;
829 }
830
831 rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2;
832 rs->xfer = xfer;
833 if (rs->poll) {
834 xfer_mode = ROCKCHIP_SPI_POLL;
835 } else {
836 use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false;
837 if (use_dma)
838 xfer_mode = ROCKCHIP_SPI_DMA;
839 else
840 xfer_mode = ROCKCHIP_SPI_IRQ;
841 }
842
843 ret = rockchip_spi_config(rs, spi, xfer, xfer_mode, ctlr->slave);
844 if (ret)
845 return ret;
846
847 rs->tx = xfer->tx_buf;
848 rs->rx = xfer->rx_buf;
849
850 reinit_completion(&rs->xfer_done);
851
852 switch (xfer_mode) {
853 case ROCKCHIP_SPI_POLL:
854 ret = rockchip_spi_pio_transfer(rs, ctlr, xfer);
855 break;
856 case ROCKCHIP_SPI_DMA:
857 ret = rockchip_spi_prepare_dma(rs, ctlr, xfer);
858 break;
859 default:
860 ret = rockchip_spi_prepare_irq(rs, ctlr, xfer);
861 }
862
863 if (rs->ready) {
864 gpiod_set_value(rs->ready, 0);
865 udelay(1);
866 gpiod_set_value(rs->ready, 1);
867 }
868
869 if (ret > 0)
870 ret = rockchip_spi_transfer_wait(ctlr, xfer);
871
872 if (rs->ready)
873 gpiod_set_value(rs->ready, 0);
874
875 return ret;
876 }
877
rockchip_spi_can_dma(struct spi_controller * ctlr,struct spi_device * spi,struct spi_transfer * xfer)878 static bool rockchip_spi_can_dma(struct spi_controller *ctlr,
879 struct spi_device *spi,
880 struct spi_transfer *xfer)
881 {
882 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
883 unsigned int bytes_per_word = xfer->bits_per_word <= 8 ? 1 : 2;
884
885 /* if the numbor of spi words to transfer is less than the fifo
886 * length we can just fill the fifo and wait for a single irq,
887 * so don't bother setting up dma
888 */
889 return xfer->len / bytes_per_word >= rs->fifo_len;
890 }
891
rockchip_spi_setup(struct spi_device * spi)892 static int rockchip_spi_setup(struct spi_device *spi)
893 {
894 struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
895 u32 cr0;
896
897 if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH) && !rs->cs_high_supported) {
898 dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
899 return -EINVAL;
900 }
901
902 pm_runtime_get_sync(rs->dev);
903
904 cr0 = readl_relaxed(rs->regs + ROCKCHIP_SPI_CTRLR0);
905
906 cr0 |= ((spi->mode & 0x3) << CR0_SCPH_OFFSET);
907 if (spi->mode & SPI_CS_HIGH)
908 cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;
909
910 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
911
912 pm_runtime_put(rs->dev);
913
914 return 0;
915 }
916
rockchip_spi_misc_open(struct inode * inode,struct file * filp)917 static int rockchip_spi_misc_open(struct inode *inode, struct file *filp)
918 {
919 struct miscdevice *misc = filp->private_data;
920 struct spi_controller *ctlr = dev_get_drvdata(misc->parent);
921 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
922
923 pm_runtime_get_sync(rs->dev);
924
925 return 0;
926 }
927
rockchip_spi_misc_release(struct inode * inode,struct file * filp)928 static int rockchip_spi_misc_release(struct inode *inode, struct file *filp)
929 {
930 struct miscdevice *misc = filp->private_data;
931 struct spi_controller *ctlr = dev_get_drvdata(misc->parent);
932 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
933
934 pm_runtime_put(rs->dev);
935
936 return 0;
937 }
938
rockchip_spi_mmap(struct file * filp,struct vm_area_struct * vma)939 static int rockchip_spi_mmap(struct file *filp, struct vm_area_struct *vma)
940 {
941 struct miscdevice *misc = filp->private_data;
942 struct spi_controller *ctlr = dev_get_drvdata(misc->parent);
943 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
944 size_t size = vma->vm_end - vma->vm_start;
945 int err;
946
947 if (size > ROCKCHIP_SPI_REGISTER_SIZE) {
948 dev_warn(misc->parent, "mmap size is out of limitation\n");
949 return -EINVAL;
950 }
951
952 vma->vm_flags |= VM_IO;
953 vma->vm_flags |= (VM_DONTEXPAND | VM_DONTDUMP);
954 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
955
956 err = remap_pfn_range(vma, vma->vm_start,
957 __phys_to_pfn(rs->base_addr_phy),
958 size, vma->vm_page_prot);
959 if (err)
960 return -EAGAIN;
961
962 return 0;
963 }
964
965 static const struct file_operations rockchip_spi_misc_fops = {
966 .open = rockchip_spi_misc_open,
967 .release = rockchip_spi_misc_release,
968 .mmap = rockchip_spi_mmap,
969 };
970
rockchip_spi_probe(struct platform_device * pdev)971 static int rockchip_spi_probe(struct platform_device *pdev)
972 {
973 int ret;
974 struct rockchip_spi *rs;
975 struct spi_controller *ctlr;
976 struct resource *mem;
977 struct device_node *np = pdev->dev.of_node;
978 u32 rsd_nsecs, num_cs, csm;
979 bool slave_mode;
980 struct pinctrl *pinctrl = NULL;
981 const struct rockchip_spi_quirks *quirks_cfg;
982
983 slave_mode = of_property_read_bool(np, "spi-slave");
984
985 if (slave_mode)
986 ctlr = spi_alloc_slave(&pdev->dev,
987 sizeof(struct rockchip_spi));
988 else
989 ctlr = spi_alloc_master(&pdev->dev,
990 sizeof(struct rockchip_spi));
991
992 if (!ctlr)
993 return -ENOMEM;
994
995 platform_set_drvdata(pdev, ctlr);
996
997 rs = spi_controller_get_devdata(ctlr);
998 ctlr->slave = slave_mode;
999
1000 /* Get basic io resource and map it */
1001 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1002 rs->regs = devm_ioremap_resource(&pdev->dev, mem);
1003 if (IS_ERR(rs->regs)) {
1004 ret = PTR_ERR(rs->regs);
1005 goto err_put_ctlr;
1006 }
1007 rs->base_addr_phy = mem->start;
1008
1009 if (!has_acpi_companion(&pdev->dev))
1010 rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
1011 if (IS_ERR(rs->apb_pclk)) {
1012 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
1013 ret = PTR_ERR(rs->apb_pclk);
1014 goto err_put_ctlr;
1015 }
1016
1017 if (!has_acpi_companion(&pdev->dev))
1018 rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
1019 if (IS_ERR(rs->spiclk)) {
1020 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
1021 ret = PTR_ERR(rs->spiclk);
1022 goto err_put_ctlr;
1023 }
1024
1025 rs->sclk_in = devm_clk_get_optional(&pdev->dev, "sclk_in");
1026 if (IS_ERR(rs->sclk_in)) {
1027 dev_err(&pdev->dev, "Failed to get sclk_in\n");
1028 ret = PTR_ERR(rs->sclk_in);
1029 goto err_put_ctlr;
1030 }
1031
1032 ret = clk_prepare_enable(rs->apb_pclk);
1033 if (ret < 0) {
1034 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
1035 goto err_put_ctlr;
1036 }
1037
1038 ret = clk_prepare_enable(rs->spiclk);
1039 if (ret < 0) {
1040 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
1041 goto err_disable_apbclk;
1042 }
1043
1044 ret = clk_prepare_enable(rs->sclk_in);
1045 if (ret < 0) {
1046 dev_err(&pdev->dev, "Failed to enable sclk_in\n");
1047 goto err_disable_spiclk;
1048 }
1049
1050 spi_enable_chip(rs, false);
1051
1052 ret = platform_get_irq(pdev, 0);
1053 if (ret < 0)
1054 goto err_disable_sclk_in;
1055
1056 ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL,
1057 IRQF_ONESHOT, dev_name(&pdev->dev), ctlr);
1058 if (ret)
1059 goto err_disable_sclk_in;
1060
1061 rs->dev = &pdev->dev;
1062
1063 rs->freq = clk_get_rate(rs->spiclk);
1064 if (!rs->freq) {
1065 ret = device_property_read_u32(&pdev->dev, "clock-frequency", &rs->freq);
1066 if (ret) {
1067 dev_warn(rs->dev, "Failed to get clock or clock-frequency property\n");
1068 goto err_disable_sclk_in;
1069 }
1070 }
1071
1072 if (!device_property_read_u32(&pdev->dev, "rx-sample-delay-ns", &rsd_nsecs)) {
1073 /* rx sample delay is expressed in parent clock cycles (max 3) */
1074 u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8),
1075 1000000000 >> 8);
1076 if (!rsd) {
1077 dev_warn(rs->dev, "%u Hz are too slow to express %u ns delay\n",
1078 rs->freq, rsd_nsecs);
1079 } else if (rsd > CR0_RSD_MAX) {
1080 rsd = CR0_RSD_MAX;
1081 dev_warn(rs->dev, "%u Hz are too fast to express %u ns delay, clamping at %u ns\n",
1082 rs->freq, rsd_nsecs,
1083 CR0_RSD_MAX * 1000000000U / rs->freq);
1084 }
1085 rs->rsd = rsd;
1086 }
1087
1088 if (!device_property_read_u32(&pdev->dev, "csm", &csm)) {
1089 if (csm > CR0_CSM_ONE) {
1090 dev_warn(rs->dev, "The csm value %u exceeds the limit, clamping at %u\n",
1091 csm, CR0_CSM_ONE);
1092 csm = CR0_CSM_ONE;
1093 }
1094 rs->csm = csm;
1095 }
1096
1097 rs->version = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION);
1098 rs->fifo_len = get_fifo_len(rs);
1099 if (!rs->fifo_len) {
1100 dev_err(&pdev->dev, "Failed to get fifo length\n");
1101 ret = -EINVAL;
1102 goto err_disable_sclk_in;
1103 }
1104 quirks_cfg = device_get_match_data(&pdev->dev);
1105 if (quirks_cfg)
1106 rs->max_baud_div_in_cpha = quirks_cfg->max_baud_div_in_cpha;
1107
1108 pm_runtime_set_active(&pdev->dev);
1109 pm_runtime_enable(&pdev->dev);
1110
1111 ctlr->auto_runtime_pm = true;
1112 ctlr->bus_num = pdev->id;
1113 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST;
1114 if (slave_mode) {
1115 ctlr->mode_bits |= SPI_NO_CS;
1116 ctlr->slave_abort = rockchip_spi_slave_abort;
1117 } else {
1118 ctlr->flags = SPI_MASTER_GPIO_SS;
1119 ctlr->max_native_cs = ROCKCHIP_SPI_MAX_CS_NUM;
1120 /*
1121 * rk spi0 has two native cs, spi1..5 one cs only
1122 * if num-cs is missing in the dts, default to 1
1123 */
1124 if (device_property_read_u32(&pdev->dev, "num-cs", &num_cs))
1125 num_cs = 1;
1126 ctlr->num_chipselect = num_cs;
1127 ctlr->use_gpio_descriptors = true;
1128 }
1129 ctlr->dev.of_node = pdev->dev.of_node;
1130 ctlr->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4);
1131 ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX;
1132 ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);
1133
1134 ctlr->setup = rockchip_spi_setup;
1135 ctlr->set_cs = rockchip_spi_set_cs;
1136 ctlr->transfer_one = rockchip_spi_transfer_one;
1137 ctlr->max_transfer_size = rockchip_spi_max_transfer_size;
1138 ctlr->handle_err = rockchip_spi_handle_err;
1139
1140 ctlr->dma_tx = dma_request_chan(rs->dev, "tx");
1141 if (IS_ERR(ctlr->dma_tx)) {
1142 /* Check tx to see if we need defer probing driver */
1143 if (PTR_ERR(ctlr->dma_tx) == -EPROBE_DEFER) {
1144 ret = -EPROBE_DEFER;
1145 goto err_disable_pm_runtime;
1146 }
1147 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
1148 ctlr->dma_tx = NULL;
1149 }
1150
1151 ctlr->dma_rx = dma_request_chan(rs->dev, "rx");
1152 if (IS_ERR(ctlr->dma_rx)) {
1153 if (PTR_ERR(ctlr->dma_rx) == -EPROBE_DEFER) {
1154 ret = -EPROBE_DEFER;
1155 goto err_free_dma_tx;
1156 }
1157 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
1158 ctlr->dma_rx = NULL;
1159 }
1160
1161 if (ctlr->dma_tx && ctlr->dma_rx) {
1162 rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR;
1163 rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR;
1164 ctlr->can_dma = rockchip_spi_can_dma;
1165 }
1166
1167 rs->poll = device_property_read_bool(&pdev->dev, "rockchip,poll-only");
1168 init_completion(&rs->xfer_done);
1169 if (rs->poll && slave_mode) {
1170 dev_err(rs->dev, "only support rockchip,poll-only property in master mode\n");
1171 ret = -EINVAL;
1172 goto err_free_dma_rx;
1173 }
1174
1175 switch (rs->version) {
1176 case ROCKCHIP_SPI_VER2_TYPE2:
1177 rs->cs_high_supported = true;
1178 ctlr->mode_bits |= SPI_CS_HIGH;
1179 if (slave_mode)
1180 rs->cs_inactive = true;
1181 else
1182 rs->cs_inactive = false;
1183 break;
1184 default:
1185 rs->cs_inactive = false;
1186 break;
1187 }
1188 if (device_property_read_bool(&pdev->dev, "rockchip,cs-inactive-disable"))
1189 rs->cs_inactive = false;
1190
1191 pinctrl = devm_pinctrl_get(&pdev->dev);
1192 if (!IS_ERR(pinctrl)) {
1193 rs->high_speed_state = pinctrl_lookup_state(pinctrl, "high_speed");
1194 if (IS_ERR_OR_NULL(rs->high_speed_state)) {
1195 dev_warn(&pdev->dev, "no high_speed pinctrl state\n");
1196 rs->high_speed_state = NULL;
1197 }
1198 }
1199
1200 rs->ready = devm_gpiod_get_optional(&pdev->dev, "ready", GPIOD_OUT_HIGH);
1201 if (IS_ERR(rs->ready)) {
1202 ret = dev_err_probe(&pdev->dev, PTR_ERR(rs->ready),
1203 "invalid ready-gpios property in node\n");
1204 goto err_free_dma_rx;
1205 }
1206
1207 ret = devm_spi_register_controller(&pdev->dev, ctlr);
1208 if (ret < 0) {
1209 dev_err(&pdev->dev, "Failed to register controller\n");
1210 goto err_free_dma_rx;
1211 }
1212
1213 if (IS_ENABLED(CONFIG_SPI_ROCKCHIP_MISCDEV)) {
1214 char misc_name[20];
1215
1216 snprintf(misc_name, sizeof(misc_name), "rkspi-dev%d", ctlr->bus_num);
1217 rs->miscdev.minor = MISC_DYNAMIC_MINOR;
1218 rs->miscdev.name = misc_name;
1219 rs->miscdev.fops = &rockchip_spi_misc_fops;
1220 rs->miscdev.parent = &pdev->dev;
1221
1222 ret = misc_register(&rs->miscdev);
1223 if (ret)
1224 dev_err(&pdev->dev, "failed to register misc device %s\n", misc_name);
1225 else
1226 dev_info(&pdev->dev, "register misc device %s\n", misc_name);
1227 }
1228
1229 dev_info(rs->dev, "probed, poll=%d, rsd=%d, cs-inactive=%d, ready=%d\n",
1230 rs->poll, rs->rsd, rs->cs_inactive, rs->ready ? 1 : 0);
1231
1232 return 0;
1233
1234 err_free_dma_rx:
1235 if (ctlr->dma_rx)
1236 dma_release_channel(ctlr->dma_rx);
1237 err_free_dma_tx:
1238 if (ctlr->dma_tx)
1239 dma_release_channel(ctlr->dma_tx);
1240 err_disable_pm_runtime:
1241 pm_runtime_disable(&pdev->dev);
1242 err_disable_sclk_in:
1243 clk_disable_unprepare(rs->sclk_in);
1244 err_disable_spiclk:
1245 clk_disable_unprepare(rs->spiclk);
1246 err_disable_apbclk:
1247 clk_disable_unprepare(rs->apb_pclk);
1248 err_put_ctlr:
1249 spi_controller_put(ctlr);
1250
1251 return ret;
1252 }
1253
rockchip_spi_remove(struct platform_device * pdev)1254 static int rockchip_spi_remove(struct platform_device *pdev)
1255 {
1256 struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev));
1257 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1258
1259 if (IS_ENABLED(CONFIG_SPI_ROCKCHIP_MISCDEV))
1260 misc_deregister(&rs->miscdev);
1261
1262 pm_runtime_get_sync(&pdev->dev);
1263
1264 clk_disable_unprepare(rs->sclk_in);
1265 clk_disable_unprepare(rs->spiclk);
1266 clk_disable_unprepare(rs->apb_pclk);
1267
1268 pm_runtime_put_noidle(&pdev->dev);
1269 pm_runtime_disable(&pdev->dev);
1270 pm_runtime_set_suspended(&pdev->dev);
1271
1272 if (ctlr->dma_tx)
1273 dma_release_channel(ctlr->dma_tx);
1274 if (ctlr->dma_rx)
1275 dma_release_channel(ctlr->dma_rx);
1276
1277 spi_controller_put(ctlr);
1278
1279 return 0;
1280 }
1281
1282 #ifdef CONFIG_PM
rockchip_spi_runtime_suspend(struct device * dev)1283 static int rockchip_spi_runtime_suspend(struct device *dev)
1284 {
1285 struct spi_controller *ctlr = dev_get_drvdata(dev);
1286 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1287
1288 clk_disable_unprepare(rs->spiclk);
1289 clk_disable_unprepare(rs->apb_pclk);
1290
1291 return 0;
1292 }
1293
rockchip_spi_runtime_resume(struct device * dev)1294 static int rockchip_spi_runtime_resume(struct device *dev)
1295 {
1296 int ret;
1297 struct spi_controller *ctlr = dev_get_drvdata(dev);
1298 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1299
1300 ret = clk_prepare_enable(rs->apb_pclk);
1301 if (ret < 0)
1302 return ret;
1303
1304 ret = clk_prepare_enable(rs->spiclk);
1305 if (ret < 0)
1306 clk_disable_unprepare(rs->apb_pclk);
1307
1308 return 0;
1309 }
1310 #endif /* CONFIG_PM */
1311
1312 #ifdef CONFIG_PM_SLEEP
rockchip_spi_suspend(struct device * dev)1313 static int rockchip_spi_suspend(struct device *dev)
1314 {
1315 int ret;
1316 struct spi_controller *ctlr = dev_get_drvdata(dev);
1317
1318 ret = spi_controller_suspend(ctlr);
1319 if (ret < 0)
1320 return ret;
1321
1322 /* Avoid redundant clock disable */
1323 if (!pm_runtime_status_suspended(dev))
1324 rockchip_spi_runtime_suspend(dev);
1325
1326 pinctrl_pm_select_sleep_state(dev);
1327
1328 return 0;
1329 }
1330
rockchip_spi_resume(struct device * dev)1331 static int rockchip_spi_resume(struct device *dev)
1332 {
1333 int ret;
1334 struct spi_controller *ctlr = dev_get_drvdata(dev);
1335
1336 pinctrl_pm_select_default_state(dev);
1337
1338 if (!pm_runtime_status_suspended(dev)) {
1339 ret = rockchip_spi_runtime_resume(dev);
1340 if (ret < 0)
1341 return ret;
1342 }
1343
1344 ret = spi_controller_resume(ctlr);
1345 if (ret < 0)
1346 rockchip_spi_runtime_suspend(dev);
1347
1348 return 0;
1349 }
1350 #endif /* CONFIG_PM_SLEEP */
1351
1352 static const struct dev_pm_ops rockchip_spi_pm = {
1353 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
1354 SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
1355 rockchip_spi_runtime_resume, NULL)
1356 };
1357
1358 static const struct rockchip_spi_quirks rockchip_spi_quirks_cfg = {
1359 .max_baud_div_in_cpha = 4,
1360 };
1361
1362 static const struct of_device_id rockchip_spi_dt_match[] = {
1363 {
1364 .compatible = "rockchip,px30-spi",
1365 .data = &rockchip_spi_quirks_cfg,
1366 },
1367 { .compatible = "rockchip,rk3036-spi", },
1368 { .compatible = "rockchip,rk3066-spi", },
1369 { .compatible = "rockchip,rk3188-spi", },
1370 { .compatible = "rockchip,rk3228-spi", },
1371 { .compatible = "rockchip,rk3288-spi", },
1372 { .compatible = "rockchip,rk3308-spi", },
1373 { .compatible = "rockchip,rk3328-spi", },
1374 { .compatible = "rockchip,rk3368-spi", },
1375 { .compatible = "rockchip,rk3399-spi", },
1376 { .compatible = "rockchip,rv1106-spi", },
1377 { .compatible = "rockchip,rv1108-spi", },
1378 { .compatible = "rockchip,rv1126-spi", },
1379 { },
1380 };
1381 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
1382
1383 static struct platform_driver rockchip_spi_driver = {
1384 .driver = {
1385 .name = DRIVER_NAME,
1386 .pm = &rockchip_spi_pm,
1387 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
1388 },
1389 .probe = rockchip_spi_probe,
1390 .remove = rockchip_spi_remove,
1391 };
1392
1393 module_platform_driver(rockchip_spi_driver);
1394
1395 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
1396 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
1397 MODULE_LICENSE("GPL v2");
1398