1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
4*4882a593Smuzhiyun * Copyright (C) 2013, Intel Corporation
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #ifndef SPI_PXA2XX_H
8*4882a593Smuzhiyun #define SPI_PXA2XX_H
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/atomic.h>
11*4882a593Smuzhiyun #include <linux/dmaengine.h>
12*4882a593Smuzhiyun #include <linux/errno.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/interrupt.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/pxa2xx_ssp.h>
17*4882a593Smuzhiyun #include <linux/scatterlist.h>
18*4882a593Smuzhiyun #include <linux/sizes.h>
19*4882a593Smuzhiyun #include <linux/spi/spi.h>
20*4882a593Smuzhiyun #include <linux/spi/pxa2xx_spi.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun struct driver_data {
23*4882a593Smuzhiyun /* Driver model hookup */
24*4882a593Smuzhiyun struct platform_device *pdev;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* SSP Info */
27*4882a593Smuzhiyun struct ssp_device *ssp;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* SPI framework hookup */
30*4882a593Smuzhiyun enum pxa_ssp_type ssp_type;
31*4882a593Smuzhiyun struct spi_controller *controller;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* PXA hookup */
34*4882a593Smuzhiyun struct pxa2xx_spi_controller *controller_info;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* SSP register addresses */
37*4882a593Smuzhiyun void __iomem *ioaddr;
38*4882a593Smuzhiyun phys_addr_t ssdr_physical;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* SSP masks*/
41*4882a593Smuzhiyun u32 dma_cr1;
42*4882a593Smuzhiyun u32 int_cr1;
43*4882a593Smuzhiyun u32 clear_sr;
44*4882a593Smuzhiyun u32 mask_sr;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* DMA engine support */
47*4882a593Smuzhiyun atomic_t dma_running;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* Current transfer state info */
50*4882a593Smuzhiyun void *tx;
51*4882a593Smuzhiyun void *tx_end;
52*4882a593Smuzhiyun void *rx;
53*4882a593Smuzhiyun void *rx_end;
54*4882a593Smuzhiyun u8 n_bytes;
55*4882a593Smuzhiyun int (*write)(struct driver_data *drv_data);
56*4882a593Smuzhiyun int (*read)(struct driver_data *drv_data);
57*4882a593Smuzhiyun irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
58*4882a593Smuzhiyun void (*cs_control)(u32 command);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun void __iomem *lpss_base;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* GPIOs for chip selects */
63*4882a593Smuzhiyun struct gpio_desc **cs_gpiods;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* Optional slave FIFO ready signal */
66*4882a593Smuzhiyun struct gpio_desc *gpiod_ready;
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun struct chip_data {
70*4882a593Smuzhiyun u32 cr1;
71*4882a593Smuzhiyun u32 dds_rate;
72*4882a593Smuzhiyun u32 timeout;
73*4882a593Smuzhiyun u8 n_bytes;
74*4882a593Smuzhiyun u32 dma_burst_size;
75*4882a593Smuzhiyun u32 threshold;
76*4882a593Smuzhiyun u32 dma_threshold;
77*4882a593Smuzhiyun u16 lpss_rx_threshold;
78*4882a593Smuzhiyun u16 lpss_tx_threshold;
79*4882a593Smuzhiyun u8 enable_dma;
80*4882a593Smuzhiyun union {
81*4882a593Smuzhiyun struct gpio_desc *gpiod_cs;
82*4882a593Smuzhiyun unsigned int frm;
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun int gpio_cs_inverted;
85*4882a593Smuzhiyun int (*write)(struct driver_data *drv_data);
86*4882a593Smuzhiyun int (*read)(struct driver_data *drv_data);
87*4882a593Smuzhiyun void (*cs_control)(u32 command);
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun
pxa2xx_spi_read(const struct driver_data * drv_data,unsigned reg)90*4882a593Smuzhiyun static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data,
91*4882a593Smuzhiyun unsigned reg)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun return __raw_readl(drv_data->ioaddr + reg);
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
pxa2xx_spi_write(const struct driver_data * drv_data,unsigned reg,u32 val)96*4882a593Smuzhiyun static inline void pxa2xx_spi_write(const struct driver_data *drv_data,
97*4882a593Smuzhiyun unsigned reg, u32 val)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun __raw_writel(val, drv_data->ioaddr + reg);
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun #define DMA_ALIGNMENT 8
103*4882a593Smuzhiyun
pxa25x_ssp_comp(struct driver_data * drv_data)104*4882a593Smuzhiyun static inline int pxa25x_ssp_comp(struct driver_data *drv_data)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun switch (drv_data->ssp_type) {
107*4882a593Smuzhiyun case PXA25x_SSP:
108*4882a593Smuzhiyun case CE4100_SSP:
109*4882a593Smuzhiyun case QUARK_X1000_SSP:
110*4882a593Smuzhiyun return 1;
111*4882a593Smuzhiyun default:
112*4882a593Smuzhiyun return 0;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun
write_SSSR_CS(struct driver_data * drv_data,u32 val)116*4882a593Smuzhiyun static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun if (drv_data->ssp_type == CE4100_SSP ||
119*4882a593Smuzhiyun drv_data->ssp_type == QUARK_X1000_SSP)
120*4882a593Smuzhiyun val |= pxa2xx_spi_read(drv_data, SSSR) & SSSR_ALT_FRM_MASK;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun pxa2xx_spi_write(drv_data, SSSR, val);
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun extern int pxa2xx_spi_flush(struct driver_data *drv_data);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun #define MAX_DMA_LEN SZ_64K
128*4882a593Smuzhiyun #define DEFAULT_DMA_CR1 (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data);
131*4882a593Smuzhiyun extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data,
132*4882a593Smuzhiyun struct spi_transfer *xfer);
133*4882a593Smuzhiyun extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
134*4882a593Smuzhiyun extern void pxa2xx_spi_dma_stop(struct driver_data *drv_data);
135*4882a593Smuzhiyun extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
136*4882a593Smuzhiyun extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
137*4882a593Smuzhiyun extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
138*4882a593Smuzhiyun struct spi_device *spi,
139*4882a593Smuzhiyun u8 bits_per_word,
140*4882a593Smuzhiyun u32 *burst_code,
141*4882a593Smuzhiyun u32 *threshold);
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun #endif /* SPI_PXA2XX_H */
144