1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * OpenCores tiny SPI master driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * https://opencores.org/project,tiny_spi
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2011 Thomas Chou <thomas@wytron.com.tw>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Based on spi_s3c24xx.c, which is:
10*4882a593Smuzhiyun * Copyright (c) 2006 Ben Dooks
11*4882a593Smuzhiyun * Copyright (c) 2006 Simtec Electronics
12*4882a593Smuzhiyun * Ben Dooks <ben@simtec.co.uk>
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/interrupt.h>
16*4882a593Smuzhiyun #include <linux/errno.h>
17*4882a593Smuzhiyun #include <linux/module.h>
18*4882a593Smuzhiyun #include <linux/platform_device.h>
19*4882a593Smuzhiyun #include <linux/spi/spi.h>
20*4882a593Smuzhiyun #include <linux/spi/spi_bitbang.h>
21*4882a593Smuzhiyun #include <linux/spi/spi_oc_tiny.h>
22*4882a593Smuzhiyun #include <linux/io.h>
23*4882a593Smuzhiyun #include <linux/of.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define DRV_NAME "spi_oc_tiny"
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define TINY_SPI_RXDATA 0
28*4882a593Smuzhiyun #define TINY_SPI_TXDATA 4
29*4882a593Smuzhiyun #define TINY_SPI_STATUS 8
30*4882a593Smuzhiyun #define TINY_SPI_CONTROL 12
31*4882a593Smuzhiyun #define TINY_SPI_BAUD 16
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define TINY_SPI_STATUS_TXE 0x1
34*4882a593Smuzhiyun #define TINY_SPI_STATUS_TXR 0x2
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun struct tiny_spi {
37*4882a593Smuzhiyun /* bitbang has to be first */
38*4882a593Smuzhiyun struct spi_bitbang bitbang;
39*4882a593Smuzhiyun struct completion done;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun void __iomem *base;
42*4882a593Smuzhiyun int irq;
43*4882a593Smuzhiyun unsigned int freq;
44*4882a593Smuzhiyun unsigned int baudwidth;
45*4882a593Smuzhiyun unsigned int baud;
46*4882a593Smuzhiyun unsigned int speed_hz;
47*4882a593Smuzhiyun unsigned int mode;
48*4882a593Smuzhiyun unsigned int len;
49*4882a593Smuzhiyun unsigned int txc, rxc;
50*4882a593Smuzhiyun const u8 *txp;
51*4882a593Smuzhiyun u8 *rxp;
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
tiny_spi_to_hw(struct spi_device * sdev)54*4882a593Smuzhiyun static inline struct tiny_spi *tiny_spi_to_hw(struct spi_device *sdev)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun return spi_master_get_devdata(sdev->master);
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
tiny_spi_baud(struct spi_device * spi,unsigned int hz)59*4882a593Smuzhiyun static unsigned int tiny_spi_baud(struct spi_device *spi, unsigned int hz)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun struct tiny_spi *hw = tiny_spi_to_hw(spi);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun return min(DIV_ROUND_UP(hw->freq, hz * 2), (1U << hw->baudwidth)) - 1;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
tiny_spi_setup_transfer(struct spi_device * spi,struct spi_transfer * t)66*4882a593Smuzhiyun static int tiny_spi_setup_transfer(struct spi_device *spi,
67*4882a593Smuzhiyun struct spi_transfer *t)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun struct tiny_spi *hw = tiny_spi_to_hw(spi);
70*4882a593Smuzhiyun unsigned int baud = hw->baud;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun if (t) {
73*4882a593Smuzhiyun if (t->speed_hz && t->speed_hz != hw->speed_hz)
74*4882a593Smuzhiyun baud = tiny_spi_baud(spi, t->speed_hz);
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun writel(baud, hw->base + TINY_SPI_BAUD);
77*4882a593Smuzhiyun writel(hw->mode, hw->base + TINY_SPI_CONTROL);
78*4882a593Smuzhiyun return 0;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
tiny_spi_setup(struct spi_device * spi)81*4882a593Smuzhiyun static int tiny_spi_setup(struct spi_device *spi)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun struct tiny_spi *hw = tiny_spi_to_hw(spi);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun if (spi->max_speed_hz != hw->speed_hz) {
86*4882a593Smuzhiyun hw->speed_hz = spi->max_speed_hz;
87*4882a593Smuzhiyun hw->baud = tiny_spi_baud(spi, hw->speed_hz);
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun hw->mode = spi->mode & (SPI_CPOL | SPI_CPHA);
90*4882a593Smuzhiyun return 0;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
tiny_spi_wait_txr(struct tiny_spi * hw)93*4882a593Smuzhiyun static inline void tiny_spi_wait_txr(struct tiny_spi *hw)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun while (!(readb(hw->base + TINY_SPI_STATUS) &
96*4882a593Smuzhiyun TINY_SPI_STATUS_TXR))
97*4882a593Smuzhiyun cpu_relax();
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
tiny_spi_wait_txe(struct tiny_spi * hw)100*4882a593Smuzhiyun static inline void tiny_spi_wait_txe(struct tiny_spi *hw)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun while (!(readb(hw->base + TINY_SPI_STATUS) &
103*4882a593Smuzhiyun TINY_SPI_STATUS_TXE))
104*4882a593Smuzhiyun cpu_relax();
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
tiny_spi_txrx_bufs(struct spi_device * spi,struct spi_transfer * t)107*4882a593Smuzhiyun static int tiny_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun struct tiny_spi *hw = tiny_spi_to_hw(spi);
110*4882a593Smuzhiyun const u8 *txp = t->tx_buf;
111*4882a593Smuzhiyun u8 *rxp = t->rx_buf;
112*4882a593Smuzhiyun unsigned int i;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun if (hw->irq >= 0) {
115*4882a593Smuzhiyun /* use interrupt driven data transfer */
116*4882a593Smuzhiyun hw->len = t->len;
117*4882a593Smuzhiyun hw->txp = t->tx_buf;
118*4882a593Smuzhiyun hw->rxp = t->rx_buf;
119*4882a593Smuzhiyun hw->txc = 0;
120*4882a593Smuzhiyun hw->rxc = 0;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun /* send the first byte */
123*4882a593Smuzhiyun if (t->len > 1) {
124*4882a593Smuzhiyun writeb(hw->txp ? *hw->txp++ : 0,
125*4882a593Smuzhiyun hw->base + TINY_SPI_TXDATA);
126*4882a593Smuzhiyun hw->txc++;
127*4882a593Smuzhiyun writeb(hw->txp ? *hw->txp++ : 0,
128*4882a593Smuzhiyun hw->base + TINY_SPI_TXDATA);
129*4882a593Smuzhiyun hw->txc++;
130*4882a593Smuzhiyun writeb(TINY_SPI_STATUS_TXR, hw->base + TINY_SPI_STATUS);
131*4882a593Smuzhiyun } else {
132*4882a593Smuzhiyun writeb(hw->txp ? *hw->txp++ : 0,
133*4882a593Smuzhiyun hw->base + TINY_SPI_TXDATA);
134*4882a593Smuzhiyun hw->txc++;
135*4882a593Smuzhiyun writeb(TINY_SPI_STATUS_TXE, hw->base + TINY_SPI_STATUS);
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun wait_for_completion(&hw->done);
139*4882a593Smuzhiyun } else {
140*4882a593Smuzhiyun /* we need to tighten the transfer loop */
141*4882a593Smuzhiyun writeb(txp ? *txp++ : 0, hw->base + TINY_SPI_TXDATA);
142*4882a593Smuzhiyun for (i = 1; i < t->len; i++) {
143*4882a593Smuzhiyun writeb(txp ? *txp++ : 0, hw->base + TINY_SPI_TXDATA);
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun if (rxp || (i != t->len - 1))
146*4882a593Smuzhiyun tiny_spi_wait_txr(hw);
147*4882a593Smuzhiyun if (rxp)
148*4882a593Smuzhiyun *rxp++ = readb(hw->base + TINY_SPI_TXDATA);
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun tiny_spi_wait_txe(hw);
151*4882a593Smuzhiyun if (rxp)
152*4882a593Smuzhiyun *rxp++ = readb(hw->base + TINY_SPI_RXDATA);
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun return t->len;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
tiny_spi_irq(int irq,void * dev)158*4882a593Smuzhiyun static irqreturn_t tiny_spi_irq(int irq, void *dev)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun struct tiny_spi *hw = dev;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun writeb(0, hw->base + TINY_SPI_STATUS);
163*4882a593Smuzhiyun if (hw->rxc + 1 == hw->len) {
164*4882a593Smuzhiyun if (hw->rxp)
165*4882a593Smuzhiyun *hw->rxp++ = readb(hw->base + TINY_SPI_RXDATA);
166*4882a593Smuzhiyun hw->rxc++;
167*4882a593Smuzhiyun complete(&hw->done);
168*4882a593Smuzhiyun } else {
169*4882a593Smuzhiyun if (hw->rxp)
170*4882a593Smuzhiyun *hw->rxp++ = readb(hw->base + TINY_SPI_TXDATA);
171*4882a593Smuzhiyun hw->rxc++;
172*4882a593Smuzhiyun if (hw->txc < hw->len) {
173*4882a593Smuzhiyun writeb(hw->txp ? *hw->txp++ : 0,
174*4882a593Smuzhiyun hw->base + TINY_SPI_TXDATA);
175*4882a593Smuzhiyun hw->txc++;
176*4882a593Smuzhiyun writeb(TINY_SPI_STATUS_TXR,
177*4882a593Smuzhiyun hw->base + TINY_SPI_STATUS);
178*4882a593Smuzhiyun } else {
179*4882a593Smuzhiyun writeb(TINY_SPI_STATUS_TXE,
180*4882a593Smuzhiyun hw->base + TINY_SPI_STATUS);
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun return IRQ_HANDLED;
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun #ifdef CONFIG_OF
187*4882a593Smuzhiyun #include <linux/of_gpio.h>
188*4882a593Smuzhiyun
tiny_spi_of_probe(struct platform_device * pdev)189*4882a593Smuzhiyun static int tiny_spi_of_probe(struct platform_device *pdev)
190*4882a593Smuzhiyun {
191*4882a593Smuzhiyun struct tiny_spi *hw = platform_get_drvdata(pdev);
192*4882a593Smuzhiyun struct device_node *np = pdev->dev.of_node;
193*4882a593Smuzhiyun u32 val;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun if (!np)
196*4882a593Smuzhiyun return 0;
197*4882a593Smuzhiyun hw->bitbang.master->dev.of_node = pdev->dev.of_node;
198*4882a593Smuzhiyun if (!of_property_read_u32(np, "clock-frequency", &val))
199*4882a593Smuzhiyun hw->freq = val;
200*4882a593Smuzhiyun if (!of_property_read_u32(np, "baud-width", &val))
201*4882a593Smuzhiyun hw->baudwidth = val;
202*4882a593Smuzhiyun return 0;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun #else /* !CONFIG_OF */
tiny_spi_of_probe(struct platform_device * pdev)205*4882a593Smuzhiyun static int tiny_spi_of_probe(struct platform_device *pdev)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun return 0;
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun #endif /* CONFIG_OF */
210*4882a593Smuzhiyun
tiny_spi_probe(struct platform_device * pdev)211*4882a593Smuzhiyun static int tiny_spi_probe(struct platform_device *pdev)
212*4882a593Smuzhiyun {
213*4882a593Smuzhiyun struct tiny_spi_platform_data *platp = dev_get_platdata(&pdev->dev);
214*4882a593Smuzhiyun struct tiny_spi *hw;
215*4882a593Smuzhiyun struct spi_master *master;
216*4882a593Smuzhiyun int err = -ENODEV;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun master = spi_alloc_master(&pdev->dev, sizeof(struct tiny_spi));
219*4882a593Smuzhiyun if (!master)
220*4882a593Smuzhiyun return err;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun /* setup the master state. */
223*4882a593Smuzhiyun master->bus_num = pdev->id;
224*4882a593Smuzhiyun master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
225*4882a593Smuzhiyun master->setup = tiny_spi_setup;
226*4882a593Smuzhiyun master->use_gpio_descriptors = true;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun hw = spi_master_get_devdata(master);
229*4882a593Smuzhiyun platform_set_drvdata(pdev, hw);
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun /* setup the state for the bitbang driver */
232*4882a593Smuzhiyun hw->bitbang.master = master;
233*4882a593Smuzhiyun hw->bitbang.setup_transfer = tiny_spi_setup_transfer;
234*4882a593Smuzhiyun hw->bitbang.txrx_bufs = tiny_spi_txrx_bufs;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun /* find and map our resources */
237*4882a593Smuzhiyun hw->base = devm_platform_ioremap_resource(pdev, 0);
238*4882a593Smuzhiyun if (IS_ERR(hw->base)) {
239*4882a593Smuzhiyun err = PTR_ERR(hw->base);
240*4882a593Smuzhiyun goto exit;
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun /* irq is optional */
243*4882a593Smuzhiyun hw->irq = platform_get_irq(pdev, 0);
244*4882a593Smuzhiyun if (hw->irq >= 0) {
245*4882a593Smuzhiyun init_completion(&hw->done);
246*4882a593Smuzhiyun err = devm_request_irq(&pdev->dev, hw->irq, tiny_spi_irq, 0,
247*4882a593Smuzhiyun pdev->name, hw);
248*4882a593Smuzhiyun if (err)
249*4882a593Smuzhiyun goto exit;
250*4882a593Smuzhiyun }
251*4882a593Smuzhiyun /* find platform data */
252*4882a593Smuzhiyun if (platp) {
253*4882a593Smuzhiyun hw->freq = platp->freq;
254*4882a593Smuzhiyun hw->baudwidth = platp->baudwidth;
255*4882a593Smuzhiyun } else {
256*4882a593Smuzhiyun err = tiny_spi_of_probe(pdev);
257*4882a593Smuzhiyun if (err)
258*4882a593Smuzhiyun goto exit;
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun /* register our spi controller */
262*4882a593Smuzhiyun err = spi_bitbang_start(&hw->bitbang);
263*4882a593Smuzhiyun if (err)
264*4882a593Smuzhiyun goto exit;
265*4882a593Smuzhiyun dev_info(&pdev->dev, "base %p, irq %d\n", hw->base, hw->irq);
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun return 0;
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun exit:
270*4882a593Smuzhiyun spi_master_put(master);
271*4882a593Smuzhiyun return err;
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun
tiny_spi_remove(struct platform_device * pdev)274*4882a593Smuzhiyun static int tiny_spi_remove(struct platform_device *pdev)
275*4882a593Smuzhiyun {
276*4882a593Smuzhiyun struct tiny_spi *hw = platform_get_drvdata(pdev);
277*4882a593Smuzhiyun struct spi_master *master = hw->bitbang.master;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun spi_bitbang_stop(&hw->bitbang);
280*4882a593Smuzhiyun spi_master_put(master);
281*4882a593Smuzhiyun return 0;
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun #ifdef CONFIG_OF
285*4882a593Smuzhiyun static const struct of_device_id tiny_spi_match[] = {
286*4882a593Smuzhiyun { .compatible = "opencores,tiny-spi-rtlsvn2", },
287*4882a593Smuzhiyun {},
288*4882a593Smuzhiyun };
289*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, tiny_spi_match);
290*4882a593Smuzhiyun #endif /* CONFIG_OF */
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun static struct platform_driver tiny_spi_driver = {
293*4882a593Smuzhiyun .probe = tiny_spi_probe,
294*4882a593Smuzhiyun .remove = tiny_spi_remove,
295*4882a593Smuzhiyun .driver = {
296*4882a593Smuzhiyun .name = DRV_NAME,
297*4882a593Smuzhiyun .pm = NULL,
298*4882a593Smuzhiyun .of_match_table = of_match_ptr(tiny_spi_match),
299*4882a593Smuzhiyun },
300*4882a593Smuzhiyun };
301*4882a593Smuzhiyun module_platform_driver(tiny_spi_driver);
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun MODULE_DESCRIPTION("OpenCores tiny SPI driver");
304*4882a593Smuzhiyun MODULE_AUTHOR("Thomas Chou <thomas@wytron.com.tw>");
305*4882a593Smuzhiyun MODULE_LICENSE("GPL");
306*4882a593Smuzhiyun MODULE_ALIAS("platform:" DRV_NAME);
307