1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2016 Broadcom Limited
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/device.h>
7*4882a593Smuzhiyun #include <linux/io.h>
8*4882a593Smuzhiyun #include <linux/ioport.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/of.h>
11*4882a593Smuzhiyun #include <linux/of_address.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun #include <linux/slab.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include "spi-bcm-qspi.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define INTR_BASE_BIT_SHIFT 0x02
18*4882a593Smuzhiyun #define INTR_COUNT 0x07
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun struct bcm_iproc_intc {
21*4882a593Smuzhiyun struct bcm_qspi_soc_intc soc_intc;
22*4882a593Smuzhiyun struct platform_device *pdev;
23*4882a593Smuzhiyun void __iomem *int_reg;
24*4882a593Smuzhiyun void __iomem *int_status_reg;
25*4882a593Smuzhiyun spinlock_t soclock;
26*4882a593Smuzhiyun bool big_endian;
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
bcm_iproc_qspi_get_l2_int_status(struct bcm_qspi_soc_intc * soc_intc)29*4882a593Smuzhiyun static u32 bcm_iproc_qspi_get_l2_int_status(struct bcm_qspi_soc_intc *soc_intc)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun struct bcm_iproc_intc *priv =
32*4882a593Smuzhiyun container_of(soc_intc, struct bcm_iproc_intc, soc_intc);
33*4882a593Smuzhiyun void __iomem *mmio = priv->int_status_reg;
34*4882a593Smuzhiyun int i;
35*4882a593Smuzhiyun u32 val = 0, sts = 0;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun for (i = 0; i < INTR_COUNT; i++) {
38*4882a593Smuzhiyun if (bcm_qspi_readl(priv->big_endian, mmio + (i * 4)))
39*4882a593Smuzhiyun val |= 1UL << i;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun if (val & INTR_MSPI_DONE_MASK)
43*4882a593Smuzhiyun sts |= MSPI_DONE;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun if (val & BSPI_LR_INTERRUPTS_ALL)
46*4882a593Smuzhiyun sts |= BSPI_DONE;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun if (val & BSPI_LR_INTERRUPTS_ERROR)
49*4882a593Smuzhiyun sts |= BSPI_ERR;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun return sts;
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
bcm_iproc_qspi_int_ack(struct bcm_qspi_soc_intc * soc_intc,int type)54*4882a593Smuzhiyun static void bcm_iproc_qspi_int_ack(struct bcm_qspi_soc_intc *soc_intc, int type)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun struct bcm_iproc_intc *priv =
57*4882a593Smuzhiyun container_of(soc_intc, struct bcm_iproc_intc, soc_intc);
58*4882a593Smuzhiyun void __iomem *mmio = priv->int_status_reg;
59*4882a593Smuzhiyun u32 mask = get_qspi_mask(type);
60*4882a593Smuzhiyun int i;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun for (i = 0; i < INTR_COUNT; i++) {
63*4882a593Smuzhiyun if (mask & (1UL << i))
64*4882a593Smuzhiyun bcm_qspi_writel(priv->big_endian, 1, mmio + (i * 4));
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
bcm_iproc_qspi_int_set(struct bcm_qspi_soc_intc * soc_intc,int type,bool en)68*4882a593Smuzhiyun static void bcm_iproc_qspi_int_set(struct bcm_qspi_soc_intc *soc_intc, int type,
69*4882a593Smuzhiyun bool en)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun struct bcm_iproc_intc *priv =
72*4882a593Smuzhiyun container_of(soc_intc, struct bcm_iproc_intc, soc_intc);
73*4882a593Smuzhiyun void __iomem *mmio = priv->int_reg;
74*4882a593Smuzhiyun u32 mask = get_qspi_mask(type);
75*4882a593Smuzhiyun u32 val;
76*4882a593Smuzhiyun unsigned long flags;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun spin_lock_irqsave(&priv->soclock, flags);
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun val = bcm_qspi_readl(priv->big_endian, mmio);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun if (en)
83*4882a593Smuzhiyun val = val | (mask << INTR_BASE_BIT_SHIFT);
84*4882a593Smuzhiyun else
85*4882a593Smuzhiyun val = val & ~(mask << INTR_BASE_BIT_SHIFT);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun bcm_qspi_writel(priv->big_endian, val, mmio);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun spin_unlock_irqrestore(&priv->soclock, flags);
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
bcm_iproc_probe(struct platform_device * pdev)92*4882a593Smuzhiyun static int bcm_iproc_probe(struct platform_device *pdev)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun struct device *dev = &pdev->dev;
95*4882a593Smuzhiyun struct bcm_iproc_intc *priv;
96*4882a593Smuzhiyun struct bcm_qspi_soc_intc *soc_intc;
97*4882a593Smuzhiyun struct resource *res;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
100*4882a593Smuzhiyun if (!priv)
101*4882a593Smuzhiyun return -ENOMEM;
102*4882a593Smuzhiyun soc_intc = &priv->soc_intc;
103*4882a593Smuzhiyun priv->pdev = pdev;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun spin_lock_init(&priv->soclock);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr_regs");
108*4882a593Smuzhiyun priv->int_reg = devm_ioremap_resource(dev, res);
109*4882a593Smuzhiyun if (IS_ERR(priv->int_reg))
110*4882a593Smuzhiyun return PTR_ERR(priv->int_reg);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
113*4882a593Smuzhiyun "intr_status_reg");
114*4882a593Smuzhiyun priv->int_status_reg = devm_ioremap_resource(dev, res);
115*4882a593Smuzhiyun if (IS_ERR(priv->int_status_reg))
116*4882a593Smuzhiyun return PTR_ERR(priv->int_status_reg);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun priv->big_endian = of_device_is_big_endian(dev->of_node);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun bcm_iproc_qspi_int_ack(soc_intc, MSPI_BSPI_DONE);
121*4882a593Smuzhiyun bcm_iproc_qspi_int_set(soc_intc, MSPI_BSPI_DONE, false);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun soc_intc->bcm_qspi_int_ack = bcm_iproc_qspi_int_ack;
124*4882a593Smuzhiyun soc_intc->bcm_qspi_int_set = bcm_iproc_qspi_int_set;
125*4882a593Smuzhiyun soc_intc->bcm_qspi_get_int_status = bcm_iproc_qspi_get_l2_int_status;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun return bcm_qspi_probe(pdev, soc_intc);
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
bcm_iproc_remove(struct platform_device * pdev)130*4882a593Smuzhiyun static int bcm_iproc_remove(struct platform_device *pdev)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun return bcm_qspi_remove(pdev);
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun static const struct of_device_id bcm_iproc_of_match[] = {
136*4882a593Smuzhiyun { .compatible = "brcm,spi-nsp-qspi" },
137*4882a593Smuzhiyun { .compatible = "brcm,spi-ns2-qspi" },
138*4882a593Smuzhiyun {},
139*4882a593Smuzhiyun };
140*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, bcm_iproc_of_match);
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun static struct platform_driver bcm_iproc_driver = {
143*4882a593Smuzhiyun .probe = bcm_iproc_probe,
144*4882a593Smuzhiyun .remove = bcm_iproc_remove,
145*4882a593Smuzhiyun .driver = {
146*4882a593Smuzhiyun .name = "bcm_iproc",
147*4882a593Smuzhiyun .pm = &bcm_qspi_pm_ops,
148*4882a593Smuzhiyun .of_match_table = bcm_iproc_of_match,
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun };
151*4882a593Smuzhiyun module_platform_driver(bcm_iproc_driver);
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
154*4882a593Smuzhiyun MODULE_AUTHOR("Kamal Dasu");
155*4882a593Smuzhiyun MODULE_DESCRIPTION("SPI flash driver for Broadcom iProc SoCs");
156