1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 // Copyright (C) 2008 Juergen Beisert
4
5 #include <linux/clk.h>
6 #include <linux/completion.h>
7 #include <linux/delay.h>
8 #include <linux/dmaengine.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/err.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/irq.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/pinctrl/consumer.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/slab.h>
20 #include <linux/spi/spi.h>
21 #include <linux/spi/spi_bitbang.h>
22 #include <linux/types.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/property.h>
26
27 #include <linux/platform_data/dma-imx.h>
28
29 #define DRIVER_NAME "spi_imx"
30
31 static bool use_dma = true;
32 module_param(use_dma, bool, 0644);
33 MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)");
34
35 #define MXC_RPM_TIMEOUT 2000 /* 2000ms */
36
37 #define MXC_CSPIRXDATA 0x00
38 #define MXC_CSPITXDATA 0x04
39 #define MXC_CSPICTRL 0x08
40 #define MXC_CSPIINT 0x0c
41 #define MXC_RESET 0x1c
42
43 /* generic defines to abstract from the different register layouts */
44 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
45 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
46 #define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */
47
48 /* The maximum bytes that a sdma BD can transfer. */
49 #define MAX_SDMA_BD_BYTES (1 << 15)
50 #define MX51_ECSPI_CTRL_MAX_BURST 512
51 /* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/
52 #define MX53_MAX_TRANSFER_BYTES 512
53
54 enum spi_imx_devtype {
55 IMX1_CSPI,
56 IMX21_CSPI,
57 IMX27_CSPI,
58 IMX31_CSPI,
59 IMX35_CSPI, /* CSPI on all i.mx except above */
60 IMX51_ECSPI, /* ECSPI on i.mx51 */
61 IMX53_ECSPI, /* ECSPI on i.mx53 and later */
62 };
63
64 struct spi_imx_data;
65
66 struct spi_imx_devtype_data {
67 void (*intctrl)(struct spi_imx_data *, int);
68 int (*prepare_message)(struct spi_imx_data *, struct spi_message *);
69 int (*prepare_transfer)(struct spi_imx_data *, struct spi_device *);
70 void (*trigger)(struct spi_imx_data *);
71 int (*rx_available)(struct spi_imx_data *);
72 void (*reset)(struct spi_imx_data *);
73 void (*setup_wml)(struct spi_imx_data *);
74 void (*disable)(struct spi_imx_data *);
75 void (*disable_dma)(struct spi_imx_data *);
76 bool has_dmamode;
77 bool has_slavemode;
78 unsigned int fifo_size;
79 bool dynamic_burst;
80 enum spi_imx_devtype devtype;
81 };
82
83 struct spi_imx_data {
84 struct spi_bitbang bitbang;
85 struct device *dev;
86
87 struct completion xfer_done;
88 void __iomem *base;
89 unsigned long base_phys;
90
91 struct clk *clk_per;
92 struct clk *clk_ipg;
93 unsigned long spi_clk;
94 unsigned int spi_bus_clk;
95
96 unsigned int bits_per_word;
97 unsigned int spi_drctl;
98
99 unsigned int count, remainder;
100 void (*tx)(struct spi_imx_data *);
101 void (*rx)(struct spi_imx_data *);
102 void *rx_buf;
103 const void *tx_buf;
104 unsigned int txfifo; /* number of words pushed in tx FIFO */
105 unsigned int dynamic_burst;
106
107 /* Slave mode */
108 bool slave_mode;
109 bool slave_aborted;
110 unsigned int slave_burst;
111
112 /* DMA */
113 bool usedma;
114 u32 wml;
115 struct completion dma_rx_completion;
116 struct completion dma_tx_completion;
117
118 const struct spi_imx_devtype_data *devtype_data;
119 };
120
is_imx27_cspi(struct spi_imx_data * d)121 static inline int is_imx27_cspi(struct spi_imx_data *d)
122 {
123 return d->devtype_data->devtype == IMX27_CSPI;
124 }
125
is_imx35_cspi(struct spi_imx_data * d)126 static inline int is_imx35_cspi(struct spi_imx_data *d)
127 {
128 return d->devtype_data->devtype == IMX35_CSPI;
129 }
130
is_imx51_ecspi(struct spi_imx_data * d)131 static inline int is_imx51_ecspi(struct spi_imx_data *d)
132 {
133 return d->devtype_data->devtype == IMX51_ECSPI;
134 }
135
is_imx53_ecspi(struct spi_imx_data * d)136 static inline int is_imx53_ecspi(struct spi_imx_data *d)
137 {
138 return d->devtype_data->devtype == IMX53_ECSPI;
139 }
140
141 #define MXC_SPI_BUF_RX(type) \
142 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
143 { \
144 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
145 \
146 if (spi_imx->rx_buf) { \
147 *(type *)spi_imx->rx_buf = val; \
148 spi_imx->rx_buf += sizeof(type); \
149 } \
150 \
151 spi_imx->remainder -= sizeof(type); \
152 }
153
154 #define MXC_SPI_BUF_TX(type) \
155 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
156 { \
157 type val = 0; \
158 \
159 if (spi_imx->tx_buf) { \
160 val = *(type *)spi_imx->tx_buf; \
161 spi_imx->tx_buf += sizeof(type); \
162 } \
163 \
164 spi_imx->count -= sizeof(type); \
165 \
166 writel(val, spi_imx->base + MXC_CSPITXDATA); \
167 }
168
169 MXC_SPI_BUF_RX(u8)
170 MXC_SPI_BUF_TX(u8)
171 MXC_SPI_BUF_RX(u16)
172 MXC_SPI_BUF_TX(u16)
173 MXC_SPI_BUF_RX(u32)
174 MXC_SPI_BUF_TX(u32)
175
176 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
177 * (which is currently not the case in this driver)
178 */
179 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
180 256, 384, 512, 768, 1024};
181
182 /* MX21, MX27 */
spi_imx_clkdiv_1(unsigned int fin,unsigned int fspi,unsigned int max,unsigned int * fres)183 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
184 unsigned int fspi, unsigned int max, unsigned int *fres)
185 {
186 int i;
187
188 for (i = 2; i < max; i++)
189 if (fspi * mxc_clkdivs[i] >= fin)
190 break;
191
192 *fres = fin / mxc_clkdivs[i];
193 return i;
194 }
195
196 /* MX1, MX31, MX35, MX51 CSPI */
spi_imx_clkdiv_2(unsigned int fin,unsigned int fspi,unsigned int * fres)197 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
198 unsigned int fspi, unsigned int *fres)
199 {
200 int i, div = 4;
201
202 for (i = 0; i < 7; i++) {
203 if (fspi * div >= fin)
204 goto out;
205 div <<= 1;
206 }
207
208 out:
209 *fres = fin / div;
210 return i;
211 }
212
spi_imx_bytes_per_word(const int bits_per_word)213 static int spi_imx_bytes_per_word(const int bits_per_word)
214 {
215 if (bits_per_word <= 8)
216 return 1;
217 else if (bits_per_word <= 16)
218 return 2;
219 else
220 return 4;
221 }
222
spi_imx_can_dma(struct spi_master * master,struct spi_device * spi,struct spi_transfer * transfer)223 static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
224 struct spi_transfer *transfer)
225 {
226 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
227
228 if (!use_dma || master->fallback)
229 return false;
230
231 if (!master->dma_rx)
232 return false;
233
234 if (spi_imx->slave_mode)
235 return false;
236
237 if (transfer->len < spi_imx->devtype_data->fifo_size)
238 return false;
239
240 spi_imx->dynamic_burst = 0;
241
242 return true;
243 }
244
245 #define MX51_ECSPI_CTRL 0x08
246 #define MX51_ECSPI_CTRL_ENABLE (1 << 0)
247 #define MX51_ECSPI_CTRL_XCH (1 << 2)
248 #define MX51_ECSPI_CTRL_SMC (1 << 3)
249 #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
250 #define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16)
251 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
252 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
253 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
254 #define MX51_ECSPI_CTRL_BL_OFFSET 20
255 #define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20)
256
257 #define MX51_ECSPI_CONFIG 0x0c
258 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
259 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
260 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
261 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
262 #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
263
264 #define MX51_ECSPI_INT 0x10
265 #define MX51_ECSPI_INT_TEEN (1 << 0)
266 #define MX51_ECSPI_INT_RREN (1 << 3)
267 #define MX51_ECSPI_INT_RDREN (1 << 4)
268
269 #define MX51_ECSPI_DMA 0x14
270 #define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f)
271 #define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16)
272 #define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24)
273
274 #define MX51_ECSPI_DMA_TEDEN (1 << 7)
275 #define MX51_ECSPI_DMA_RXDEN (1 << 23)
276 #define MX51_ECSPI_DMA_RXTDEN (1 << 31)
277
278 #define MX51_ECSPI_STAT 0x18
279 #define MX51_ECSPI_STAT_RR (1 << 3)
280
281 #define MX51_ECSPI_TESTREG 0x20
282 #define MX51_ECSPI_TESTREG_LBC BIT(31)
283
spi_imx_buf_rx_swap_u32(struct spi_imx_data * spi_imx)284 static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx)
285 {
286 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
287 #ifdef __LITTLE_ENDIAN
288 unsigned int bytes_per_word;
289 #endif
290
291 if (spi_imx->rx_buf) {
292 #ifdef __LITTLE_ENDIAN
293 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
294 if (bytes_per_word == 1)
295 val = cpu_to_be32(val);
296 else if (bytes_per_word == 2)
297 val = (val << 16) | (val >> 16);
298 #endif
299 *(u32 *)spi_imx->rx_buf = val;
300 spi_imx->rx_buf += sizeof(u32);
301 }
302
303 spi_imx->remainder -= sizeof(u32);
304 }
305
spi_imx_buf_rx_swap(struct spi_imx_data * spi_imx)306 static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
307 {
308 int unaligned;
309 u32 val;
310
311 unaligned = spi_imx->remainder % 4;
312
313 if (!unaligned) {
314 spi_imx_buf_rx_swap_u32(spi_imx);
315 return;
316 }
317
318 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
319 spi_imx_buf_rx_u16(spi_imx);
320 return;
321 }
322
323 val = readl(spi_imx->base + MXC_CSPIRXDATA);
324
325 while (unaligned--) {
326 if (spi_imx->rx_buf) {
327 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff;
328 spi_imx->rx_buf++;
329 }
330 spi_imx->remainder--;
331 }
332 }
333
spi_imx_buf_tx_swap_u32(struct spi_imx_data * spi_imx)334 static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx)
335 {
336 u32 val = 0;
337 #ifdef __LITTLE_ENDIAN
338 unsigned int bytes_per_word;
339 #endif
340
341 if (spi_imx->tx_buf) {
342 val = *(u32 *)spi_imx->tx_buf;
343 spi_imx->tx_buf += sizeof(u32);
344 }
345
346 spi_imx->count -= sizeof(u32);
347 #ifdef __LITTLE_ENDIAN
348 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
349
350 if (bytes_per_word == 1)
351 val = cpu_to_be32(val);
352 else if (bytes_per_word == 2)
353 val = (val << 16) | (val >> 16);
354 #endif
355 writel(val, spi_imx->base + MXC_CSPITXDATA);
356 }
357
spi_imx_buf_tx_swap(struct spi_imx_data * spi_imx)358 static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
359 {
360 int unaligned;
361 u32 val = 0;
362
363 unaligned = spi_imx->count % 4;
364
365 if (!unaligned) {
366 spi_imx_buf_tx_swap_u32(spi_imx);
367 return;
368 }
369
370 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
371 spi_imx_buf_tx_u16(spi_imx);
372 return;
373 }
374
375 while (unaligned--) {
376 if (spi_imx->tx_buf) {
377 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned);
378 spi_imx->tx_buf++;
379 }
380 spi_imx->count--;
381 }
382
383 writel(val, spi_imx->base + MXC_CSPITXDATA);
384 }
385
mx53_ecspi_rx_slave(struct spi_imx_data * spi_imx)386 static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx)
387 {
388 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA));
389
390 if (spi_imx->rx_buf) {
391 int n_bytes = spi_imx->slave_burst % sizeof(val);
392
393 if (!n_bytes)
394 n_bytes = sizeof(val);
395
396 memcpy(spi_imx->rx_buf,
397 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes);
398
399 spi_imx->rx_buf += n_bytes;
400 spi_imx->slave_burst -= n_bytes;
401 }
402
403 spi_imx->remainder -= sizeof(u32);
404 }
405
mx53_ecspi_tx_slave(struct spi_imx_data * spi_imx)406 static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx)
407 {
408 u32 val = 0;
409 int n_bytes = spi_imx->count % sizeof(val);
410
411 if (!n_bytes)
412 n_bytes = sizeof(val);
413
414 if (spi_imx->tx_buf) {
415 memcpy(((u8 *)&val) + sizeof(val) - n_bytes,
416 spi_imx->tx_buf, n_bytes);
417 val = cpu_to_be32(val);
418 spi_imx->tx_buf += n_bytes;
419 }
420
421 spi_imx->count -= n_bytes;
422
423 writel(val, spi_imx->base + MXC_CSPITXDATA);
424 }
425
426 /* MX51 eCSPI */
mx51_ecspi_clkdiv(struct spi_imx_data * spi_imx,unsigned int fspi,unsigned int * fres)427 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
428 unsigned int fspi, unsigned int *fres)
429 {
430 /*
431 * there are two 4-bit dividers, the pre-divider divides by
432 * $pre, the post-divider by 2^$post
433 */
434 unsigned int pre, post;
435 unsigned int fin = spi_imx->spi_clk;
436
437 fspi = min(fspi, fin);
438
439 post = fls(fin) - fls(fspi);
440 if (fin > fspi << post)
441 post++;
442
443 /* now we have: (fin <= fspi << post) with post being minimal */
444
445 post = max(4U, post) - 4;
446 if (unlikely(post > 0xf)) {
447 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
448 fspi, fin);
449 return 0xff;
450 }
451
452 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
453
454 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
455 __func__, fin, fspi, post, pre);
456
457 /* Resulting frequency for the SCLK line. */
458 *fres = (fin / (pre + 1)) >> post;
459
460 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
461 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
462 }
463
mx51_ecspi_intctrl(struct spi_imx_data * spi_imx,int enable)464 static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
465 {
466 unsigned val = 0;
467
468 if (enable & MXC_INT_TE)
469 val |= MX51_ECSPI_INT_TEEN;
470
471 if (enable & MXC_INT_RR)
472 val |= MX51_ECSPI_INT_RREN;
473
474 if (enable & MXC_INT_RDR)
475 val |= MX51_ECSPI_INT_RDREN;
476
477 writel(val, spi_imx->base + MX51_ECSPI_INT);
478 }
479
mx51_ecspi_trigger(struct spi_imx_data * spi_imx)480 static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
481 {
482 u32 reg;
483
484 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
485 reg |= MX51_ECSPI_CTRL_XCH;
486 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
487 }
488
mx51_disable_dma(struct spi_imx_data * spi_imx)489 static void mx51_disable_dma(struct spi_imx_data *spi_imx)
490 {
491 writel(0, spi_imx->base + MX51_ECSPI_DMA);
492 }
493
mx51_ecspi_disable(struct spi_imx_data * spi_imx)494 static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
495 {
496 u32 ctrl;
497
498 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
499 ctrl &= ~MX51_ECSPI_CTRL_ENABLE;
500 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
501 }
502
mx51_ecspi_prepare_message(struct spi_imx_data * spi_imx,struct spi_message * msg)503 static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
504 struct spi_message *msg)
505 {
506 struct spi_device *spi = msg->spi;
507 struct spi_transfer *xfer;
508 u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
509 u32 min_speed_hz = ~0U;
510 u32 testreg, delay;
511 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
512
513 /* set Master or Slave mode */
514 if (spi_imx->slave_mode)
515 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK;
516 else
517 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
518
519 /*
520 * Enable SPI_RDY handling (falling edge/level triggered).
521 */
522 if (spi->mode & SPI_READY)
523 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
524
525 /* set chip select to use */
526 ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
527
528 /*
529 * The ctrl register must be written first, with the EN bit set other
530 * registers must not be written to.
531 */
532 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
533
534 testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
535 if (spi->mode & SPI_LOOP)
536 testreg |= MX51_ECSPI_TESTREG_LBC;
537 else
538 testreg &= ~MX51_ECSPI_TESTREG_LBC;
539 writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG);
540
541 /*
542 * eCSPI burst completion by Chip Select signal in Slave mode
543 * is not functional for imx53 Soc, config SPI burst completed when
544 * BURST_LENGTH + 1 bits are received
545 */
546 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
547 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
548 else
549 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
550
551 if (spi->mode & SPI_CPHA)
552 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
553 else
554 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
555
556 if (spi->mode & SPI_CPOL) {
557 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
558 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
559 } else {
560 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
561 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
562 }
563
564 if (spi->mode & SPI_CS_HIGH)
565 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
566 else
567 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
568
569 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
570
571 /*
572 * Wait until the changes in the configuration register CONFIGREG
573 * propagate into the hardware. It takes exactly one tick of the
574 * SCLK clock, but we will wait two SCLK clock just to be sure. The
575 * effect of the delay it takes for the hardware to apply changes
576 * is noticable if the SCLK clock run very slow. In such a case, if
577 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
578 * be asserted before the SCLK polarity changes, which would disrupt
579 * the SPI communication as the device on the other end would consider
580 * the change of SCLK polarity as a clock tick already.
581 *
582 * Because spi_imx->spi_bus_clk is only set in bitbang prepare_message
583 * callback, iterate over all the transfers in spi_message, find the
584 * one with lowest bus frequency, and use that bus frequency for the
585 * delay calculation. In case all transfers have speed_hz == 0, then
586 * min_speed_hz is ~0 and the resulting delay is zero.
587 */
588 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
589 if (!xfer->speed_hz)
590 continue;
591 min_speed_hz = min(xfer->speed_hz, min_speed_hz);
592 }
593
594 delay = (2 * 1000000) / min_speed_hz;
595 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
596 udelay(delay);
597 else /* SCLK is _very_ slow */
598 usleep_range(delay, delay + 10);
599
600 return 0;
601 }
602
mx51_ecspi_prepare_transfer(struct spi_imx_data * spi_imx,struct spi_device * spi)603 static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
604 struct spi_device *spi)
605 {
606 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
607 u32 clk;
608
609 /* Clear BL field and set the right value */
610 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
611 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
612 ctrl |= (spi_imx->slave_burst * 8 - 1)
613 << MX51_ECSPI_CTRL_BL_OFFSET;
614 else
615 ctrl |= (spi_imx->bits_per_word - 1)
616 << MX51_ECSPI_CTRL_BL_OFFSET;
617
618 /* set clock speed */
619 ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET |
620 0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET);
621 ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk);
622 spi_imx->spi_bus_clk = clk;
623
624 if (spi_imx->usedma)
625 ctrl |= MX51_ECSPI_CTRL_SMC;
626
627 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
628
629 return 0;
630 }
631
mx51_setup_wml(struct spi_imx_data * spi_imx)632 static void mx51_setup_wml(struct spi_imx_data *spi_imx)
633 {
634 /*
635 * Configure the DMA register: setup the watermark
636 * and enable DMA request.
637 */
638 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
639 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
640 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
641 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
642 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
643 }
644
mx51_ecspi_rx_available(struct spi_imx_data * spi_imx)645 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
646 {
647 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
648 }
649
mx51_ecspi_reset(struct spi_imx_data * spi_imx)650 static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
651 {
652 /* drain receive buffer */
653 while (mx51_ecspi_rx_available(spi_imx))
654 readl(spi_imx->base + MXC_CSPIRXDATA);
655 }
656
657 #define MX31_INTREG_TEEN (1 << 0)
658 #define MX31_INTREG_RREN (1 << 3)
659
660 #define MX31_CSPICTRL_ENABLE (1 << 0)
661 #define MX31_CSPICTRL_MASTER (1 << 1)
662 #define MX31_CSPICTRL_XCH (1 << 2)
663 #define MX31_CSPICTRL_SMC (1 << 3)
664 #define MX31_CSPICTRL_POL (1 << 4)
665 #define MX31_CSPICTRL_PHA (1 << 5)
666 #define MX31_CSPICTRL_SSCTL (1 << 6)
667 #define MX31_CSPICTRL_SSPOL (1 << 7)
668 #define MX31_CSPICTRL_BC_SHIFT 8
669 #define MX35_CSPICTRL_BL_SHIFT 20
670 #define MX31_CSPICTRL_CS_SHIFT 24
671 #define MX35_CSPICTRL_CS_SHIFT 12
672 #define MX31_CSPICTRL_DR_SHIFT 16
673
674 #define MX31_CSPI_DMAREG 0x10
675 #define MX31_DMAREG_RH_DEN (1<<4)
676 #define MX31_DMAREG_TH_DEN (1<<1)
677
678 #define MX31_CSPISTATUS 0x14
679 #define MX31_STATUS_RR (1 << 3)
680
681 #define MX31_CSPI_TESTREG 0x1C
682 #define MX31_TEST_LBC (1 << 14)
683
684 /* These functions also work for the i.MX35, but be aware that
685 * the i.MX35 has a slightly different register layout for bits
686 * we do not use here.
687 */
mx31_intctrl(struct spi_imx_data * spi_imx,int enable)688 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
689 {
690 unsigned int val = 0;
691
692 if (enable & MXC_INT_TE)
693 val |= MX31_INTREG_TEEN;
694 if (enable & MXC_INT_RR)
695 val |= MX31_INTREG_RREN;
696
697 writel(val, spi_imx->base + MXC_CSPIINT);
698 }
699
mx31_trigger(struct spi_imx_data * spi_imx)700 static void mx31_trigger(struct spi_imx_data *spi_imx)
701 {
702 unsigned int reg;
703
704 reg = readl(spi_imx->base + MXC_CSPICTRL);
705 reg |= MX31_CSPICTRL_XCH;
706 writel(reg, spi_imx->base + MXC_CSPICTRL);
707 }
708
mx31_prepare_message(struct spi_imx_data * spi_imx,struct spi_message * msg)709 static int mx31_prepare_message(struct spi_imx_data *spi_imx,
710 struct spi_message *msg)
711 {
712 return 0;
713 }
714
mx31_prepare_transfer(struct spi_imx_data * spi_imx,struct spi_device * spi)715 static int mx31_prepare_transfer(struct spi_imx_data *spi_imx,
716 struct spi_device *spi)
717 {
718 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
719 unsigned int clk;
720
721 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
722 MX31_CSPICTRL_DR_SHIFT;
723 spi_imx->spi_bus_clk = clk;
724
725 if (is_imx35_cspi(spi_imx)) {
726 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT;
727 reg |= MX31_CSPICTRL_SSCTL;
728 } else {
729 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT;
730 }
731
732 if (spi->mode & SPI_CPHA)
733 reg |= MX31_CSPICTRL_PHA;
734 if (spi->mode & SPI_CPOL)
735 reg |= MX31_CSPICTRL_POL;
736 if (spi->mode & SPI_CS_HIGH)
737 reg |= MX31_CSPICTRL_SSPOL;
738 if (!spi->cs_gpiod)
739 reg |= (spi->chip_select) <<
740 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
741 MX31_CSPICTRL_CS_SHIFT);
742
743 if (spi_imx->usedma)
744 reg |= MX31_CSPICTRL_SMC;
745
746 writel(reg, spi_imx->base + MXC_CSPICTRL);
747
748 reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
749 if (spi->mode & SPI_LOOP)
750 reg |= MX31_TEST_LBC;
751 else
752 reg &= ~MX31_TEST_LBC;
753 writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
754
755 if (spi_imx->usedma) {
756 /*
757 * configure DMA requests when RXFIFO is half full and
758 * when TXFIFO is half empty
759 */
760 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
761 spi_imx->base + MX31_CSPI_DMAREG);
762 }
763
764 return 0;
765 }
766
mx31_rx_available(struct spi_imx_data * spi_imx)767 static int mx31_rx_available(struct spi_imx_data *spi_imx)
768 {
769 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
770 }
771
mx31_reset(struct spi_imx_data * spi_imx)772 static void mx31_reset(struct spi_imx_data *spi_imx)
773 {
774 /* drain receive buffer */
775 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
776 readl(spi_imx->base + MXC_CSPIRXDATA);
777 }
778
779 #define MX21_INTREG_RR (1 << 4)
780 #define MX21_INTREG_TEEN (1 << 9)
781 #define MX21_INTREG_RREN (1 << 13)
782
783 #define MX21_CSPICTRL_POL (1 << 5)
784 #define MX21_CSPICTRL_PHA (1 << 6)
785 #define MX21_CSPICTRL_SSPOL (1 << 8)
786 #define MX21_CSPICTRL_XCH (1 << 9)
787 #define MX21_CSPICTRL_ENABLE (1 << 10)
788 #define MX21_CSPICTRL_MASTER (1 << 11)
789 #define MX21_CSPICTRL_DR_SHIFT 14
790 #define MX21_CSPICTRL_CS_SHIFT 19
791
mx21_intctrl(struct spi_imx_data * spi_imx,int enable)792 static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
793 {
794 unsigned int val = 0;
795
796 if (enable & MXC_INT_TE)
797 val |= MX21_INTREG_TEEN;
798 if (enable & MXC_INT_RR)
799 val |= MX21_INTREG_RREN;
800
801 writel(val, spi_imx->base + MXC_CSPIINT);
802 }
803
mx21_trigger(struct spi_imx_data * spi_imx)804 static void mx21_trigger(struct spi_imx_data *spi_imx)
805 {
806 unsigned int reg;
807
808 reg = readl(spi_imx->base + MXC_CSPICTRL);
809 reg |= MX21_CSPICTRL_XCH;
810 writel(reg, spi_imx->base + MXC_CSPICTRL);
811 }
812
mx21_prepare_message(struct spi_imx_data * spi_imx,struct spi_message * msg)813 static int mx21_prepare_message(struct spi_imx_data *spi_imx,
814 struct spi_message *msg)
815 {
816 return 0;
817 }
818
mx21_prepare_transfer(struct spi_imx_data * spi_imx,struct spi_device * spi)819 static int mx21_prepare_transfer(struct spi_imx_data *spi_imx,
820 struct spi_device *spi)
821 {
822 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
823 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
824 unsigned int clk;
825
826 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk)
827 << MX21_CSPICTRL_DR_SHIFT;
828 spi_imx->spi_bus_clk = clk;
829
830 reg |= spi_imx->bits_per_word - 1;
831
832 if (spi->mode & SPI_CPHA)
833 reg |= MX21_CSPICTRL_PHA;
834 if (spi->mode & SPI_CPOL)
835 reg |= MX21_CSPICTRL_POL;
836 if (spi->mode & SPI_CS_HIGH)
837 reg |= MX21_CSPICTRL_SSPOL;
838 if (!spi->cs_gpiod)
839 reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT;
840
841 writel(reg, spi_imx->base + MXC_CSPICTRL);
842
843 return 0;
844 }
845
mx21_rx_available(struct spi_imx_data * spi_imx)846 static int mx21_rx_available(struct spi_imx_data *spi_imx)
847 {
848 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
849 }
850
mx21_reset(struct spi_imx_data * spi_imx)851 static void mx21_reset(struct spi_imx_data *spi_imx)
852 {
853 writel(1, spi_imx->base + MXC_RESET);
854 }
855
856 #define MX1_INTREG_RR (1 << 3)
857 #define MX1_INTREG_TEEN (1 << 8)
858 #define MX1_INTREG_RREN (1 << 11)
859
860 #define MX1_CSPICTRL_POL (1 << 4)
861 #define MX1_CSPICTRL_PHA (1 << 5)
862 #define MX1_CSPICTRL_XCH (1 << 8)
863 #define MX1_CSPICTRL_ENABLE (1 << 9)
864 #define MX1_CSPICTRL_MASTER (1 << 10)
865 #define MX1_CSPICTRL_DR_SHIFT 13
866
mx1_intctrl(struct spi_imx_data * spi_imx,int enable)867 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
868 {
869 unsigned int val = 0;
870
871 if (enable & MXC_INT_TE)
872 val |= MX1_INTREG_TEEN;
873 if (enable & MXC_INT_RR)
874 val |= MX1_INTREG_RREN;
875
876 writel(val, spi_imx->base + MXC_CSPIINT);
877 }
878
mx1_trigger(struct spi_imx_data * spi_imx)879 static void mx1_trigger(struct spi_imx_data *spi_imx)
880 {
881 unsigned int reg;
882
883 reg = readl(spi_imx->base + MXC_CSPICTRL);
884 reg |= MX1_CSPICTRL_XCH;
885 writel(reg, spi_imx->base + MXC_CSPICTRL);
886 }
887
mx1_prepare_message(struct spi_imx_data * spi_imx,struct spi_message * msg)888 static int mx1_prepare_message(struct spi_imx_data *spi_imx,
889 struct spi_message *msg)
890 {
891 return 0;
892 }
893
mx1_prepare_transfer(struct spi_imx_data * spi_imx,struct spi_device * spi)894 static int mx1_prepare_transfer(struct spi_imx_data *spi_imx,
895 struct spi_device *spi)
896 {
897 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
898 unsigned int clk;
899
900 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
901 MX1_CSPICTRL_DR_SHIFT;
902 spi_imx->spi_bus_clk = clk;
903
904 reg |= spi_imx->bits_per_word - 1;
905
906 if (spi->mode & SPI_CPHA)
907 reg |= MX1_CSPICTRL_PHA;
908 if (spi->mode & SPI_CPOL)
909 reg |= MX1_CSPICTRL_POL;
910
911 writel(reg, spi_imx->base + MXC_CSPICTRL);
912
913 return 0;
914 }
915
mx1_rx_available(struct spi_imx_data * spi_imx)916 static int mx1_rx_available(struct spi_imx_data *spi_imx)
917 {
918 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
919 }
920
mx1_reset(struct spi_imx_data * spi_imx)921 static void mx1_reset(struct spi_imx_data *spi_imx)
922 {
923 writel(1, spi_imx->base + MXC_RESET);
924 }
925
926 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
927 .intctrl = mx1_intctrl,
928 .prepare_message = mx1_prepare_message,
929 .prepare_transfer = mx1_prepare_transfer,
930 .trigger = mx1_trigger,
931 .rx_available = mx1_rx_available,
932 .reset = mx1_reset,
933 .fifo_size = 8,
934 .has_dmamode = false,
935 .dynamic_burst = false,
936 .has_slavemode = false,
937 .devtype = IMX1_CSPI,
938 };
939
940 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
941 .intctrl = mx21_intctrl,
942 .prepare_message = mx21_prepare_message,
943 .prepare_transfer = mx21_prepare_transfer,
944 .trigger = mx21_trigger,
945 .rx_available = mx21_rx_available,
946 .reset = mx21_reset,
947 .fifo_size = 8,
948 .has_dmamode = false,
949 .dynamic_burst = false,
950 .has_slavemode = false,
951 .devtype = IMX21_CSPI,
952 };
953
954 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
955 /* i.mx27 cspi shares the functions with i.mx21 one */
956 .intctrl = mx21_intctrl,
957 .prepare_message = mx21_prepare_message,
958 .prepare_transfer = mx21_prepare_transfer,
959 .trigger = mx21_trigger,
960 .rx_available = mx21_rx_available,
961 .reset = mx21_reset,
962 .fifo_size = 8,
963 .has_dmamode = false,
964 .dynamic_burst = false,
965 .has_slavemode = false,
966 .devtype = IMX27_CSPI,
967 };
968
969 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
970 .intctrl = mx31_intctrl,
971 .prepare_message = mx31_prepare_message,
972 .prepare_transfer = mx31_prepare_transfer,
973 .trigger = mx31_trigger,
974 .rx_available = mx31_rx_available,
975 .reset = mx31_reset,
976 .fifo_size = 8,
977 .has_dmamode = false,
978 .dynamic_burst = false,
979 .has_slavemode = false,
980 .devtype = IMX31_CSPI,
981 };
982
983 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
984 /* i.mx35 and later cspi shares the functions with i.mx31 one */
985 .intctrl = mx31_intctrl,
986 .prepare_message = mx31_prepare_message,
987 .prepare_transfer = mx31_prepare_transfer,
988 .trigger = mx31_trigger,
989 .rx_available = mx31_rx_available,
990 .reset = mx31_reset,
991 .fifo_size = 8,
992 .has_dmamode = true,
993 .dynamic_burst = false,
994 .has_slavemode = false,
995 .devtype = IMX35_CSPI,
996 };
997
998 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
999 .intctrl = mx51_ecspi_intctrl,
1000 .prepare_message = mx51_ecspi_prepare_message,
1001 .prepare_transfer = mx51_ecspi_prepare_transfer,
1002 .trigger = mx51_ecspi_trigger,
1003 .rx_available = mx51_ecspi_rx_available,
1004 .reset = mx51_ecspi_reset,
1005 .setup_wml = mx51_setup_wml,
1006 .disable_dma = mx51_disable_dma,
1007 .fifo_size = 64,
1008 .has_dmamode = true,
1009 .dynamic_burst = true,
1010 .has_slavemode = true,
1011 .disable = mx51_ecspi_disable,
1012 .devtype = IMX51_ECSPI,
1013 };
1014
1015 static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
1016 .intctrl = mx51_ecspi_intctrl,
1017 .prepare_message = mx51_ecspi_prepare_message,
1018 .prepare_transfer = mx51_ecspi_prepare_transfer,
1019 .trigger = mx51_ecspi_trigger,
1020 .rx_available = mx51_ecspi_rx_available,
1021 .disable_dma = mx51_disable_dma,
1022 .reset = mx51_ecspi_reset,
1023 .fifo_size = 64,
1024 .has_dmamode = true,
1025 .has_slavemode = true,
1026 .disable = mx51_ecspi_disable,
1027 .devtype = IMX53_ECSPI,
1028 };
1029
1030 static const struct platform_device_id spi_imx_devtype[] = {
1031 {
1032 .name = "imx1-cspi",
1033 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
1034 }, {
1035 .name = "imx21-cspi",
1036 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
1037 }, {
1038 .name = "imx27-cspi",
1039 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
1040 }, {
1041 .name = "imx31-cspi",
1042 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
1043 }, {
1044 .name = "imx35-cspi",
1045 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
1046 }, {
1047 .name = "imx51-ecspi",
1048 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
1049 }, {
1050 .name = "imx53-ecspi",
1051 .driver_data = (kernel_ulong_t) &imx53_ecspi_devtype_data,
1052 }, {
1053 /* sentinel */
1054 }
1055 };
1056
1057 static const struct of_device_id spi_imx_dt_ids[] = {
1058 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
1059 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
1060 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
1061 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
1062 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
1063 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
1064 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
1065 { /* sentinel */ }
1066 };
1067 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
1068
spi_imx_set_burst_len(struct spi_imx_data * spi_imx,int n_bits)1069 static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits)
1070 {
1071 u32 ctrl;
1072
1073 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
1074 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
1075 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET);
1076 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
1077 }
1078
spi_imx_push(struct spi_imx_data * spi_imx)1079 static void spi_imx_push(struct spi_imx_data *spi_imx)
1080 {
1081 unsigned int burst_len, fifo_words;
1082
1083 if (spi_imx->dynamic_burst)
1084 fifo_words = 4;
1085 else
1086 fifo_words = spi_imx_bytes_per_word(spi_imx->bits_per_word);
1087 /*
1088 * Reload the FIFO when the remaining bytes to be transferred in the
1089 * current burst is 0. This only applies when bits_per_word is a
1090 * multiple of 8.
1091 */
1092 if (!spi_imx->remainder) {
1093 if (spi_imx->dynamic_burst) {
1094
1095 /* We need to deal unaligned data first */
1096 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST;
1097
1098 if (!burst_len)
1099 burst_len = MX51_ECSPI_CTRL_MAX_BURST;
1100
1101 spi_imx_set_burst_len(spi_imx, burst_len * 8);
1102
1103 spi_imx->remainder = burst_len;
1104 } else {
1105 spi_imx->remainder = fifo_words;
1106 }
1107 }
1108
1109 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) {
1110 if (!spi_imx->count)
1111 break;
1112 if (spi_imx->dynamic_burst &&
1113 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder,
1114 fifo_words))
1115 break;
1116 spi_imx->tx(spi_imx);
1117 spi_imx->txfifo++;
1118 }
1119
1120 if (!spi_imx->slave_mode)
1121 spi_imx->devtype_data->trigger(spi_imx);
1122 }
1123
spi_imx_isr(int irq,void * dev_id)1124 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
1125 {
1126 struct spi_imx_data *spi_imx = dev_id;
1127
1128 while (spi_imx->txfifo &&
1129 spi_imx->devtype_data->rx_available(spi_imx)) {
1130 spi_imx->rx(spi_imx);
1131 spi_imx->txfifo--;
1132 }
1133
1134 if (spi_imx->count) {
1135 spi_imx_push(spi_imx);
1136 return IRQ_HANDLED;
1137 }
1138
1139 if (spi_imx->txfifo) {
1140 /* No data left to push, but still waiting for rx data,
1141 * enable receive data available interrupt.
1142 */
1143 spi_imx->devtype_data->intctrl(
1144 spi_imx, MXC_INT_RR);
1145 return IRQ_HANDLED;
1146 }
1147
1148 spi_imx->devtype_data->intctrl(spi_imx, 0);
1149 complete(&spi_imx->xfer_done);
1150
1151 return IRQ_HANDLED;
1152 }
1153
spi_imx_dma_configure(struct spi_master * master)1154 static int spi_imx_dma_configure(struct spi_master *master)
1155 {
1156 int ret;
1157 enum dma_slave_buswidth buswidth;
1158 struct dma_slave_config rx = {}, tx = {};
1159 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1160
1161 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) {
1162 case 4:
1163 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1164 break;
1165 case 2:
1166 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1167 break;
1168 case 1:
1169 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1170 break;
1171 default:
1172 return -EINVAL;
1173 }
1174
1175 tx.direction = DMA_MEM_TO_DEV;
1176 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
1177 tx.dst_addr_width = buswidth;
1178 tx.dst_maxburst = spi_imx->wml;
1179 ret = dmaengine_slave_config(master->dma_tx, &tx);
1180 if (ret) {
1181 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
1182 return ret;
1183 }
1184
1185 rx.direction = DMA_DEV_TO_MEM;
1186 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
1187 rx.src_addr_width = buswidth;
1188 rx.src_maxburst = spi_imx->wml;
1189 ret = dmaengine_slave_config(master->dma_rx, &rx);
1190 if (ret) {
1191 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
1192 return ret;
1193 }
1194
1195 return 0;
1196 }
1197
spi_imx_setupxfer(struct spi_device * spi,struct spi_transfer * t)1198 static int spi_imx_setupxfer(struct spi_device *spi,
1199 struct spi_transfer *t)
1200 {
1201 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1202
1203 if (!t)
1204 return 0;
1205
1206 if (!t->speed_hz) {
1207 if (!spi->max_speed_hz) {
1208 dev_err(&spi->dev, "no speed_hz provided!\n");
1209 return -EINVAL;
1210 }
1211 dev_dbg(&spi->dev, "using spi->max_speed_hz!\n");
1212 spi_imx->spi_bus_clk = spi->max_speed_hz;
1213 } else
1214 spi_imx->spi_bus_clk = t->speed_hz;
1215
1216 spi_imx->bits_per_word = t->bits_per_word;
1217
1218 /*
1219 * Initialize the functions for transfer. To transfer non byte-aligned
1220 * words, we have to use multiple word-size bursts, we can't use
1221 * dynamic_burst in that case.
1222 */
1223 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode &&
1224 (spi_imx->bits_per_word == 8 ||
1225 spi_imx->bits_per_word == 16 ||
1226 spi_imx->bits_per_word == 32)) {
1227
1228 spi_imx->rx = spi_imx_buf_rx_swap;
1229 spi_imx->tx = spi_imx_buf_tx_swap;
1230 spi_imx->dynamic_burst = 1;
1231
1232 } else {
1233 if (spi_imx->bits_per_word <= 8) {
1234 spi_imx->rx = spi_imx_buf_rx_u8;
1235 spi_imx->tx = spi_imx_buf_tx_u8;
1236 } else if (spi_imx->bits_per_word <= 16) {
1237 spi_imx->rx = spi_imx_buf_rx_u16;
1238 spi_imx->tx = spi_imx_buf_tx_u16;
1239 } else {
1240 spi_imx->rx = spi_imx_buf_rx_u32;
1241 spi_imx->tx = spi_imx_buf_tx_u32;
1242 }
1243 spi_imx->dynamic_burst = 0;
1244 }
1245
1246 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
1247 spi_imx->usedma = true;
1248 else
1249 spi_imx->usedma = false;
1250
1251 if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) {
1252 spi_imx->rx = mx53_ecspi_rx_slave;
1253 spi_imx->tx = mx53_ecspi_tx_slave;
1254 spi_imx->slave_burst = t->len;
1255 }
1256
1257 spi_imx->devtype_data->prepare_transfer(spi_imx, spi);
1258
1259 return 0;
1260 }
1261
spi_imx_sdma_exit(struct spi_imx_data * spi_imx)1262 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
1263 {
1264 struct spi_master *master = spi_imx->bitbang.master;
1265
1266 if (master->dma_rx) {
1267 dma_release_channel(master->dma_rx);
1268 master->dma_rx = NULL;
1269 }
1270
1271 if (master->dma_tx) {
1272 dma_release_channel(master->dma_tx);
1273 master->dma_tx = NULL;
1274 }
1275 }
1276
spi_imx_sdma_init(struct device * dev,struct spi_imx_data * spi_imx,struct spi_master * master)1277 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
1278 struct spi_master *master)
1279 {
1280 int ret;
1281
1282 /* use pio mode for i.mx6dl chip TKT238285 */
1283 if (of_machine_is_compatible("fsl,imx6dl"))
1284 return 0;
1285
1286 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
1287
1288 /* Prepare for TX DMA: */
1289 master->dma_tx = dma_request_chan(dev, "tx");
1290 if (IS_ERR(master->dma_tx)) {
1291 ret = PTR_ERR(master->dma_tx);
1292 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
1293 master->dma_tx = NULL;
1294 goto err;
1295 }
1296
1297 /* Prepare for RX : */
1298 master->dma_rx = dma_request_chan(dev, "rx");
1299 if (IS_ERR(master->dma_rx)) {
1300 ret = PTR_ERR(master->dma_rx);
1301 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
1302 master->dma_rx = NULL;
1303 goto err;
1304 }
1305
1306 init_completion(&spi_imx->dma_rx_completion);
1307 init_completion(&spi_imx->dma_tx_completion);
1308 master->can_dma = spi_imx_can_dma;
1309 master->max_dma_len = MAX_SDMA_BD_BYTES;
1310 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
1311 SPI_MASTER_MUST_TX;
1312
1313 return 0;
1314 err:
1315 spi_imx_sdma_exit(spi_imx);
1316 return ret;
1317 }
1318
spi_imx_dma_rx_callback(void * cookie)1319 static void spi_imx_dma_rx_callback(void *cookie)
1320 {
1321 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1322
1323 complete(&spi_imx->dma_rx_completion);
1324 }
1325
spi_imx_dma_tx_callback(void * cookie)1326 static void spi_imx_dma_tx_callback(void *cookie)
1327 {
1328 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1329
1330 complete(&spi_imx->dma_tx_completion);
1331 }
1332
spi_imx_calculate_timeout(struct spi_imx_data * spi_imx,int size)1333 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
1334 {
1335 unsigned long timeout = 0;
1336
1337 /* Time with actual data transfer and CS change delay related to HW */
1338 timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
1339
1340 /* Add extra second for scheduler related activities */
1341 timeout += 1;
1342
1343 /* Double calculated timeout */
1344 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
1345 }
1346
spi_imx_dma_transfer(struct spi_imx_data * spi_imx,struct spi_transfer * transfer)1347 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
1348 struct spi_transfer *transfer)
1349 {
1350 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
1351 unsigned long transfer_timeout;
1352 unsigned long timeout;
1353 struct spi_master *master = spi_imx->bitbang.master;
1354 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1355 struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents);
1356 unsigned int bytes_per_word, i;
1357 int ret;
1358
1359 /* Get the right burst length from the last sg to ensure no tail data */
1360 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
1361 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
1362 if (!(sg_dma_len(last_sg) % (i * bytes_per_word)))
1363 break;
1364 }
1365 /* Use 1 as wml in case no available burst length got */
1366 if (i == 0)
1367 i = 1;
1368
1369 spi_imx->wml = i;
1370
1371 ret = spi_imx_dma_configure(master);
1372 if (ret)
1373 goto dma_failure_no_start;
1374
1375 if (!spi_imx->devtype_data->setup_wml) {
1376 dev_err(spi_imx->dev, "No setup_wml()?\n");
1377 ret = -EINVAL;
1378 goto dma_failure_no_start;
1379 }
1380 spi_imx->devtype_data->setup_wml(spi_imx);
1381
1382 /*
1383 * The TX DMA setup starts the transfer, so make sure RX is configured
1384 * before TX.
1385 */
1386 desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
1387 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1388 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1389 if (!desc_rx) {
1390 ret = -EINVAL;
1391 goto dma_failure_no_start;
1392 }
1393
1394 desc_rx->callback = spi_imx_dma_rx_callback;
1395 desc_rx->callback_param = (void *)spi_imx;
1396 dmaengine_submit(desc_rx);
1397 reinit_completion(&spi_imx->dma_rx_completion);
1398 dma_async_issue_pending(master->dma_rx);
1399
1400 desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
1401 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1402 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1403 if (!desc_tx) {
1404 dmaengine_terminate_all(master->dma_tx);
1405 dmaengine_terminate_all(master->dma_rx);
1406 return -EINVAL;
1407 }
1408
1409 desc_tx->callback = spi_imx_dma_tx_callback;
1410 desc_tx->callback_param = (void *)spi_imx;
1411 dmaengine_submit(desc_tx);
1412 reinit_completion(&spi_imx->dma_tx_completion);
1413 dma_async_issue_pending(master->dma_tx);
1414
1415 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1416
1417 /* Wait SDMA to finish the data transfer.*/
1418 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1419 transfer_timeout);
1420 if (!timeout) {
1421 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1422 dmaengine_terminate_all(master->dma_tx);
1423 dmaengine_terminate_all(master->dma_rx);
1424 return -ETIMEDOUT;
1425 }
1426
1427 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1428 transfer_timeout);
1429 if (!timeout) {
1430 dev_err(&master->dev, "I/O Error in DMA RX\n");
1431 spi_imx->devtype_data->reset(spi_imx);
1432 dmaengine_terminate_all(master->dma_rx);
1433 return -ETIMEDOUT;
1434 }
1435
1436 return transfer->len;
1437 /* fallback to pio */
1438 dma_failure_no_start:
1439 transfer->error |= SPI_TRANS_FAIL_NO_START;
1440 return ret;
1441 }
1442
spi_imx_pio_transfer(struct spi_device * spi,struct spi_transfer * transfer)1443 static int spi_imx_pio_transfer(struct spi_device *spi,
1444 struct spi_transfer *transfer)
1445 {
1446 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1447 unsigned long transfer_timeout;
1448 unsigned long timeout;
1449
1450 spi_imx->tx_buf = transfer->tx_buf;
1451 spi_imx->rx_buf = transfer->rx_buf;
1452 spi_imx->count = transfer->len;
1453 spi_imx->txfifo = 0;
1454 spi_imx->remainder = 0;
1455
1456 reinit_completion(&spi_imx->xfer_done);
1457
1458 spi_imx_push(spi_imx);
1459
1460 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1461
1462 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1463
1464 timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
1465 transfer_timeout);
1466 if (!timeout) {
1467 dev_err(&spi->dev, "I/O Error in PIO\n");
1468 spi_imx->devtype_data->reset(spi_imx);
1469 return -ETIMEDOUT;
1470 }
1471
1472 return transfer->len;
1473 }
1474
spi_imx_pio_transfer_slave(struct spi_device * spi,struct spi_transfer * transfer)1475 static int spi_imx_pio_transfer_slave(struct spi_device *spi,
1476 struct spi_transfer *transfer)
1477 {
1478 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1479 int ret = transfer->len;
1480
1481 if (is_imx53_ecspi(spi_imx) &&
1482 transfer->len > MX53_MAX_TRANSFER_BYTES) {
1483 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n",
1484 MX53_MAX_TRANSFER_BYTES);
1485 return -EMSGSIZE;
1486 }
1487
1488 spi_imx->tx_buf = transfer->tx_buf;
1489 spi_imx->rx_buf = transfer->rx_buf;
1490 spi_imx->count = transfer->len;
1491 spi_imx->txfifo = 0;
1492 spi_imx->remainder = 0;
1493
1494 reinit_completion(&spi_imx->xfer_done);
1495 spi_imx->slave_aborted = false;
1496
1497 spi_imx_push(spi_imx);
1498
1499 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR);
1500
1501 if (wait_for_completion_interruptible(&spi_imx->xfer_done) ||
1502 spi_imx->slave_aborted) {
1503 dev_dbg(&spi->dev, "interrupted\n");
1504 ret = -EINTR;
1505 }
1506
1507 /* ecspi has a HW issue when works in Slave mode,
1508 * after 64 words writtern to TXFIFO, even TXFIFO becomes empty,
1509 * ECSPI_TXDATA keeps shift out the last word data,
1510 * so we have to disable ECSPI when in slave mode after the
1511 * transfer completes
1512 */
1513 if (spi_imx->devtype_data->disable)
1514 spi_imx->devtype_data->disable(spi_imx);
1515
1516 return ret;
1517 }
1518
spi_imx_transfer(struct spi_device * spi,struct spi_transfer * transfer)1519 static int spi_imx_transfer(struct spi_device *spi,
1520 struct spi_transfer *transfer)
1521 {
1522 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1523
1524 transfer->effective_speed_hz = spi_imx->spi_bus_clk;
1525
1526 /* flush rxfifo before transfer */
1527 while (spi_imx->devtype_data->rx_available(spi_imx))
1528 readl(spi_imx->base + MXC_CSPIRXDATA);
1529
1530 if (spi_imx->slave_mode)
1531 return spi_imx_pio_transfer_slave(spi, transfer);
1532
1533 if (spi_imx->usedma)
1534 return spi_imx_dma_transfer(spi_imx, transfer);
1535
1536 return spi_imx_pio_transfer(spi, transfer);
1537 }
1538
spi_imx_setup(struct spi_device * spi)1539 static int spi_imx_setup(struct spi_device *spi)
1540 {
1541 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1542 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1543
1544 return 0;
1545 }
1546
spi_imx_cleanup(struct spi_device * spi)1547 static void spi_imx_cleanup(struct spi_device *spi)
1548 {
1549 }
1550
1551 static int
spi_imx_prepare_message(struct spi_master * master,struct spi_message * msg)1552 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1553 {
1554 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1555 int ret;
1556
1557 ret = pm_runtime_get_sync(spi_imx->dev);
1558 if (ret < 0) {
1559 pm_runtime_put_noidle(spi_imx->dev);
1560 dev_err(spi_imx->dev, "failed to enable clock\n");
1561 return ret;
1562 }
1563
1564 ret = spi_imx->devtype_data->prepare_message(spi_imx, msg);
1565 if (ret) {
1566 pm_runtime_mark_last_busy(spi_imx->dev);
1567 pm_runtime_put_autosuspend(spi_imx->dev);
1568 }
1569
1570 return ret;
1571 }
1572
1573 static int
spi_imx_unprepare_message(struct spi_master * master,struct spi_message * msg)1574 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1575 {
1576 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1577
1578 pm_runtime_mark_last_busy(spi_imx->dev);
1579 pm_runtime_put_autosuspend(spi_imx->dev);
1580 return 0;
1581 }
1582
spi_imx_slave_abort(struct spi_master * master)1583 static int spi_imx_slave_abort(struct spi_master *master)
1584 {
1585 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1586
1587 spi_imx->slave_aborted = true;
1588 complete(&spi_imx->xfer_done);
1589
1590 return 0;
1591 }
1592
spi_imx_probe(struct platform_device * pdev)1593 static int spi_imx_probe(struct platform_device *pdev)
1594 {
1595 struct device_node *np = pdev->dev.of_node;
1596 const struct of_device_id *of_id =
1597 of_match_device(spi_imx_dt_ids, &pdev->dev);
1598 struct spi_master *master;
1599 struct spi_imx_data *spi_imx;
1600 struct resource *res;
1601 int ret, irq, spi_drctl;
1602 const struct spi_imx_devtype_data *devtype_data = of_id ? of_id->data :
1603 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
1604 bool slave_mode;
1605 u32 val;
1606
1607 slave_mode = devtype_data->has_slavemode &&
1608 of_property_read_bool(np, "spi-slave");
1609 if (slave_mode)
1610 master = spi_alloc_slave(&pdev->dev,
1611 sizeof(struct spi_imx_data));
1612 else
1613 master = spi_alloc_master(&pdev->dev,
1614 sizeof(struct spi_imx_data));
1615 if (!master)
1616 return -ENOMEM;
1617
1618 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
1619 if ((ret < 0) || (spi_drctl >= 0x3)) {
1620 /* '11' is reserved */
1621 spi_drctl = 0;
1622 }
1623
1624 platform_set_drvdata(pdev, master);
1625
1626 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1627 master->bus_num = np ? -1 : pdev->id;
1628 master->use_gpio_descriptors = true;
1629
1630 spi_imx = spi_master_get_devdata(master);
1631 spi_imx->bitbang.master = master;
1632 spi_imx->dev = &pdev->dev;
1633 spi_imx->slave_mode = slave_mode;
1634
1635 spi_imx->devtype_data = devtype_data;
1636
1637 /*
1638 * Get number of chip selects from device properties. This can be
1639 * coming from device tree or boardfiles, if it is not defined,
1640 * a default value of 3 chip selects will be used, as all the legacy
1641 * board files have <= 3 chip selects.
1642 */
1643 if (!device_property_read_u32(&pdev->dev, "num-cs", &val))
1644 master->num_chipselect = val;
1645 else
1646 master->num_chipselect = 3;
1647
1648 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1649 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1650 spi_imx->bitbang.master->setup = spi_imx_setup;
1651 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1652 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1653 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1654 spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort;
1655 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
1656 | SPI_NO_CS;
1657 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
1658 is_imx53_ecspi(spi_imx))
1659 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
1660
1661 spi_imx->spi_drctl = spi_drctl;
1662
1663 init_completion(&spi_imx->xfer_done);
1664
1665 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1666 spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1667 if (IS_ERR(spi_imx->base)) {
1668 ret = PTR_ERR(spi_imx->base);
1669 goto out_master_put;
1670 }
1671 spi_imx->base_phys = res->start;
1672
1673 irq = platform_get_irq(pdev, 0);
1674 if (irq < 0) {
1675 ret = irq;
1676 goto out_master_put;
1677 }
1678
1679 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1680 dev_name(&pdev->dev), spi_imx);
1681 if (ret) {
1682 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1683 goto out_master_put;
1684 }
1685
1686 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1687 if (IS_ERR(spi_imx->clk_ipg)) {
1688 ret = PTR_ERR(spi_imx->clk_ipg);
1689 goto out_master_put;
1690 }
1691
1692 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1693 if (IS_ERR(spi_imx->clk_per)) {
1694 ret = PTR_ERR(spi_imx->clk_per);
1695 goto out_master_put;
1696 }
1697
1698 ret = clk_prepare_enable(spi_imx->clk_per);
1699 if (ret)
1700 goto out_master_put;
1701
1702 ret = clk_prepare_enable(spi_imx->clk_ipg);
1703 if (ret)
1704 goto out_put_per;
1705
1706 pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT);
1707 pm_runtime_use_autosuspend(spi_imx->dev);
1708 pm_runtime_get_noresume(spi_imx->dev);
1709 pm_runtime_set_active(spi_imx->dev);
1710 pm_runtime_enable(spi_imx->dev);
1711
1712 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1713 /*
1714 * Only validated on i.mx35 and i.mx6 now, can remove the constraint
1715 * if validated on other chips.
1716 */
1717 if (spi_imx->devtype_data->has_dmamode) {
1718 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
1719 if (ret == -EPROBE_DEFER)
1720 goto out_runtime_pm_put;
1721
1722 if (ret < 0)
1723 dev_dbg(&pdev->dev, "dma setup error %d, use pio\n",
1724 ret);
1725 }
1726
1727 spi_imx->devtype_data->reset(spi_imx);
1728
1729 spi_imx->devtype_data->intctrl(spi_imx, 0);
1730
1731 master->dev.of_node = pdev->dev.of_node;
1732 ret = spi_bitbang_start(&spi_imx->bitbang);
1733 if (ret) {
1734 dev_err_probe(&pdev->dev, ret, "bitbang start failed\n");
1735 goto out_bitbang_start;
1736 }
1737
1738 pm_runtime_mark_last_busy(spi_imx->dev);
1739 pm_runtime_put_autosuspend(spi_imx->dev);
1740
1741 return ret;
1742
1743 out_bitbang_start:
1744 if (spi_imx->devtype_data->has_dmamode)
1745 spi_imx_sdma_exit(spi_imx);
1746 out_runtime_pm_put:
1747 pm_runtime_dont_use_autosuspend(spi_imx->dev);
1748 pm_runtime_set_suspended(&pdev->dev);
1749 pm_runtime_disable(spi_imx->dev);
1750
1751 clk_disable_unprepare(spi_imx->clk_ipg);
1752 out_put_per:
1753 clk_disable_unprepare(spi_imx->clk_per);
1754 out_master_put:
1755 spi_master_put(master);
1756
1757 return ret;
1758 }
1759
spi_imx_remove(struct platform_device * pdev)1760 static int spi_imx_remove(struct platform_device *pdev)
1761 {
1762 struct spi_master *master = platform_get_drvdata(pdev);
1763 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1764 int ret;
1765
1766 spi_bitbang_stop(&spi_imx->bitbang);
1767
1768 ret = pm_runtime_get_sync(spi_imx->dev);
1769 if (ret < 0) {
1770 pm_runtime_put_noidle(spi_imx->dev);
1771 dev_err(spi_imx->dev, "failed to enable clock\n");
1772 return ret;
1773 }
1774
1775 writel(0, spi_imx->base + MXC_CSPICTRL);
1776
1777 pm_runtime_dont_use_autosuspend(spi_imx->dev);
1778 pm_runtime_put_sync(spi_imx->dev);
1779 pm_runtime_disable(spi_imx->dev);
1780
1781 spi_imx_sdma_exit(spi_imx);
1782 spi_master_put(master);
1783
1784 return 0;
1785 }
1786
spi_imx_runtime_resume(struct device * dev)1787 static int __maybe_unused spi_imx_runtime_resume(struct device *dev)
1788 {
1789 struct spi_master *master = dev_get_drvdata(dev);
1790 struct spi_imx_data *spi_imx;
1791 int ret;
1792
1793 spi_imx = spi_master_get_devdata(master);
1794
1795 ret = clk_prepare_enable(spi_imx->clk_per);
1796 if (ret)
1797 return ret;
1798
1799 ret = clk_prepare_enable(spi_imx->clk_ipg);
1800 if (ret) {
1801 clk_disable_unprepare(spi_imx->clk_per);
1802 return ret;
1803 }
1804
1805 return 0;
1806 }
1807
spi_imx_runtime_suspend(struct device * dev)1808 static int __maybe_unused spi_imx_runtime_suspend(struct device *dev)
1809 {
1810 struct spi_master *master = dev_get_drvdata(dev);
1811 struct spi_imx_data *spi_imx;
1812
1813 spi_imx = spi_master_get_devdata(master);
1814
1815 clk_disable_unprepare(spi_imx->clk_per);
1816 clk_disable_unprepare(spi_imx->clk_ipg);
1817
1818 return 0;
1819 }
1820
spi_imx_suspend(struct device * dev)1821 static int __maybe_unused spi_imx_suspend(struct device *dev)
1822 {
1823 pinctrl_pm_select_sleep_state(dev);
1824 return 0;
1825 }
1826
spi_imx_resume(struct device * dev)1827 static int __maybe_unused spi_imx_resume(struct device *dev)
1828 {
1829 pinctrl_pm_select_default_state(dev);
1830 return 0;
1831 }
1832
1833 static const struct dev_pm_ops imx_spi_pm = {
1834 SET_RUNTIME_PM_OPS(spi_imx_runtime_suspend,
1835 spi_imx_runtime_resume, NULL)
1836 SET_SYSTEM_SLEEP_PM_OPS(spi_imx_suspend, spi_imx_resume)
1837 };
1838
1839 static struct platform_driver spi_imx_driver = {
1840 .driver = {
1841 .name = DRIVER_NAME,
1842 .of_match_table = spi_imx_dt_ids,
1843 .pm = &imx_spi_pm,
1844 },
1845 .id_table = spi_imx_devtype,
1846 .probe = spi_imx_probe,
1847 .remove = spi_imx_remove,
1848 };
1849 module_platform_driver(spi_imx_driver);
1850
1851 MODULE_DESCRIPTION("SPI Controller driver");
1852 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1853 MODULE_LICENSE("GPL");
1854 MODULE_ALIAS("platform:" DRIVER_NAME);
1855