1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Freescale SPI controller driver. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Maintainer: Kumar Gala 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (C) 2006 Polycom, Inc. 8*4882a593Smuzhiyun * Copyright 2010 Freescale Semiconductor, Inc. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * CPM SPI and QE buffer descriptors mode support: 11*4882a593Smuzhiyun * Copyright (c) 2009 MontaVista Software, Inc. 12*4882a593Smuzhiyun * Author: Anton Vorontsov <avorontsov@ru.mvista.com> 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * GRLIB support: 15*4882a593Smuzhiyun * Copyright (c) 2012 Aeroflex Gaisler AB. 16*4882a593Smuzhiyun * Author: Andreas Larsson <andreas@gaisler.com> 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #ifndef __SPI_FSL_SPI_H__ 20*4882a593Smuzhiyun #define __SPI_FSL_SPI_H__ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* SPI Controller registers */ 23*4882a593Smuzhiyun struct fsl_spi_reg { 24*4882a593Smuzhiyun __be32 cap; /* TYPE_GRLIB specific */ 25*4882a593Smuzhiyun u8 res1[0x1C]; 26*4882a593Smuzhiyun __be32 mode; 27*4882a593Smuzhiyun __be32 event; 28*4882a593Smuzhiyun __be32 mask; 29*4882a593Smuzhiyun __be32 command; 30*4882a593Smuzhiyun __be32 transmit; 31*4882a593Smuzhiyun __be32 receive; 32*4882a593Smuzhiyun __be32 slvsel; /* TYPE_GRLIB specific */ 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* SPI Controller mode register definitions */ 36*4882a593Smuzhiyun #define SPMODE_LOOP (1 << 30) 37*4882a593Smuzhiyun #define SPMODE_CI_INACTIVEHIGH (1 << 29) 38*4882a593Smuzhiyun #define SPMODE_CP_BEGIN_EDGECLK (1 << 28) 39*4882a593Smuzhiyun #define SPMODE_DIV16 (1 << 27) 40*4882a593Smuzhiyun #define SPMODE_REV (1 << 26) 41*4882a593Smuzhiyun #define SPMODE_MS (1 << 25) 42*4882a593Smuzhiyun #define SPMODE_ENABLE (1 << 24) 43*4882a593Smuzhiyun #define SPMODE_LEN(x) ((x) << 20) 44*4882a593Smuzhiyun #define SPMODE_PM(x) ((x) << 16) 45*4882a593Smuzhiyun #define SPMODE_OP (1 << 14) 46*4882a593Smuzhiyun #define SPMODE_CG(x) ((x) << 7) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* TYPE_GRLIB SPI Controller capability register definitions */ 49*4882a593Smuzhiyun #define SPCAP_SSEN(x) (((x) >> 16) & 0x1) 50*4882a593Smuzhiyun #define SPCAP_SSSZ(x) (((x) >> 24) & 0xff) 51*4882a593Smuzhiyun #define SPCAP_MAXWLEN(x) (((x) >> 20) & 0xf) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* 54*4882a593Smuzhiyun * Default for SPI Mode: 55*4882a593Smuzhiyun * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \ 58*4882a593Smuzhiyun SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf)) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* SPIE register values */ 61*4882a593Smuzhiyun #define SPIE_NE 0x00000200 /* Not empty */ 62*4882a593Smuzhiyun #define SPIE_NF 0x00000100 /* Not full */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* SPIM register values */ 65*4882a593Smuzhiyun #define SPIM_NE 0x00000200 /* Not empty */ 66*4882a593Smuzhiyun #define SPIM_NF 0x00000100 /* Not full */ 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #endif /* __SPI_FSL_SPI_H__ */ 69