1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Freescale SPI/eSPI controller driver library.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Maintainer: Kumar Gala
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright 2010 Freescale Semiconductor, Inc.
8*4882a593Smuzhiyun * Copyright (C) 2006 Polycom, Inc.
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * CPM SPI and QE buffer descriptors mode support:
11*4882a593Smuzhiyun * Copyright (c) 2009 MontaVista Software, Inc.
12*4882a593Smuzhiyun * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun #ifndef __SPI_FSL_LIB_H__
15*4882a593Smuzhiyun #define __SPI_FSL_LIB_H__
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <asm/io.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /* SPI/eSPI Controller driver's private data. */
20*4882a593Smuzhiyun struct mpc8xxx_spi {
21*4882a593Smuzhiyun struct device *dev;
22*4882a593Smuzhiyun void __iomem *reg_base;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* rx & tx bufs from the spi_transfer */
25*4882a593Smuzhiyun const void *tx;
26*4882a593Smuzhiyun void *rx;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun int subblock;
29*4882a593Smuzhiyun struct spi_pram __iomem *pram;
30*4882a593Smuzhiyun #ifdef CONFIG_FSL_SOC
31*4882a593Smuzhiyun struct cpm_buf_desc __iomem *tx_bd;
32*4882a593Smuzhiyun struct cpm_buf_desc __iomem *rx_bd;
33*4882a593Smuzhiyun #endif
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun struct spi_transfer *xfer_in_progress;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* dma addresses for CPM transfers */
38*4882a593Smuzhiyun dma_addr_t tx_dma;
39*4882a593Smuzhiyun dma_addr_t rx_dma;
40*4882a593Smuzhiyun bool map_tx_dma;
41*4882a593Smuzhiyun bool map_rx_dma;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun dma_addr_t dma_dummy_tx;
44*4882a593Smuzhiyun dma_addr_t dma_dummy_rx;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* functions to deal with different sized buffers */
47*4882a593Smuzhiyun void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
48*4882a593Smuzhiyun u32(*get_tx) (struct mpc8xxx_spi *);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun unsigned int count;
51*4882a593Smuzhiyun unsigned int irq;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun unsigned nsecs; /* (clock cycle time)/2 */
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun u32 spibrg; /* SPIBRG input clock */
56*4882a593Smuzhiyun u32 rx_shift; /* RX data reg shift when in qe mode */
57*4882a593Smuzhiyun u32 tx_shift; /* TX data reg shift when in qe mode */
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun unsigned int flags;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SPI_FSL_SPI)
62*4882a593Smuzhiyun int type;
63*4882a593Smuzhiyun int native_chipselects;
64*4882a593Smuzhiyun u8 max_bits_per_word;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun void (*set_shifts)(u32 *rx_shift, u32 *tx_shift,
67*4882a593Smuzhiyun int bits_per_word, int msb_first);
68*4882a593Smuzhiyun #endif
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun struct completion done;
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun struct spi_mpc8xxx_cs {
74*4882a593Smuzhiyun /* functions to deal with different sized buffers */
75*4882a593Smuzhiyun void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
76*4882a593Smuzhiyun u32 (*get_tx) (struct mpc8xxx_spi *);
77*4882a593Smuzhiyun u32 rx_shift; /* RX data reg shift when in qe mode */
78*4882a593Smuzhiyun u32 tx_shift; /* TX data reg shift when in qe mode */
79*4882a593Smuzhiyun u32 hw_mode; /* Holds HW mode register settings */
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun
mpc8xxx_spi_write_reg(__be32 __iomem * reg,u32 val)82*4882a593Smuzhiyun static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun iowrite32be(val, reg);
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
mpc8xxx_spi_read_reg(__be32 __iomem * reg)87*4882a593Smuzhiyun static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun return ioread32be(reg);
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun struct mpc8xxx_spi_probe_info {
93*4882a593Smuzhiyun struct fsl_spi_platform_data pdata;
94*4882a593Smuzhiyun __be32 __iomem *immr_spi_cs;
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun extern u32 mpc8xxx_spi_tx_buf_u8(struct mpc8xxx_spi *mpc8xxx_spi);
98*4882a593Smuzhiyun extern u32 mpc8xxx_spi_tx_buf_u16(struct mpc8xxx_spi *mpc8xxx_spi);
99*4882a593Smuzhiyun extern u32 mpc8xxx_spi_tx_buf_u32(struct mpc8xxx_spi *mpc8xxx_spi);
100*4882a593Smuzhiyun extern void mpc8xxx_spi_rx_buf_u8(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
101*4882a593Smuzhiyun extern void mpc8xxx_spi_rx_buf_u16(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
102*4882a593Smuzhiyun extern void mpc8xxx_spi_rx_buf_u32(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun extern struct mpc8xxx_spi_probe_info *to_of_pinfo(
105*4882a593Smuzhiyun struct fsl_spi_platform_data *pdata);
106*4882a593Smuzhiyun extern int mpc8xxx_spi_bufs(struct mpc8xxx_spi *mspi,
107*4882a593Smuzhiyun struct spi_transfer *t, unsigned int len);
108*4882a593Smuzhiyun extern const char *mpc8xxx_spi_strmode(unsigned int flags);
109*4882a593Smuzhiyun extern void mpc8xxx_spi_probe(struct device *dev, struct resource *mem,
110*4882a593Smuzhiyun unsigned int irq);
111*4882a593Smuzhiyun extern int mpc8xxx_spi_remove(struct device *dev);
112*4882a593Smuzhiyun extern int of_mpc8xxx_spi_probe(struct platform_device *ofdev);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun #endif /* __SPI_FSL_LIB_H__ */
115