1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Freescale SPI/eSPI controller driver library.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Maintainer: Kumar Gala
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2006 Polycom, Inc.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * CPM SPI and QE buffer descriptors mode support:
10*4882a593Smuzhiyun * Copyright (c) 2009 MontaVista Software, Inc.
11*4882a593Smuzhiyun * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * Copyright 2010 Freescale Semiconductor, Inc.
14*4882a593Smuzhiyun */
15*4882a593Smuzhiyun #include <linux/dma-mapping.h>
16*4882a593Smuzhiyun #include <linux/fsl_devices.h>
17*4882a593Smuzhiyun #include <linux/interrupt.h>
18*4882a593Smuzhiyun #include <linux/kernel.h>
19*4882a593Smuzhiyun #include <linux/mm.h>
20*4882a593Smuzhiyun #include <linux/module.h>
21*4882a593Smuzhiyun #include <linux/of_platform.h>
22*4882a593Smuzhiyun #include <linux/spi/spi.h>
23*4882a593Smuzhiyun #ifdef CONFIG_FSL_SOC
24*4882a593Smuzhiyun #include <sysdev/fsl_soc.h>
25*4882a593Smuzhiyun #endif
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include "spi-fsl-lib.h"
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define MPC8XXX_SPI_RX_BUF(type) \
30*4882a593Smuzhiyun void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
31*4882a593Smuzhiyun { \
32*4882a593Smuzhiyun type *rx = mpc8xxx_spi->rx; \
33*4882a593Smuzhiyun *rx++ = (type)(data >> mpc8xxx_spi->rx_shift); \
34*4882a593Smuzhiyun mpc8xxx_spi->rx = rx; \
35*4882a593Smuzhiyun } \
36*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mpc8xxx_spi_rx_buf_##type);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #define MPC8XXX_SPI_TX_BUF(type) \
39*4882a593Smuzhiyun u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \
40*4882a593Smuzhiyun { \
41*4882a593Smuzhiyun u32 data; \
42*4882a593Smuzhiyun const type *tx = mpc8xxx_spi->tx; \
43*4882a593Smuzhiyun if (!tx) \
44*4882a593Smuzhiyun return 0; \
45*4882a593Smuzhiyun data = *tx++ << mpc8xxx_spi->tx_shift; \
46*4882a593Smuzhiyun mpc8xxx_spi->tx = tx; \
47*4882a593Smuzhiyun return data; \
48*4882a593Smuzhiyun } \
49*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mpc8xxx_spi_tx_buf_##type);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun MPC8XXX_SPI_RX_BUF(u8)
MPC8XXX_SPI_RX_BUF(u16)52*4882a593Smuzhiyun MPC8XXX_SPI_RX_BUF(u16)
53*4882a593Smuzhiyun MPC8XXX_SPI_RX_BUF(u32)
54*4882a593Smuzhiyun MPC8XXX_SPI_TX_BUF(u8)
55*4882a593Smuzhiyun MPC8XXX_SPI_TX_BUF(u16)
56*4882a593Smuzhiyun MPC8XXX_SPI_TX_BUF(u32)
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun struct mpc8xxx_spi_probe_info *to_of_pinfo(struct fsl_spi_platform_data *pdata)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(to_of_pinfo);
63*4882a593Smuzhiyun
mpc8xxx_spi_strmode(unsigned int flags)64*4882a593Smuzhiyun const char *mpc8xxx_spi_strmode(unsigned int flags)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun if (flags & SPI_QE_CPU_MODE) {
67*4882a593Smuzhiyun return "QE CPU";
68*4882a593Smuzhiyun } else if (flags & SPI_CPM_MODE) {
69*4882a593Smuzhiyun if (flags & SPI_QE)
70*4882a593Smuzhiyun return "QE";
71*4882a593Smuzhiyun else if (flags & SPI_CPM2)
72*4882a593Smuzhiyun return "CPM2";
73*4882a593Smuzhiyun else
74*4882a593Smuzhiyun return "CPM1";
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun return "CPU";
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mpc8xxx_spi_strmode);
79*4882a593Smuzhiyun
mpc8xxx_spi_probe(struct device * dev,struct resource * mem,unsigned int irq)80*4882a593Smuzhiyun void mpc8xxx_spi_probe(struct device *dev, struct resource *mem,
81*4882a593Smuzhiyun unsigned int irq)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
84*4882a593Smuzhiyun struct spi_master *master;
85*4882a593Smuzhiyun struct mpc8xxx_spi *mpc8xxx_spi;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun master = dev_get_drvdata(dev);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* the spi->mode bits understood by this driver: */
90*4882a593Smuzhiyun master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
91*4882a593Smuzhiyun | SPI_LSB_FIRST | SPI_LOOP;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun master->dev.of_node = dev->of_node;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun mpc8xxx_spi = spi_master_get_devdata(master);
96*4882a593Smuzhiyun mpc8xxx_spi->dev = dev;
97*4882a593Smuzhiyun mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8;
98*4882a593Smuzhiyun mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8;
99*4882a593Smuzhiyun mpc8xxx_spi->flags = pdata->flags;
100*4882a593Smuzhiyun mpc8xxx_spi->spibrg = pdata->sysclk;
101*4882a593Smuzhiyun mpc8xxx_spi->irq = irq;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun mpc8xxx_spi->rx_shift = 0;
104*4882a593Smuzhiyun mpc8xxx_spi->tx_shift = 0;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun master->bus_num = pdata->bus_num;
107*4882a593Smuzhiyun master->num_chipselect = pdata->max_chipselect;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun init_completion(&mpc8xxx_spi->done);
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mpc8xxx_spi_probe);
112*4882a593Smuzhiyun
of_mpc8xxx_spi_probe(struct platform_device * ofdev)113*4882a593Smuzhiyun int of_mpc8xxx_spi_probe(struct platform_device *ofdev)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun struct device *dev = &ofdev->dev;
116*4882a593Smuzhiyun struct device_node *np = ofdev->dev.of_node;
117*4882a593Smuzhiyun struct mpc8xxx_spi_probe_info *pinfo;
118*4882a593Smuzhiyun struct fsl_spi_platform_data *pdata;
119*4882a593Smuzhiyun const void *prop;
120*4882a593Smuzhiyun int ret = -ENOMEM;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun pinfo = devm_kzalloc(&ofdev->dev, sizeof(*pinfo), GFP_KERNEL);
123*4882a593Smuzhiyun if (!pinfo)
124*4882a593Smuzhiyun return ret;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun pdata = &pinfo->pdata;
127*4882a593Smuzhiyun dev->platform_data = pdata;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun /* Allocate bus num dynamically. */
130*4882a593Smuzhiyun pdata->bus_num = -1;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun #ifdef CONFIG_FSL_SOC
133*4882a593Smuzhiyun /* SPI controller is either clocked from QE or SoC clock. */
134*4882a593Smuzhiyun pdata->sysclk = get_brgfreq();
135*4882a593Smuzhiyun if (pdata->sysclk == -1) {
136*4882a593Smuzhiyun pdata->sysclk = fsl_get_sys_freq();
137*4882a593Smuzhiyun if (pdata->sysclk == -1)
138*4882a593Smuzhiyun return -ENODEV;
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun #else
141*4882a593Smuzhiyun ret = of_property_read_u32(np, "clock-frequency", &pdata->sysclk);
142*4882a593Smuzhiyun if (ret)
143*4882a593Smuzhiyun return ret;
144*4882a593Smuzhiyun #endif
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun prop = of_get_property(np, "mode", NULL);
147*4882a593Smuzhiyun if (prop && !strcmp(prop, "cpu-qe"))
148*4882a593Smuzhiyun pdata->flags = SPI_QE_CPU_MODE;
149*4882a593Smuzhiyun else if (prop && !strcmp(prop, "qe"))
150*4882a593Smuzhiyun pdata->flags = SPI_CPM_MODE | SPI_QE;
151*4882a593Smuzhiyun else if (of_device_is_compatible(np, "fsl,cpm2-spi"))
152*4882a593Smuzhiyun pdata->flags = SPI_CPM_MODE | SPI_CPM2;
153*4882a593Smuzhiyun else if (of_device_is_compatible(np, "fsl,cpm1-spi"))
154*4882a593Smuzhiyun pdata->flags = SPI_CPM_MODE | SPI_CPM1;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun return 0;
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(of_mpc8xxx_spi_probe);
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun MODULE_LICENSE("GPL");
161