1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public
3*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive
4*4882a593Smuzhiyun * for more details.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2011, 2012 Cavium, Inc.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/platform_device.h>
10*4882a593Smuzhiyun #include <linux/spi/spi.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/io.h>
13*4882a593Smuzhiyun #include <linux/of.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <asm/octeon/octeon.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include "spi-cavium.h"
18*4882a593Smuzhiyun
octeon_spi_probe(struct platform_device * pdev)19*4882a593Smuzhiyun static int octeon_spi_probe(struct platform_device *pdev)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun void __iomem *reg_base;
22*4882a593Smuzhiyun struct spi_master *master;
23*4882a593Smuzhiyun struct octeon_spi *p;
24*4882a593Smuzhiyun int err = -ENOENT;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun master = spi_alloc_master(&pdev->dev, sizeof(struct octeon_spi));
27*4882a593Smuzhiyun if (!master)
28*4882a593Smuzhiyun return -ENOMEM;
29*4882a593Smuzhiyun p = spi_master_get_devdata(master);
30*4882a593Smuzhiyun platform_set_drvdata(pdev, master);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun reg_base = devm_platform_ioremap_resource(pdev, 0);
33*4882a593Smuzhiyun if (IS_ERR(reg_base)) {
34*4882a593Smuzhiyun err = PTR_ERR(reg_base);
35*4882a593Smuzhiyun goto fail;
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun p->register_base = reg_base;
39*4882a593Smuzhiyun p->sys_freq = octeon_get_io_clock_rate();
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun p->regs.config = 0;
42*4882a593Smuzhiyun p->regs.status = 0x08;
43*4882a593Smuzhiyun p->regs.tx = 0x10;
44*4882a593Smuzhiyun p->regs.data = 0x80;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun master->num_chipselect = 4;
47*4882a593Smuzhiyun master->mode_bits = SPI_CPHA |
48*4882a593Smuzhiyun SPI_CPOL |
49*4882a593Smuzhiyun SPI_CS_HIGH |
50*4882a593Smuzhiyun SPI_LSB_FIRST |
51*4882a593Smuzhiyun SPI_3WIRE;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun master->transfer_one_message = octeon_spi_transfer_one_message;
54*4882a593Smuzhiyun master->bits_per_word_mask = SPI_BPW_MASK(8);
55*4882a593Smuzhiyun master->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun master->dev.of_node = pdev->dev.of_node;
58*4882a593Smuzhiyun err = devm_spi_register_master(&pdev->dev, master);
59*4882a593Smuzhiyun if (err) {
60*4882a593Smuzhiyun dev_err(&pdev->dev, "register master failed: %d\n", err);
61*4882a593Smuzhiyun goto fail;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun dev_info(&pdev->dev, "OCTEON SPI bus driver\n");
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun return 0;
67*4882a593Smuzhiyun fail:
68*4882a593Smuzhiyun spi_master_put(master);
69*4882a593Smuzhiyun return err;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
octeon_spi_remove(struct platform_device * pdev)72*4882a593Smuzhiyun static int octeon_spi_remove(struct platform_device *pdev)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun struct spi_master *master = platform_get_drvdata(pdev);
75*4882a593Smuzhiyun struct octeon_spi *p = spi_master_get_devdata(master);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* Clear the CSENA* and put everything in a known state. */
78*4882a593Smuzhiyun writeq(0, p->register_base + OCTEON_SPI_CFG(p));
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun return 0;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun static const struct of_device_id octeon_spi_match[] = {
84*4882a593Smuzhiyun { .compatible = "cavium,octeon-3010-spi", },
85*4882a593Smuzhiyun {},
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, octeon_spi_match);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun static struct platform_driver octeon_spi_driver = {
90*4882a593Smuzhiyun .driver = {
91*4882a593Smuzhiyun .name = "spi-octeon",
92*4882a593Smuzhiyun .of_match_table = octeon_spi_match,
93*4882a593Smuzhiyun },
94*4882a593Smuzhiyun .probe = octeon_spi_probe,
95*4882a593Smuzhiyun .remove = octeon_spi_remove,
96*4882a593Smuzhiyun };
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun module_platform_driver(octeon_spi_driver);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun MODULE_DESCRIPTION("Cavium, Inc. OCTEON SPI bus driver");
101*4882a593Smuzhiyun MODULE_AUTHOR("David Daney");
102*4882a593Smuzhiyun MODULE_LICENSE("GPL");
103