1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2016 Broadcom
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #ifndef __SPI_BCM_QSPI_H__
7*4882a593Smuzhiyun #define __SPI_BCM_QSPI_H__
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/types.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun /* BSPI interrupt masks */
13*4882a593Smuzhiyun #define INTR_BSPI_LR_OVERREAD_MASK BIT(4)
14*4882a593Smuzhiyun #define INTR_BSPI_LR_SESSION_DONE_MASK BIT(3)
15*4882a593Smuzhiyun #define INTR_BSPI_LR_IMPATIENT_MASK BIT(2)
16*4882a593Smuzhiyun #define INTR_BSPI_LR_SESSION_ABORTED_MASK BIT(1)
17*4882a593Smuzhiyun #define INTR_BSPI_LR_FULLNESS_REACHED_MASK BIT(0)
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define BSPI_LR_INTERRUPTS_DATA \
20*4882a593Smuzhiyun (INTR_BSPI_LR_SESSION_DONE_MASK | \
21*4882a593Smuzhiyun INTR_BSPI_LR_FULLNESS_REACHED_MASK)
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define BSPI_LR_INTERRUPTS_ERROR \
24*4882a593Smuzhiyun (INTR_BSPI_LR_OVERREAD_MASK | \
25*4882a593Smuzhiyun INTR_BSPI_LR_IMPATIENT_MASK | \
26*4882a593Smuzhiyun INTR_BSPI_LR_SESSION_ABORTED_MASK)
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define BSPI_LR_INTERRUPTS_ALL \
29*4882a593Smuzhiyun (BSPI_LR_INTERRUPTS_ERROR | \
30*4882a593Smuzhiyun BSPI_LR_INTERRUPTS_DATA)
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* MSPI Interrupt masks */
33*4882a593Smuzhiyun #define INTR_MSPI_HALTED_MASK BIT(6)
34*4882a593Smuzhiyun #define INTR_MSPI_DONE_MASK BIT(5)
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define MSPI_INTERRUPTS_ALL \
37*4882a593Smuzhiyun (INTR_MSPI_DONE_MASK | \
38*4882a593Smuzhiyun INTR_MSPI_HALTED_MASK)
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #define QSPI_INTERRUPTS_ALL \
41*4882a593Smuzhiyun (MSPI_INTERRUPTS_ALL | \
42*4882a593Smuzhiyun BSPI_LR_INTERRUPTS_ALL)
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun struct platform_device;
45*4882a593Smuzhiyun struct dev_pm_ops;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun enum {
48*4882a593Smuzhiyun MSPI_DONE = 0x1,
49*4882a593Smuzhiyun BSPI_DONE = 0x2,
50*4882a593Smuzhiyun BSPI_ERR = 0x4,
51*4882a593Smuzhiyun MSPI_BSPI_DONE = 0x7
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun struct bcm_qspi_soc_intc {
55*4882a593Smuzhiyun void (*bcm_qspi_int_ack)(struct bcm_qspi_soc_intc *soc_intc, int type);
56*4882a593Smuzhiyun void (*bcm_qspi_int_set)(struct bcm_qspi_soc_intc *soc_intc, int type,
57*4882a593Smuzhiyun bool en);
58*4882a593Smuzhiyun u32 (*bcm_qspi_get_int_status)(struct bcm_qspi_soc_intc *soc_intc);
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* Read controller register*/
bcm_qspi_readl(bool be,void __iomem * addr)62*4882a593Smuzhiyun static inline u32 bcm_qspi_readl(bool be, void __iomem *addr)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun if (be)
65*4882a593Smuzhiyun return ioread32be(addr);
66*4882a593Smuzhiyun else
67*4882a593Smuzhiyun return readl_relaxed(addr);
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /* Write controller register*/
bcm_qspi_writel(bool be,unsigned int data,void __iomem * addr)71*4882a593Smuzhiyun static inline void bcm_qspi_writel(bool be,
72*4882a593Smuzhiyun unsigned int data, void __iomem *addr)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun if (be)
75*4882a593Smuzhiyun iowrite32be(data, addr);
76*4882a593Smuzhiyun else
77*4882a593Smuzhiyun writel_relaxed(data, addr);
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
get_qspi_mask(int type)80*4882a593Smuzhiyun static inline u32 get_qspi_mask(int type)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun switch (type) {
83*4882a593Smuzhiyun case MSPI_DONE:
84*4882a593Smuzhiyun return INTR_MSPI_DONE_MASK;
85*4882a593Smuzhiyun case BSPI_DONE:
86*4882a593Smuzhiyun return BSPI_LR_INTERRUPTS_ALL;
87*4882a593Smuzhiyun case MSPI_BSPI_DONE:
88*4882a593Smuzhiyun return QSPI_INTERRUPTS_ALL;
89*4882a593Smuzhiyun case BSPI_ERR:
90*4882a593Smuzhiyun return BSPI_LR_INTERRUPTS_ERROR;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun return 0;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /* The common driver functions to be called by the SoC platform driver */
97*4882a593Smuzhiyun int bcm_qspi_probe(struct platform_device *pdev,
98*4882a593Smuzhiyun struct bcm_qspi_soc_intc *soc_intc);
99*4882a593Smuzhiyun int bcm_qspi_remove(struct platform_device *pdev);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun /* pm_ops used by the SoC platform driver called on PM suspend/resume */
102*4882a593Smuzhiyun extern const struct dev_pm_ops bcm_qspi_pm_ops;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun #endif /* __SPI_BCM_QSPI_H__ */
105