1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Altera SPI driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2008 Thomas Chou <thomas@wytron.com.tw>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Based on spi_s3c24xx.c, which is:
8*4882a593Smuzhiyun * Copyright (c) 2006 Ben Dooks
9*4882a593Smuzhiyun * Copyright (c) 2006 Simtec Electronics
10*4882a593Smuzhiyun * Ben Dooks <ben@simtec.co.uk>
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/interrupt.h>
14*4882a593Smuzhiyun #include <linux/errno.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun #include <linux/spi/altera.h>
18*4882a593Smuzhiyun #include <linux/spi/spi.h>
19*4882a593Smuzhiyun #include <linux/io.h>
20*4882a593Smuzhiyun #include <linux/of.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define DRV_NAME "spi_altera"
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define ALTERA_SPI_RXDATA 0
25*4882a593Smuzhiyun #define ALTERA_SPI_TXDATA 4
26*4882a593Smuzhiyun #define ALTERA_SPI_STATUS 8
27*4882a593Smuzhiyun #define ALTERA_SPI_CONTROL 12
28*4882a593Smuzhiyun #define ALTERA_SPI_SLAVE_SEL 20
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define ALTERA_SPI_STATUS_ROE_MSK 0x8
31*4882a593Smuzhiyun #define ALTERA_SPI_STATUS_TOE_MSK 0x10
32*4882a593Smuzhiyun #define ALTERA_SPI_STATUS_TMT_MSK 0x20
33*4882a593Smuzhiyun #define ALTERA_SPI_STATUS_TRDY_MSK 0x40
34*4882a593Smuzhiyun #define ALTERA_SPI_STATUS_RRDY_MSK 0x80
35*4882a593Smuzhiyun #define ALTERA_SPI_STATUS_E_MSK 0x100
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define ALTERA_SPI_CONTROL_IROE_MSK 0x8
38*4882a593Smuzhiyun #define ALTERA_SPI_CONTROL_ITOE_MSK 0x10
39*4882a593Smuzhiyun #define ALTERA_SPI_CONTROL_ITRDY_MSK 0x40
40*4882a593Smuzhiyun #define ALTERA_SPI_CONTROL_IRRDY_MSK 0x80
41*4882a593Smuzhiyun #define ALTERA_SPI_CONTROL_IE_MSK 0x100
42*4882a593Smuzhiyun #define ALTERA_SPI_CONTROL_SSO_MSK 0x400
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define ALTERA_SPI_MAX_CS 32
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun enum altera_spi_type {
47*4882a593Smuzhiyun ALTERA_SPI_TYPE_UNKNOWN,
48*4882a593Smuzhiyun ALTERA_SPI_TYPE_SUBDEV,
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun struct altera_spi {
52*4882a593Smuzhiyun int irq;
53*4882a593Smuzhiyun int len;
54*4882a593Smuzhiyun int count;
55*4882a593Smuzhiyun int bytes_per_word;
56*4882a593Smuzhiyun u32 imr;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* data buffers */
59*4882a593Smuzhiyun const unsigned char *tx;
60*4882a593Smuzhiyun unsigned char *rx;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun struct regmap *regmap;
63*4882a593Smuzhiyun u32 regoff;
64*4882a593Smuzhiyun struct device *dev;
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun static const struct regmap_config spi_altera_config = {
68*4882a593Smuzhiyun .reg_bits = 32,
69*4882a593Smuzhiyun .reg_stride = 4,
70*4882a593Smuzhiyun .val_bits = 32,
71*4882a593Smuzhiyun .fast_io = true,
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun
altr_spi_writel(struct altera_spi * hw,unsigned int reg,unsigned int val)74*4882a593Smuzhiyun static int altr_spi_writel(struct altera_spi *hw, unsigned int reg,
75*4882a593Smuzhiyun unsigned int val)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun int ret;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun ret = regmap_write(hw->regmap, hw->regoff + reg, val);
80*4882a593Smuzhiyun if (ret)
81*4882a593Smuzhiyun dev_err(hw->dev, "fail to write reg 0x%x val 0x%x: %d\n",
82*4882a593Smuzhiyun reg, val, ret);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun return ret;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
altr_spi_readl(struct altera_spi * hw,unsigned int reg,unsigned int * val)87*4882a593Smuzhiyun static int altr_spi_readl(struct altera_spi *hw, unsigned int reg,
88*4882a593Smuzhiyun unsigned int *val)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun int ret;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun ret = regmap_read(hw->regmap, hw->regoff + reg, val);
93*4882a593Smuzhiyun if (ret)
94*4882a593Smuzhiyun dev_err(hw->dev, "fail to read reg 0x%x: %d\n", reg, ret);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun return ret;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
altera_spi_to_hw(struct spi_device * sdev)99*4882a593Smuzhiyun static inline struct altera_spi *altera_spi_to_hw(struct spi_device *sdev)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun return spi_master_get_devdata(sdev->master);
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
altera_spi_set_cs(struct spi_device * spi,bool is_high)104*4882a593Smuzhiyun static void altera_spi_set_cs(struct spi_device *spi, bool is_high)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun struct altera_spi *hw = altera_spi_to_hw(spi);
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun if (is_high) {
109*4882a593Smuzhiyun hw->imr &= ~ALTERA_SPI_CONTROL_SSO_MSK;
110*4882a593Smuzhiyun altr_spi_writel(hw, ALTERA_SPI_CONTROL, hw->imr);
111*4882a593Smuzhiyun altr_spi_writel(hw, ALTERA_SPI_SLAVE_SEL, 0);
112*4882a593Smuzhiyun } else {
113*4882a593Smuzhiyun altr_spi_writel(hw, ALTERA_SPI_SLAVE_SEL,
114*4882a593Smuzhiyun BIT(spi->chip_select));
115*4882a593Smuzhiyun hw->imr |= ALTERA_SPI_CONTROL_SSO_MSK;
116*4882a593Smuzhiyun altr_spi_writel(hw, ALTERA_SPI_CONTROL, hw->imr);
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
altera_spi_tx_word(struct altera_spi * hw)120*4882a593Smuzhiyun static void altera_spi_tx_word(struct altera_spi *hw)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun unsigned int txd = 0;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun if (hw->tx) {
125*4882a593Smuzhiyun switch (hw->bytes_per_word) {
126*4882a593Smuzhiyun case 1:
127*4882a593Smuzhiyun txd = hw->tx[hw->count];
128*4882a593Smuzhiyun break;
129*4882a593Smuzhiyun case 2:
130*4882a593Smuzhiyun txd = (hw->tx[hw->count * 2]
131*4882a593Smuzhiyun | (hw->tx[hw->count * 2 + 1] << 8));
132*4882a593Smuzhiyun break;
133*4882a593Smuzhiyun case 4:
134*4882a593Smuzhiyun txd = (hw->tx[hw->count * 4]
135*4882a593Smuzhiyun | (hw->tx[hw->count * 4 + 1] << 8)
136*4882a593Smuzhiyun | (hw->tx[hw->count * 4 + 2] << 16)
137*4882a593Smuzhiyun | (hw->tx[hw->count * 4 + 3] << 24));
138*4882a593Smuzhiyun break;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun altr_spi_writel(hw, ALTERA_SPI_TXDATA, txd);
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun
altera_spi_rx_word(struct altera_spi * hw)146*4882a593Smuzhiyun static void altera_spi_rx_word(struct altera_spi *hw)
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun unsigned int rxd;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun altr_spi_readl(hw, ALTERA_SPI_RXDATA, &rxd);
151*4882a593Smuzhiyun if (hw->rx) {
152*4882a593Smuzhiyun switch (hw->bytes_per_word) {
153*4882a593Smuzhiyun case 1:
154*4882a593Smuzhiyun hw->rx[hw->count] = rxd;
155*4882a593Smuzhiyun break;
156*4882a593Smuzhiyun case 2:
157*4882a593Smuzhiyun hw->rx[hw->count * 2] = rxd;
158*4882a593Smuzhiyun hw->rx[hw->count * 2 + 1] = rxd >> 8;
159*4882a593Smuzhiyun break;
160*4882a593Smuzhiyun case 4:
161*4882a593Smuzhiyun hw->rx[hw->count * 4] = rxd;
162*4882a593Smuzhiyun hw->rx[hw->count * 4 + 1] = rxd >> 8;
163*4882a593Smuzhiyun hw->rx[hw->count * 4 + 2] = rxd >> 16;
164*4882a593Smuzhiyun hw->rx[hw->count * 4 + 3] = rxd >> 24;
165*4882a593Smuzhiyun break;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun hw->count++;
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun
altera_spi_txrx(struct spi_master * master,struct spi_device * spi,struct spi_transfer * t)173*4882a593Smuzhiyun static int altera_spi_txrx(struct spi_master *master,
174*4882a593Smuzhiyun struct spi_device *spi, struct spi_transfer *t)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun struct altera_spi *hw = spi_master_get_devdata(master);
177*4882a593Smuzhiyun u32 val;
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun hw->tx = t->tx_buf;
180*4882a593Smuzhiyun hw->rx = t->rx_buf;
181*4882a593Smuzhiyun hw->count = 0;
182*4882a593Smuzhiyun hw->bytes_per_word = DIV_ROUND_UP(t->bits_per_word, 8);
183*4882a593Smuzhiyun hw->len = t->len / hw->bytes_per_word;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun if (hw->irq >= 0) {
186*4882a593Smuzhiyun /* enable receive interrupt */
187*4882a593Smuzhiyun hw->imr |= ALTERA_SPI_CONTROL_IRRDY_MSK;
188*4882a593Smuzhiyun altr_spi_writel(hw, ALTERA_SPI_CONTROL, hw->imr);
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun /* send the first byte */
191*4882a593Smuzhiyun altera_spi_tx_word(hw);
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun return 1;
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun while (hw->count < hw->len) {
197*4882a593Smuzhiyun altera_spi_tx_word(hw);
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun for (;;) {
200*4882a593Smuzhiyun altr_spi_readl(hw, ALTERA_SPI_STATUS, &val);
201*4882a593Smuzhiyun if (val & ALTERA_SPI_STATUS_RRDY_MSK)
202*4882a593Smuzhiyun break;
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun cpu_relax();
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun altera_spi_rx_word(hw);
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun spi_finalize_current_transfer(master);
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun return 0;
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun
altera_spi_irq(int irq,void * dev)214*4882a593Smuzhiyun static irqreturn_t altera_spi_irq(int irq, void *dev)
215*4882a593Smuzhiyun {
216*4882a593Smuzhiyun struct spi_master *master = dev;
217*4882a593Smuzhiyun struct altera_spi *hw = spi_master_get_devdata(master);
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun altera_spi_rx_word(hw);
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun if (hw->count < hw->len) {
222*4882a593Smuzhiyun altera_spi_tx_word(hw);
223*4882a593Smuzhiyun } else {
224*4882a593Smuzhiyun /* disable receive interrupt */
225*4882a593Smuzhiyun hw->imr &= ~ALTERA_SPI_CONTROL_IRRDY_MSK;
226*4882a593Smuzhiyun altr_spi_writel(hw, ALTERA_SPI_CONTROL, hw->imr);
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun spi_finalize_current_transfer(master);
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun return IRQ_HANDLED;
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun
altera_spi_probe(struct platform_device * pdev)234*4882a593Smuzhiyun static int altera_spi_probe(struct platform_device *pdev)
235*4882a593Smuzhiyun {
236*4882a593Smuzhiyun const struct platform_device_id *platid = platform_get_device_id(pdev);
237*4882a593Smuzhiyun struct altera_spi_platform_data *pdata = dev_get_platdata(&pdev->dev);
238*4882a593Smuzhiyun enum altera_spi_type type = ALTERA_SPI_TYPE_UNKNOWN;
239*4882a593Smuzhiyun struct altera_spi *hw;
240*4882a593Smuzhiyun struct spi_master *master;
241*4882a593Smuzhiyun int err = -ENODEV;
242*4882a593Smuzhiyun u32 val;
243*4882a593Smuzhiyun u16 i;
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun master = spi_alloc_master(&pdev->dev, sizeof(struct altera_spi));
246*4882a593Smuzhiyun if (!master)
247*4882a593Smuzhiyun return err;
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun /* setup the master state. */
250*4882a593Smuzhiyun master->bus_num = pdev->id;
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun if (pdata) {
253*4882a593Smuzhiyun if (pdata->num_chipselect > ALTERA_SPI_MAX_CS) {
254*4882a593Smuzhiyun dev_err(&pdev->dev,
255*4882a593Smuzhiyun "Invalid number of chipselect: %hu\n",
256*4882a593Smuzhiyun pdata->num_chipselect);
257*4882a593Smuzhiyun err = -EINVAL;
258*4882a593Smuzhiyun goto exit;
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun master->num_chipselect = pdata->num_chipselect;
262*4882a593Smuzhiyun master->mode_bits = pdata->mode_bits;
263*4882a593Smuzhiyun master->bits_per_word_mask = pdata->bits_per_word_mask;
264*4882a593Smuzhiyun } else {
265*4882a593Smuzhiyun master->num_chipselect = 16;
266*4882a593Smuzhiyun master->mode_bits = SPI_CS_HIGH;
267*4882a593Smuzhiyun master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16);
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun master->dev.of_node = pdev->dev.of_node;
271*4882a593Smuzhiyun master->transfer_one = altera_spi_txrx;
272*4882a593Smuzhiyun master->set_cs = altera_spi_set_cs;
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun hw = spi_master_get_devdata(master);
275*4882a593Smuzhiyun hw->dev = &pdev->dev;
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun if (platid)
278*4882a593Smuzhiyun type = platid->driver_data;
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun /* find and map our resources */
281*4882a593Smuzhiyun if (type == ALTERA_SPI_TYPE_SUBDEV) {
282*4882a593Smuzhiyun struct resource *regoff;
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun hw->regmap = dev_get_regmap(pdev->dev.parent, NULL);
285*4882a593Smuzhiyun if (!hw->regmap) {
286*4882a593Smuzhiyun dev_err(&pdev->dev, "get regmap failed\n");
287*4882a593Smuzhiyun goto exit;
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun regoff = platform_get_resource(pdev, IORESOURCE_REG, 0);
291*4882a593Smuzhiyun if (regoff)
292*4882a593Smuzhiyun hw->regoff = regoff->start;
293*4882a593Smuzhiyun } else {
294*4882a593Smuzhiyun void __iomem *res;
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun res = devm_platform_ioremap_resource(pdev, 0);
297*4882a593Smuzhiyun if (IS_ERR(res)) {
298*4882a593Smuzhiyun err = PTR_ERR(res);
299*4882a593Smuzhiyun goto exit;
300*4882a593Smuzhiyun }
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun hw->regmap = devm_regmap_init_mmio(&pdev->dev, res,
303*4882a593Smuzhiyun &spi_altera_config);
304*4882a593Smuzhiyun if (IS_ERR(hw->regmap)) {
305*4882a593Smuzhiyun dev_err(&pdev->dev, "regmap mmio init failed\n");
306*4882a593Smuzhiyun err = PTR_ERR(hw->regmap);
307*4882a593Smuzhiyun goto exit;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun }
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun /* program defaults into the registers */
312*4882a593Smuzhiyun hw->imr = 0; /* disable spi interrupts */
313*4882a593Smuzhiyun altr_spi_writel(hw, ALTERA_SPI_CONTROL, hw->imr);
314*4882a593Smuzhiyun altr_spi_writel(hw, ALTERA_SPI_STATUS, 0); /* clear status reg */
315*4882a593Smuzhiyun altr_spi_readl(hw, ALTERA_SPI_STATUS, &val);
316*4882a593Smuzhiyun if (val & ALTERA_SPI_STATUS_RRDY_MSK)
317*4882a593Smuzhiyun altr_spi_readl(hw, ALTERA_SPI_RXDATA, &val); /* flush rxdata */
318*4882a593Smuzhiyun /* irq is optional */
319*4882a593Smuzhiyun hw->irq = platform_get_irq(pdev, 0);
320*4882a593Smuzhiyun if (hw->irq >= 0) {
321*4882a593Smuzhiyun err = devm_request_irq(&pdev->dev, hw->irq, altera_spi_irq, 0,
322*4882a593Smuzhiyun pdev->name, master);
323*4882a593Smuzhiyun if (err)
324*4882a593Smuzhiyun goto exit;
325*4882a593Smuzhiyun }
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun err = devm_spi_register_master(&pdev->dev, master);
328*4882a593Smuzhiyun if (err)
329*4882a593Smuzhiyun goto exit;
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun if (pdata) {
332*4882a593Smuzhiyun for (i = 0; i < pdata->num_devices; i++) {
333*4882a593Smuzhiyun if (!spi_new_device(master, pdata->devices + i))
334*4882a593Smuzhiyun dev_warn(&pdev->dev,
335*4882a593Smuzhiyun "unable to create SPI device: %s\n",
336*4882a593Smuzhiyun pdata->devices[i].modalias);
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun }
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun dev_info(&pdev->dev, "regoff %u, irq %d\n", hw->regoff, hw->irq);
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun return 0;
343*4882a593Smuzhiyun exit:
344*4882a593Smuzhiyun spi_master_put(master);
345*4882a593Smuzhiyun return err;
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun #ifdef CONFIG_OF
349*4882a593Smuzhiyun static const struct of_device_id altera_spi_match[] = {
350*4882a593Smuzhiyun { .compatible = "ALTR,spi-1.0", },
351*4882a593Smuzhiyun { .compatible = "altr,spi-1.0", },
352*4882a593Smuzhiyun {},
353*4882a593Smuzhiyun };
354*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, altera_spi_match);
355*4882a593Smuzhiyun #endif /* CONFIG_OF */
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun static const struct platform_device_id altera_spi_ids[] = {
358*4882a593Smuzhiyun { DRV_NAME, ALTERA_SPI_TYPE_UNKNOWN },
359*4882a593Smuzhiyun { "subdev_spi_altera", ALTERA_SPI_TYPE_SUBDEV },
360*4882a593Smuzhiyun { }
361*4882a593Smuzhiyun };
362*4882a593Smuzhiyun MODULE_DEVICE_TABLE(platform, altera_spi_ids);
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun static struct platform_driver altera_spi_driver = {
365*4882a593Smuzhiyun .probe = altera_spi_probe,
366*4882a593Smuzhiyun .driver = {
367*4882a593Smuzhiyun .name = DRV_NAME,
368*4882a593Smuzhiyun .pm = NULL,
369*4882a593Smuzhiyun .of_match_table = of_match_ptr(altera_spi_match),
370*4882a593Smuzhiyun },
371*4882a593Smuzhiyun .id_table = altera_spi_ids,
372*4882a593Smuzhiyun };
373*4882a593Smuzhiyun module_platform_driver(altera_spi_driver);
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun MODULE_DESCRIPTION("Altera SPI driver");
376*4882a593Smuzhiyun MODULE_AUTHOR("Thomas Chou <thomas@wytron.com.tw>");
377*4882a593Smuzhiyun MODULE_LICENSE("GPL");
378*4882a593Smuzhiyun MODULE_ALIAS("platform:" DRV_NAME);
379