1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2*4882a593Smuzhiyun /* Copyright(c) 2015-17 Intel Corporation. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __SDW_INTEL_LOCAL_H 5*4882a593Smuzhiyun #define __SDW_INTEL_LOCAL_H 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /** 8*4882a593Smuzhiyun * struct sdw_intel_link_res - Soundwire Intel link resource structure, 9*4882a593Smuzhiyun * typically populated by the controller driver. 10*4882a593Smuzhiyun * @pdev: platform_device 11*4882a593Smuzhiyun * @mmio_base: mmio base of SoundWire registers 12*4882a593Smuzhiyun * @registers: Link IO registers base 13*4882a593Smuzhiyun * @shim: Audio shim pointer 14*4882a593Smuzhiyun * @alh: ALH (Audio Link Hub) pointer 15*4882a593Smuzhiyun * @irq: Interrupt line 16*4882a593Smuzhiyun * @ops: Shim callback ops 17*4882a593Smuzhiyun * @dev: device implementing hw_params and free callbacks 18*4882a593Smuzhiyun * @shim_lock: mutex to handle access to shared SHIM registers 19*4882a593Smuzhiyun * @shim_mask: global pointer to check SHIM register initialization 20*4882a593Smuzhiyun * @clock_stop_quirks: mask defining requested behavior on pm_suspend 21*4882a593Smuzhiyun * @link_mask: global mask needed for power-up/down sequences 22*4882a593Smuzhiyun * @cdns: Cadence master descriptor 23*4882a593Smuzhiyun * @list: used to walk-through all masters exposed by the same controller 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun struct sdw_intel_link_res { 26*4882a593Smuzhiyun struct platform_device *pdev; 27*4882a593Smuzhiyun void __iomem *mmio_base; /* not strictly needed, useful for debug */ 28*4882a593Smuzhiyun void __iomem *registers; 29*4882a593Smuzhiyun void __iomem *shim; 30*4882a593Smuzhiyun void __iomem *alh; 31*4882a593Smuzhiyun int irq; 32*4882a593Smuzhiyun const struct sdw_intel_ops *ops; 33*4882a593Smuzhiyun struct device *dev; 34*4882a593Smuzhiyun struct mutex *shim_lock; /* protect shared registers */ 35*4882a593Smuzhiyun u32 *shim_mask; 36*4882a593Smuzhiyun u32 clock_stop_quirks; 37*4882a593Smuzhiyun u32 link_mask; 38*4882a593Smuzhiyun struct sdw_cdns *cdns; 39*4882a593Smuzhiyun struct list_head list; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun struct sdw_intel { 43*4882a593Smuzhiyun struct sdw_cdns cdns; 44*4882a593Smuzhiyun int instance; 45*4882a593Smuzhiyun struct sdw_intel_link_res *link_res; 46*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_FS 47*4882a593Smuzhiyun struct dentry *debugfs; 48*4882a593Smuzhiyun #endif 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define SDW_INTEL_QUIRK_MASK_BUS_DISABLE BIT(1) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun int intel_master_startup(struct platform_device *pdev); 54*4882a593Smuzhiyun int intel_master_process_wakeen_event(struct platform_device *pdev); 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #endif /* __SDW_INTEL_LOCAL_H */ 57