1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/bug.h>
7*4882a593Smuzhiyun #include <linux/device.h>
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <soc/tegra/fuse.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "fuse.h"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define SOC_PROCESS_CORNERS 2
15*4882a593Smuzhiyun #define CPU_PROCESS_CORNERS 2
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun enum {
18*4882a593Smuzhiyun THRESHOLD_INDEX_0,
19*4882a593Smuzhiyun THRESHOLD_INDEX_1,
20*4882a593Smuzhiyun THRESHOLD_INDEX_COUNT,
21*4882a593Smuzhiyun };
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun static const u32 __initconst soc_process_speedos[][SOC_PROCESS_CORNERS] = {
24*4882a593Smuzhiyun {1123, UINT_MAX},
25*4882a593Smuzhiyun {0, UINT_MAX},
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun static const u32 __initconst cpu_process_speedos[][CPU_PROCESS_CORNERS] = {
29*4882a593Smuzhiyun {1695, UINT_MAX},
30*4882a593Smuzhiyun {0, UINT_MAX},
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
rev_sku_to_speedo_ids(struct tegra_sku_info * sku_info,int * threshold)33*4882a593Smuzhiyun static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info,
34*4882a593Smuzhiyun int *threshold)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun u32 tmp;
37*4882a593Smuzhiyun u32 sku = sku_info->sku_id;
38*4882a593Smuzhiyun enum tegra_revision rev = sku_info->revision;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun switch (sku) {
41*4882a593Smuzhiyun case 0x00:
42*4882a593Smuzhiyun case 0x10:
43*4882a593Smuzhiyun case 0x05:
44*4882a593Smuzhiyun case 0x06:
45*4882a593Smuzhiyun sku_info->cpu_speedo_id = 1;
46*4882a593Smuzhiyun sku_info->soc_speedo_id = 0;
47*4882a593Smuzhiyun *threshold = THRESHOLD_INDEX_0;
48*4882a593Smuzhiyun break;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun case 0x03:
51*4882a593Smuzhiyun case 0x04:
52*4882a593Smuzhiyun sku_info->cpu_speedo_id = 2;
53*4882a593Smuzhiyun sku_info->soc_speedo_id = 1;
54*4882a593Smuzhiyun *threshold = THRESHOLD_INDEX_1;
55*4882a593Smuzhiyun break;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun default:
58*4882a593Smuzhiyun pr_err("Tegra Unknown SKU %d\n", sku);
59*4882a593Smuzhiyun sku_info->cpu_speedo_id = 0;
60*4882a593Smuzhiyun sku_info->soc_speedo_id = 0;
61*4882a593Smuzhiyun *threshold = THRESHOLD_INDEX_0;
62*4882a593Smuzhiyun break;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun if (rev == TEGRA_REVISION_A01) {
66*4882a593Smuzhiyun tmp = tegra_fuse_read_early(0x270) << 1;
67*4882a593Smuzhiyun tmp |= tegra_fuse_read_early(0x26c);
68*4882a593Smuzhiyun if (!tmp)
69*4882a593Smuzhiyun sku_info->cpu_speedo_id = 0;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
tegra114_init_speedo_data(struct tegra_sku_info * sku_info)73*4882a593Smuzhiyun void __init tegra114_init_speedo_data(struct tegra_sku_info *sku_info)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun u32 cpu_speedo_val;
76*4882a593Smuzhiyun u32 soc_speedo_val;
77*4882a593Smuzhiyun int threshold;
78*4882a593Smuzhiyun int i;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
81*4882a593Smuzhiyun THRESHOLD_INDEX_COUNT);
82*4882a593Smuzhiyun BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) !=
83*4882a593Smuzhiyun THRESHOLD_INDEX_COUNT);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun rev_sku_to_speedo_ids(sku_info, &threshold);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun cpu_speedo_val = tegra_fuse_read_early(0x12c) + 1024;
88*4882a593Smuzhiyun soc_speedo_val = tegra_fuse_read_early(0x134);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun for (i = 0; i < CPU_PROCESS_CORNERS; i++)
91*4882a593Smuzhiyun if (cpu_speedo_val < cpu_process_speedos[threshold][i])
92*4882a593Smuzhiyun break;
93*4882a593Smuzhiyun sku_info->cpu_process_id = i;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun for (i = 0; i < SOC_PROCESS_CORNERS; i++)
96*4882a593Smuzhiyun if (soc_speedo_val < soc_process_speedos[threshold][i])
97*4882a593Smuzhiyun break;
98*4882a593Smuzhiyun sku_info->soc_process_id = i;
99*4882a593Smuzhiyun }
100