1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2010 Google, Inc. 4*4882a593Smuzhiyun * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Author: 7*4882a593Smuzhiyun * Colin Cross <ccross@android.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __DRIVERS_MISC_TEGRA_FUSE_H 11*4882a593Smuzhiyun #define __DRIVERS_MISC_TEGRA_FUSE_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/dmaengine.h> 14*4882a593Smuzhiyun #include <linux/types.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun struct nvmem_cell_lookup; 17*4882a593Smuzhiyun struct nvmem_device; 18*4882a593Smuzhiyun struct tegra_fuse; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun struct tegra_fuse_info { 21*4882a593Smuzhiyun u32 (*read)(struct tegra_fuse *fuse, unsigned int offset); 22*4882a593Smuzhiyun unsigned int size; 23*4882a593Smuzhiyun unsigned int spare; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun struct tegra_fuse_soc { 27*4882a593Smuzhiyun void (*init)(struct tegra_fuse *fuse); 28*4882a593Smuzhiyun void (*speedo_init)(struct tegra_sku_info *info); 29*4882a593Smuzhiyun int (*probe)(struct tegra_fuse *fuse); 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun const struct tegra_fuse_info *info; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun const struct nvmem_cell_lookup *lookups; 34*4882a593Smuzhiyun unsigned int num_lookups; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun const struct attribute_group *soc_attr_group; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun struct tegra_fuse { 40*4882a593Smuzhiyun struct device *dev; 41*4882a593Smuzhiyun void __iomem *base; 42*4882a593Smuzhiyun phys_addr_t phys; 43*4882a593Smuzhiyun struct clk *clk; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun u32 (*read_early)(struct tegra_fuse *fuse, unsigned int offset); 46*4882a593Smuzhiyun u32 (*read)(struct tegra_fuse *fuse, unsigned int offset); 47*4882a593Smuzhiyun const struct tegra_fuse_soc *soc; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* APBDMA on Tegra20 */ 50*4882a593Smuzhiyun struct { 51*4882a593Smuzhiyun struct mutex lock; 52*4882a593Smuzhiyun struct completion wait; 53*4882a593Smuzhiyun struct dma_chan *chan; 54*4882a593Smuzhiyun struct dma_slave_config config; 55*4882a593Smuzhiyun dma_addr_t phys; 56*4882a593Smuzhiyun u32 *virt; 57*4882a593Smuzhiyun } apbdma; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun struct nvmem_device *nvmem; 60*4882a593Smuzhiyun struct nvmem_cell_lookup *lookups; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun void tegra_init_revision(void); 64*4882a593Smuzhiyun void tegra_init_apbmisc(void); 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun u32 __init tegra_fuse_read_spare(unsigned int spare); 67*4882a593Smuzhiyun u32 __init tegra_fuse_read_early(unsigned int offset); 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun u8 tegra_get_major_rev(void); 70*4882a593Smuzhiyun u8 tegra_get_minor_rev(void); 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun extern const struct attribute_group tegra_soc_attr_group; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #ifdef CONFIG_ARCH_TEGRA_2x_SOC 75*4882a593Smuzhiyun void tegra20_init_speedo_data(struct tegra_sku_info *sku_info); 76*4882a593Smuzhiyun #endif 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #ifdef CONFIG_ARCH_TEGRA_3x_SOC 79*4882a593Smuzhiyun void tegra30_init_speedo_data(struct tegra_sku_info *sku_info); 80*4882a593Smuzhiyun #endif 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #ifdef CONFIG_ARCH_TEGRA_114_SOC 83*4882a593Smuzhiyun void tegra114_init_speedo_data(struct tegra_sku_info *sku_info); 84*4882a593Smuzhiyun #endif 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) 87*4882a593Smuzhiyun void tegra124_init_speedo_data(struct tegra_sku_info *sku_info); 88*4882a593Smuzhiyun #endif 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #ifdef CONFIG_ARCH_TEGRA_210_SOC 91*4882a593Smuzhiyun void tegra210_init_speedo_data(struct tegra_sku_info *sku_info); 92*4882a593Smuzhiyun #endif 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #ifdef CONFIG_ARCH_TEGRA_2x_SOC 95*4882a593Smuzhiyun extern const struct tegra_fuse_soc tegra20_fuse_soc; 96*4882a593Smuzhiyun #endif 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #ifdef CONFIG_ARCH_TEGRA_3x_SOC 99*4882a593Smuzhiyun extern const struct tegra_fuse_soc tegra30_fuse_soc; 100*4882a593Smuzhiyun #endif 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #ifdef CONFIG_ARCH_TEGRA_114_SOC 103*4882a593Smuzhiyun extern const struct tegra_fuse_soc tegra114_fuse_soc; 104*4882a593Smuzhiyun #endif 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) 107*4882a593Smuzhiyun extern const struct tegra_fuse_soc tegra124_fuse_soc; 108*4882a593Smuzhiyun #endif 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #ifdef CONFIG_ARCH_TEGRA_210_SOC 111*4882a593Smuzhiyun extern const struct tegra_fuse_soc tegra210_fuse_soc; 112*4882a593Smuzhiyun #endif 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #ifdef CONFIG_ARCH_TEGRA_186_SOC 115*4882a593Smuzhiyun extern const struct tegra_fuse_soc tegra186_fuse_soc; 116*4882a593Smuzhiyun #endif 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \ 119*4882a593Smuzhiyun IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) 120*4882a593Smuzhiyun extern const struct attribute_group tegra194_soc_attr_group; 121*4882a593Smuzhiyun #endif 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #ifdef CONFIG_ARCH_TEGRA_194_SOC 124*4882a593Smuzhiyun extern const struct tegra_fuse_soc tegra194_fuse_soc; 125*4882a593Smuzhiyun #endif 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #ifdef CONFIG_ARCH_TEGRA_234_SOC 128*4882a593Smuzhiyun extern const struct tegra_fuse_soc tegra234_fuse_soc; 129*4882a593Smuzhiyun #endif 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #endif 132