1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2019 Samsung Electronics Co., Ltd.
4*4882a593Smuzhiyun * http://www.samsung.com/
5*4882a593Smuzhiyun * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Samsung Exynos SoC Adaptive Supply Voltage support
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/cpu.h>
11*4882a593Smuzhiyun #include <linux/device.h>
12*4882a593Smuzhiyun #include <linux/errno.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/of.h>
17*4882a593Smuzhiyun #include <linux/of_device.h>
18*4882a593Smuzhiyun #include <linux/platform_device.h>
19*4882a593Smuzhiyun #include <linux/pm_opp.h>
20*4882a593Smuzhiyun #include <linux/regmap.h>
21*4882a593Smuzhiyun #include <linux/soc/samsung/exynos-chipid.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include "exynos-asv.h"
24*4882a593Smuzhiyun #include "exynos5422-asv.h"
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define MHZ 1000000U
27*4882a593Smuzhiyun
exynos_asv_update_cpu_opps(struct exynos_asv * asv,struct device * cpu)28*4882a593Smuzhiyun static int exynos_asv_update_cpu_opps(struct exynos_asv *asv,
29*4882a593Smuzhiyun struct device *cpu)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun struct exynos_asv_subsys *subsys = NULL;
32*4882a593Smuzhiyun struct dev_pm_opp *opp;
33*4882a593Smuzhiyun unsigned int opp_freq;
34*4882a593Smuzhiyun int i;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(asv->subsys); i++) {
37*4882a593Smuzhiyun if (of_device_is_compatible(cpu->of_node,
38*4882a593Smuzhiyun asv->subsys[i].cpu_dt_compat)) {
39*4882a593Smuzhiyun subsys = &asv->subsys[i];
40*4882a593Smuzhiyun break;
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun if (!subsys)
44*4882a593Smuzhiyun return -EINVAL;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun for (i = 0; i < subsys->table.num_rows; i++) {
47*4882a593Smuzhiyun unsigned int new_volt, volt;
48*4882a593Smuzhiyun int ret;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun opp_freq = exynos_asv_opp_get_frequency(subsys, i);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun opp = dev_pm_opp_find_freq_exact(cpu, opp_freq * MHZ, true);
53*4882a593Smuzhiyun if (IS_ERR(opp)) {
54*4882a593Smuzhiyun dev_info(asv->dev, "cpu%d opp%d, freq: %u missing\n",
55*4882a593Smuzhiyun cpu->id, i, opp_freq);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun continue;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun volt = dev_pm_opp_get_voltage(opp);
61*4882a593Smuzhiyun new_volt = asv->opp_get_voltage(subsys, i, volt);
62*4882a593Smuzhiyun dev_pm_opp_put(opp);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun if (new_volt == volt)
65*4882a593Smuzhiyun continue;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun ret = dev_pm_opp_adjust_voltage(cpu, opp_freq * MHZ,
68*4882a593Smuzhiyun new_volt, new_volt, new_volt);
69*4882a593Smuzhiyun if (ret < 0)
70*4882a593Smuzhiyun dev_err(asv->dev,
71*4882a593Smuzhiyun "Failed to adjust OPP %u Hz/%u uV for cpu%d\n",
72*4882a593Smuzhiyun opp_freq, new_volt, cpu->id);
73*4882a593Smuzhiyun else
74*4882a593Smuzhiyun dev_dbg(asv->dev,
75*4882a593Smuzhiyun "Adjusted OPP %u Hz/%u -> %u uV, cpu%d\n",
76*4882a593Smuzhiyun opp_freq, volt, new_volt, cpu->id);
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun return 0;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
exynos_asv_update_opps(struct exynos_asv * asv)82*4882a593Smuzhiyun static int exynos_asv_update_opps(struct exynos_asv *asv)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun struct opp_table *last_opp_table = NULL;
85*4882a593Smuzhiyun struct device *cpu;
86*4882a593Smuzhiyun int ret, cpuid;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun for_each_possible_cpu(cpuid) {
89*4882a593Smuzhiyun struct opp_table *opp_table;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun cpu = get_cpu_device(cpuid);
92*4882a593Smuzhiyun if (!cpu)
93*4882a593Smuzhiyun continue;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun opp_table = dev_pm_opp_get_opp_table(cpu);
96*4882a593Smuzhiyun if (IS_ERR(opp_table))
97*4882a593Smuzhiyun continue;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun if (!last_opp_table || opp_table != last_opp_table) {
100*4882a593Smuzhiyun last_opp_table = opp_table;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun ret = exynos_asv_update_cpu_opps(asv, cpu);
103*4882a593Smuzhiyun if (ret < 0)
104*4882a593Smuzhiyun dev_err(asv->dev, "Couldn't udate OPPs for cpu%d\n",
105*4882a593Smuzhiyun cpuid);
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun dev_pm_opp_put_opp_table(opp_table);
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun return 0;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
exynos_asv_probe(struct platform_device * pdev)114*4882a593Smuzhiyun static int exynos_asv_probe(struct platform_device *pdev)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun int (*probe_func)(struct exynos_asv *asv);
117*4882a593Smuzhiyun struct exynos_asv *asv;
118*4882a593Smuzhiyun struct device *cpu_dev;
119*4882a593Smuzhiyun u32 product_id = 0;
120*4882a593Smuzhiyun int ret, i;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun asv = devm_kzalloc(&pdev->dev, sizeof(*asv), GFP_KERNEL);
123*4882a593Smuzhiyun if (!asv)
124*4882a593Smuzhiyun return -ENOMEM;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun asv->chipid_regmap = device_node_to_regmap(pdev->dev.of_node);
127*4882a593Smuzhiyun if (IS_ERR(asv->chipid_regmap)) {
128*4882a593Smuzhiyun dev_err(&pdev->dev, "Could not find syscon regmap\n");
129*4882a593Smuzhiyun return PTR_ERR(asv->chipid_regmap);
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun ret = regmap_read(asv->chipid_regmap, EXYNOS_CHIPID_REG_PRO_ID,
133*4882a593Smuzhiyun &product_id);
134*4882a593Smuzhiyun if (ret < 0) {
135*4882a593Smuzhiyun dev_err(&pdev->dev, "Cannot read revision from ChipID: %d\n",
136*4882a593Smuzhiyun ret);
137*4882a593Smuzhiyun return -ENODEV;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun switch (product_id & EXYNOS_MASK) {
141*4882a593Smuzhiyun case 0xE5422000:
142*4882a593Smuzhiyun probe_func = exynos5422_asv_init;
143*4882a593Smuzhiyun break;
144*4882a593Smuzhiyun default:
145*4882a593Smuzhiyun return -ENODEV;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun cpu_dev = get_cpu_device(0);
149*4882a593Smuzhiyun ret = dev_pm_opp_get_opp_count(cpu_dev);
150*4882a593Smuzhiyun if (ret < 0)
151*4882a593Smuzhiyun return -EPROBE_DEFER;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun ret = of_property_read_u32(pdev->dev.of_node, "samsung,asv-bin",
154*4882a593Smuzhiyun &asv->of_bin);
155*4882a593Smuzhiyun if (ret < 0)
156*4882a593Smuzhiyun asv->of_bin = -EINVAL;
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun asv->dev = &pdev->dev;
159*4882a593Smuzhiyun dev_set_drvdata(&pdev->dev, asv);
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(asv->subsys); i++)
162*4882a593Smuzhiyun asv->subsys[i].asv = asv;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun ret = probe_func(asv);
165*4882a593Smuzhiyun if (ret < 0)
166*4882a593Smuzhiyun return ret;
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun return exynos_asv_update_opps(asv);
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun static const struct of_device_id exynos_asv_of_device_ids[] = {
172*4882a593Smuzhiyun { .compatible = "samsung,exynos4210-chipid" },
173*4882a593Smuzhiyun {}
174*4882a593Smuzhiyun };
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun static struct platform_driver exynos_asv_driver = {
177*4882a593Smuzhiyun .driver = {
178*4882a593Smuzhiyun .name = "exynos-asv",
179*4882a593Smuzhiyun .of_match_table = exynos_asv_of_device_ids,
180*4882a593Smuzhiyun },
181*4882a593Smuzhiyun .probe = exynos_asv_probe,
182*4882a593Smuzhiyun };
183*4882a593Smuzhiyun module_platform_driver(exynos_asv_driver);
184