1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Rockchip IO Voltage Domain driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2014 MundoReader S.L.
6*4882a593Smuzhiyun * Copyright 2014 Google, Inc.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/err.h>
12*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
13*4882a593Smuzhiyun #include <linux/of.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/regmap.h>
16*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
17*4882a593Smuzhiyun #include <linux/of.h>
18*4882a593Smuzhiyun #include <linux/of_device.h>
19*4882a593Smuzhiyun #include <linux/regulator/of_regulator.h>
20*4882a593Smuzhiyun #include <linux/regulator/driver.h>
21*4882a593Smuzhiyun #include <linux/regulator/machine.h>
22*4882a593Smuzhiyun #include <linux/rockchip/cpu.h>
23*4882a593Smuzhiyun #include "../../regulator/internal.h"
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define MAX_SUPPLIES 16
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /*
28*4882a593Smuzhiyun * The max voltage for 1.8V and 3.3V come from the Rockchip datasheet under
29*4882a593Smuzhiyun * "Recommended Operating Conditions" for "Digital GPIO". When the typical
30*4882a593Smuzhiyun * is 3.3V the max is 3.6V. When the typical is 1.8V the max is 1.98V.
31*4882a593Smuzhiyun *
32*4882a593Smuzhiyun * They are used like this:
33*4882a593Smuzhiyun * - If the voltage on a rail is above the "1.8" voltage (1.98V) we'll tell the
34*4882a593Smuzhiyun * SoC we're at 3.3.
35*4882a593Smuzhiyun * - If the voltage on a rail is above the "3.3" voltage (3.6V) we'll consider
36*4882a593Smuzhiyun * that to be an error.
37*4882a593Smuzhiyun */
38*4882a593Smuzhiyun #define MAX_VOLTAGE_1_8 1980000
39*4882a593Smuzhiyun #define MAX_VOLTAGE_3_3 3600000
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #define PX30_IO_VSEL 0x180
42*4882a593Smuzhiyun #define PX30_IO_VSEL_VCCIO6_SRC BIT(0)
43*4882a593Smuzhiyun #define PX30_IO_VSEL_VCCIO6_SUPPLY_NUM 1
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #define RK3288_SOC_CON2 0x24c
46*4882a593Smuzhiyun #define RK3288_SOC_CON2_FLASH0 BIT(7)
47*4882a593Smuzhiyun #define RK3288_SOC_FLASH_SUPPLY_NUM 2
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #define RK3308_SOC_CON0 0x300
50*4882a593Smuzhiyun #define RK3308_SOC_CON0_VCCIO3 BIT(8)
51*4882a593Smuzhiyun #define RK3308_SOC_VCCIO3_SUPPLY_NUM 3
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #define RK3328_SOC_CON4 0x410
54*4882a593Smuzhiyun #define RK3328_SOC_CON4_VCCIO2 BIT(7)
55*4882a593Smuzhiyun #define RK3328_SOC_VCCIO2_SUPPLY_NUM 1
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #define RK3368_SOC_CON15 0x43c
58*4882a593Smuzhiyun #define RK3368_SOC_CON15_FLASH0 BIT(14)
59*4882a593Smuzhiyun #define RK3368_SOC_FLASH_SUPPLY_NUM 2
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun #define RK3399_PMUGRF_CON0 0x180
62*4882a593Smuzhiyun #define RK3399_PMUGRF_CON0_VSEL BIT(8)
63*4882a593Smuzhiyun #define RK3399_PMUGRF_VSEL_SUPPLY_NUM 9
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun #define RK3568_PMU_GRF_IO_VSEL0 (0x0140)
66*4882a593Smuzhiyun #define RK3568_PMU_GRF_IO_VSEL1 (0x0144)
67*4882a593Smuzhiyun #define RK3568_PMU_GRF_IO_VSEL2 (0x0148)
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun struct rockchip_iodomain;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun struct rockchip_iodomain_supply {
72*4882a593Smuzhiyun struct rockchip_iodomain *iod;
73*4882a593Smuzhiyun struct regulator *reg;
74*4882a593Smuzhiyun struct notifier_block nb;
75*4882a593Smuzhiyun int idx;
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun struct rockchip_iodomain_soc_data {
79*4882a593Smuzhiyun int grf_offset;
80*4882a593Smuzhiyun const char *supply_names[MAX_SUPPLIES];
81*4882a593Smuzhiyun void (*init)(struct rockchip_iodomain *iod);
82*4882a593Smuzhiyun int (*write)(struct rockchip_iodomain_supply *supply, int uV);
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun struct rockchip_iodomain {
86*4882a593Smuzhiyun struct device *dev;
87*4882a593Smuzhiyun struct regmap *grf;
88*4882a593Smuzhiyun const struct rockchip_iodomain_soc_data *soc_data;
89*4882a593Smuzhiyun struct rockchip_iodomain_supply supplies[MAX_SUPPLIES];
90*4882a593Smuzhiyun int (*write)(struct rockchip_iodomain_supply *supply, int uV);
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun
rk3568_iodomain_write(struct rockchip_iodomain_supply * supply,int uV)93*4882a593Smuzhiyun static int rk3568_iodomain_write(struct rockchip_iodomain_supply *supply, int uV)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun struct rockchip_iodomain *iod = supply->iod;
96*4882a593Smuzhiyun u32 is_3v3 = uV > MAX_VOLTAGE_1_8;
97*4882a593Smuzhiyun u32 val0, val1;
98*4882a593Smuzhiyun int b;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun switch (supply->idx) {
101*4882a593Smuzhiyun case 0: /* pmuio1 */
102*4882a593Smuzhiyun break;
103*4882a593Smuzhiyun case 1: /* pmuio2 */
104*4882a593Smuzhiyun b = supply->idx;
105*4882a593Smuzhiyun val0 = BIT(16 + b) | (is_3v3 ? 0 : BIT(b));
106*4882a593Smuzhiyun b = supply->idx + 4;
107*4882a593Smuzhiyun val1 = BIT(16 + b) | (is_3v3 ? BIT(b) : 0);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL2, val0);
110*4882a593Smuzhiyun regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL2, val1);
111*4882a593Smuzhiyun break;
112*4882a593Smuzhiyun case 3: /* vccio2 */
113*4882a593Smuzhiyun break;
114*4882a593Smuzhiyun case 2: /* vccio1 */
115*4882a593Smuzhiyun case 4: /* vccio3 */
116*4882a593Smuzhiyun case 5: /* vccio4 */
117*4882a593Smuzhiyun case 6: /* vccio5 */
118*4882a593Smuzhiyun case 7: /* vccio6 */
119*4882a593Smuzhiyun case 8: /* vccio7 */
120*4882a593Smuzhiyun b = supply->idx - 1;
121*4882a593Smuzhiyun val0 = BIT(16 + b) | (is_3v3 ? 0 : BIT(b));
122*4882a593Smuzhiyun val1 = BIT(16 + b) | (is_3v3 ? BIT(b) : 0);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL0, val0);
125*4882a593Smuzhiyun regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL1, val1);
126*4882a593Smuzhiyun break;
127*4882a593Smuzhiyun default:
128*4882a593Smuzhiyun return -EINVAL;
129*4882a593Smuzhiyun };
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun return 0;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
rockchip_iodomain_write(struct rockchip_iodomain_supply * supply,int uV)134*4882a593Smuzhiyun static int rockchip_iodomain_write(struct rockchip_iodomain_supply *supply,
135*4882a593Smuzhiyun int uV)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun struct rockchip_iodomain *iod = supply->iod;
138*4882a593Smuzhiyun u32 val;
139*4882a593Smuzhiyun int ret;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun /* set value bit */
142*4882a593Smuzhiyun val = (uV > MAX_VOLTAGE_1_8) ? 0 : 1;
143*4882a593Smuzhiyun val <<= supply->idx;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun /* apply hiword-mask */
146*4882a593Smuzhiyun val |= (BIT(supply->idx) << 16);
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun ret = regmap_write(iod->grf, iod->soc_data->grf_offset, val);
149*4882a593Smuzhiyun if (ret)
150*4882a593Smuzhiyun dev_err(iod->dev, "Couldn't write to GRF\n");
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun return ret;
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun
rockchip_iodomain_notify(struct notifier_block * nb,unsigned long event,void * data)155*4882a593Smuzhiyun static int rockchip_iodomain_notify(struct notifier_block *nb,
156*4882a593Smuzhiyun unsigned long event,
157*4882a593Smuzhiyun void *data)
158*4882a593Smuzhiyun {
159*4882a593Smuzhiyun struct rockchip_iodomain_supply *supply =
160*4882a593Smuzhiyun container_of(nb, struct rockchip_iodomain_supply, nb);
161*4882a593Smuzhiyun int uV;
162*4882a593Smuzhiyun int ret;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun /*
165*4882a593Smuzhiyun * According to Rockchip it's important to keep the SoC IO domain
166*4882a593Smuzhiyun * higher than (or equal to) the external voltage. That means we need
167*4882a593Smuzhiyun * to change it before external voltage changes happen in the case
168*4882a593Smuzhiyun * of an increase.
169*4882a593Smuzhiyun *
170*4882a593Smuzhiyun * Note that in the "pre" change we pick the max possible voltage that
171*4882a593Smuzhiyun * the regulator might end up at (the client requests a range and we
172*4882a593Smuzhiyun * don't know for certain the exact voltage). Right now we rely on the
173*4882a593Smuzhiyun * slop in MAX_VOLTAGE_1_8 and MAX_VOLTAGE_3_3 to save us if clients
174*4882a593Smuzhiyun * request something like a max of 3.6V when they really want 3.3V.
175*4882a593Smuzhiyun * We could attempt to come up with better rules if this fails.
176*4882a593Smuzhiyun */
177*4882a593Smuzhiyun if (event & REGULATOR_EVENT_PRE_VOLTAGE_CHANGE) {
178*4882a593Smuzhiyun struct pre_voltage_change_data *pvc_data = data;
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun uV = max_t(unsigned long, pvc_data->old_uV, pvc_data->max_uV);
181*4882a593Smuzhiyun } else if (event & (REGULATOR_EVENT_VOLTAGE_CHANGE |
182*4882a593Smuzhiyun REGULATOR_EVENT_ABORT_VOLTAGE_CHANGE)) {
183*4882a593Smuzhiyun uV = (unsigned long)data;
184*4882a593Smuzhiyun } else {
185*4882a593Smuzhiyun return NOTIFY_OK;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun dev_dbg(supply->iod->dev, "Setting to %d\n", uV);
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun if (uV > MAX_VOLTAGE_3_3) {
191*4882a593Smuzhiyun dev_err(supply->iod->dev, "Voltage too high: %d\n", uV);
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun if (event == REGULATOR_EVENT_PRE_VOLTAGE_CHANGE)
194*4882a593Smuzhiyun return NOTIFY_BAD;
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun ret = supply->iod->write(supply, uV);
198*4882a593Smuzhiyun if (ret && event == REGULATOR_EVENT_PRE_VOLTAGE_CHANGE)
199*4882a593Smuzhiyun return NOTIFY_BAD;
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun dev_dbg(supply->iod->dev, "Setting to %d done\n", uV);
202*4882a593Smuzhiyun return NOTIFY_OK;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun
px30_iodomain_init(struct rockchip_iodomain * iod)205*4882a593Smuzhiyun static void px30_iodomain_init(struct rockchip_iodomain *iod)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun int ret;
208*4882a593Smuzhiyun u32 val;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun /* if no VCCIO6 supply we should leave things alone */
211*4882a593Smuzhiyun if (!iod->supplies[PX30_IO_VSEL_VCCIO6_SUPPLY_NUM].reg)
212*4882a593Smuzhiyun return;
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun /*
215*4882a593Smuzhiyun * set vccio6 iodomain to also use this framework
216*4882a593Smuzhiyun * instead of a special gpio.
217*4882a593Smuzhiyun */
218*4882a593Smuzhiyun val = PX30_IO_VSEL_VCCIO6_SRC | (PX30_IO_VSEL_VCCIO6_SRC << 16);
219*4882a593Smuzhiyun ret = regmap_write(iod->grf, PX30_IO_VSEL, val);
220*4882a593Smuzhiyun if (ret < 0)
221*4882a593Smuzhiyun dev_warn(iod->dev, "couldn't update vccio6 ctrl\n");
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun
rk3288_iodomain_init(struct rockchip_iodomain * iod)224*4882a593Smuzhiyun static void rk3288_iodomain_init(struct rockchip_iodomain *iod)
225*4882a593Smuzhiyun {
226*4882a593Smuzhiyun int ret;
227*4882a593Smuzhiyun u32 val;
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun /* if no flash supply we should leave things alone */
230*4882a593Smuzhiyun if (!iod->supplies[RK3288_SOC_FLASH_SUPPLY_NUM].reg)
231*4882a593Smuzhiyun return;
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun /*
234*4882a593Smuzhiyun * set flash0 iodomain to also use this framework
235*4882a593Smuzhiyun * instead of a special gpio.
236*4882a593Smuzhiyun */
237*4882a593Smuzhiyun val = RK3288_SOC_CON2_FLASH0 | (RK3288_SOC_CON2_FLASH0 << 16);
238*4882a593Smuzhiyun ret = regmap_write(iod->grf, RK3288_SOC_CON2, val);
239*4882a593Smuzhiyun if (ret < 0)
240*4882a593Smuzhiyun dev_warn(iod->dev, "couldn't update flash0 ctrl\n");
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun
rk3308_iodomain_init(struct rockchip_iodomain * iod)243*4882a593Smuzhiyun static void rk3308_iodomain_init(struct rockchip_iodomain *iod)
244*4882a593Smuzhiyun {
245*4882a593Smuzhiyun int ret;
246*4882a593Smuzhiyun u32 val;
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun /* if no vccio3 supply we should leave things alone */
249*4882a593Smuzhiyun if (!iod->supplies[RK3308_SOC_VCCIO3_SUPPLY_NUM].reg)
250*4882a593Smuzhiyun return;
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun /*
253*4882a593Smuzhiyun * set vccio3 iodomain to also use this framework
254*4882a593Smuzhiyun * instead of a special gpio.
255*4882a593Smuzhiyun */
256*4882a593Smuzhiyun val = RK3308_SOC_CON0_VCCIO3 | (RK3308_SOC_CON0_VCCIO3 << 16);
257*4882a593Smuzhiyun ret = regmap_write(iod->grf, RK3308_SOC_CON0, val);
258*4882a593Smuzhiyun if (ret < 0)
259*4882a593Smuzhiyun dev_warn(iod->dev, "couldn't update vccio3 vsel ctrl\n");
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun
rk3328_iodomain_init(struct rockchip_iodomain * iod)262*4882a593Smuzhiyun static void rk3328_iodomain_init(struct rockchip_iodomain *iod)
263*4882a593Smuzhiyun {
264*4882a593Smuzhiyun int ret;
265*4882a593Smuzhiyun u32 val;
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun /* if no vccio2 supply we should leave things alone */
268*4882a593Smuzhiyun if (!iod->supplies[RK3328_SOC_VCCIO2_SUPPLY_NUM].reg)
269*4882a593Smuzhiyun return;
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun /*
272*4882a593Smuzhiyun * set vccio2 iodomain to also use this framework
273*4882a593Smuzhiyun * instead of a special gpio.
274*4882a593Smuzhiyun */
275*4882a593Smuzhiyun val = RK3328_SOC_CON4_VCCIO2 | (RK3328_SOC_CON4_VCCIO2 << 16);
276*4882a593Smuzhiyun ret = regmap_write(iod->grf, RK3328_SOC_CON4, val);
277*4882a593Smuzhiyun if (ret < 0)
278*4882a593Smuzhiyun dev_warn(iod->dev, "couldn't update vccio2 vsel ctrl\n");
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun
rk3368_iodomain_init(struct rockchip_iodomain * iod)281*4882a593Smuzhiyun static void rk3368_iodomain_init(struct rockchip_iodomain *iod)
282*4882a593Smuzhiyun {
283*4882a593Smuzhiyun int ret;
284*4882a593Smuzhiyun u32 val;
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun /* if no flash supply we should leave things alone */
287*4882a593Smuzhiyun if (!iod->supplies[RK3368_SOC_FLASH_SUPPLY_NUM].reg)
288*4882a593Smuzhiyun return;
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun /*
291*4882a593Smuzhiyun * set flash0 iodomain to also use this framework
292*4882a593Smuzhiyun * instead of a special gpio.
293*4882a593Smuzhiyun */
294*4882a593Smuzhiyun val = RK3368_SOC_CON15_FLASH0 | (RK3368_SOC_CON15_FLASH0 << 16);
295*4882a593Smuzhiyun ret = regmap_write(iod->grf, RK3368_SOC_CON15, val);
296*4882a593Smuzhiyun if (ret < 0)
297*4882a593Smuzhiyun dev_warn(iod->dev, "couldn't update flash0 ctrl\n");
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun
rk3399_pmu_iodomain_init(struct rockchip_iodomain * iod)300*4882a593Smuzhiyun static void rk3399_pmu_iodomain_init(struct rockchip_iodomain *iod)
301*4882a593Smuzhiyun {
302*4882a593Smuzhiyun int ret;
303*4882a593Smuzhiyun u32 val;
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun /* if no pmu io supply we should leave things alone */
306*4882a593Smuzhiyun if (!iod->supplies[RK3399_PMUGRF_VSEL_SUPPLY_NUM].reg)
307*4882a593Smuzhiyun return;
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun /*
310*4882a593Smuzhiyun * set pmu io iodomain to also use this framework
311*4882a593Smuzhiyun * instead of a special gpio.
312*4882a593Smuzhiyun */
313*4882a593Smuzhiyun val = RK3399_PMUGRF_CON0_VSEL | (RK3399_PMUGRF_CON0_VSEL << 16);
314*4882a593Smuzhiyun ret = regmap_write(iod->grf, RK3399_PMUGRF_CON0, val);
315*4882a593Smuzhiyun if (ret < 0)
316*4882a593Smuzhiyun dev_warn(iod->dev, "couldn't update pmu io iodomain ctrl\n");
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun static const struct rockchip_iodomain_soc_data soc_data_px30 = {
320*4882a593Smuzhiyun .grf_offset = 0x180,
321*4882a593Smuzhiyun .supply_names = {
322*4882a593Smuzhiyun NULL,
323*4882a593Smuzhiyun "vccio6",
324*4882a593Smuzhiyun "vccio1",
325*4882a593Smuzhiyun "vccio2",
326*4882a593Smuzhiyun "vccio3",
327*4882a593Smuzhiyun "vccio4",
328*4882a593Smuzhiyun "vccio5",
329*4882a593Smuzhiyun "vccio-oscgpi",
330*4882a593Smuzhiyun },
331*4882a593Smuzhiyun .init = px30_iodomain_init,
332*4882a593Smuzhiyun };
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun static const struct rockchip_iodomain_soc_data soc_data_px30_pmu = {
335*4882a593Smuzhiyun .grf_offset = 0x100,
336*4882a593Smuzhiyun .supply_names = {
337*4882a593Smuzhiyun NULL,
338*4882a593Smuzhiyun NULL,
339*4882a593Smuzhiyun NULL,
340*4882a593Smuzhiyun NULL,
341*4882a593Smuzhiyun NULL,
342*4882a593Smuzhiyun NULL,
343*4882a593Smuzhiyun NULL,
344*4882a593Smuzhiyun NULL,
345*4882a593Smuzhiyun NULL,
346*4882a593Smuzhiyun NULL,
347*4882a593Smuzhiyun NULL,
348*4882a593Smuzhiyun NULL,
349*4882a593Smuzhiyun NULL,
350*4882a593Smuzhiyun NULL,
351*4882a593Smuzhiyun "pmuio1",
352*4882a593Smuzhiyun "pmuio2",
353*4882a593Smuzhiyun },
354*4882a593Smuzhiyun };
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun /*
357*4882a593Smuzhiyun * On the rk3188 the io-domains are handled by a shared register with the
358*4882a593Smuzhiyun * lower 8 bits being still being continuing drive-strength settings.
359*4882a593Smuzhiyun */
360*4882a593Smuzhiyun static const struct rockchip_iodomain_soc_data soc_data_rk3188 = {
361*4882a593Smuzhiyun .grf_offset = 0x104,
362*4882a593Smuzhiyun .supply_names = {
363*4882a593Smuzhiyun NULL,
364*4882a593Smuzhiyun NULL,
365*4882a593Smuzhiyun NULL,
366*4882a593Smuzhiyun NULL,
367*4882a593Smuzhiyun NULL,
368*4882a593Smuzhiyun NULL,
369*4882a593Smuzhiyun NULL,
370*4882a593Smuzhiyun NULL,
371*4882a593Smuzhiyun "ap0",
372*4882a593Smuzhiyun "ap1",
373*4882a593Smuzhiyun "cif",
374*4882a593Smuzhiyun "flash",
375*4882a593Smuzhiyun "vccio0",
376*4882a593Smuzhiyun "vccio1",
377*4882a593Smuzhiyun "lcdc0",
378*4882a593Smuzhiyun "lcdc1",
379*4882a593Smuzhiyun },
380*4882a593Smuzhiyun };
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun static const struct rockchip_iodomain_soc_data soc_data_rk3228 = {
383*4882a593Smuzhiyun .grf_offset = 0x418,
384*4882a593Smuzhiyun .supply_names = {
385*4882a593Smuzhiyun "vccio1",
386*4882a593Smuzhiyun "vccio2",
387*4882a593Smuzhiyun "vccio3",
388*4882a593Smuzhiyun "vccio4",
389*4882a593Smuzhiyun },
390*4882a593Smuzhiyun };
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun static const struct rockchip_iodomain_soc_data soc_data_rk3288 = {
393*4882a593Smuzhiyun .grf_offset = 0x380,
394*4882a593Smuzhiyun .supply_names = {
395*4882a593Smuzhiyun "lcdc", /* LCDC_VDD */
396*4882a593Smuzhiyun "dvp", /* DVPIO_VDD */
397*4882a593Smuzhiyun "flash0", /* FLASH0_VDD (emmc) */
398*4882a593Smuzhiyun "flash1", /* FLASH1_VDD (sdio1) */
399*4882a593Smuzhiyun "wifi", /* APIO3_VDD (sdio0) */
400*4882a593Smuzhiyun "bb", /* APIO5_VDD */
401*4882a593Smuzhiyun "audio", /* APIO4_VDD */
402*4882a593Smuzhiyun "sdcard", /* SDMMC0_VDD (sdmmc) */
403*4882a593Smuzhiyun "gpio30", /* APIO1_VDD */
404*4882a593Smuzhiyun "gpio1830", /* APIO2_VDD */
405*4882a593Smuzhiyun },
406*4882a593Smuzhiyun .init = rk3288_iodomain_init,
407*4882a593Smuzhiyun };
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun static const struct rockchip_iodomain_soc_data soc_data_rk3308 = {
410*4882a593Smuzhiyun .grf_offset = 0x300,
411*4882a593Smuzhiyun .supply_names = {
412*4882a593Smuzhiyun "vccio0",
413*4882a593Smuzhiyun "vccio1",
414*4882a593Smuzhiyun "vccio2",
415*4882a593Smuzhiyun "vccio3",
416*4882a593Smuzhiyun "vccio4",
417*4882a593Smuzhiyun "vccio5",
418*4882a593Smuzhiyun },
419*4882a593Smuzhiyun .init = rk3308_iodomain_init,
420*4882a593Smuzhiyun };
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun static const struct rockchip_iodomain_soc_data soc_data_rk3328 = {
423*4882a593Smuzhiyun .grf_offset = 0x410,
424*4882a593Smuzhiyun .supply_names = {
425*4882a593Smuzhiyun "vccio1",
426*4882a593Smuzhiyun "vccio2",
427*4882a593Smuzhiyun "vccio3",
428*4882a593Smuzhiyun "vccio4",
429*4882a593Smuzhiyun "vccio5",
430*4882a593Smuzhiyun "vccio6",
431*4882a593Smuzhiyun "pmuio",
432*4882a593Smuzhiyun },
433*4882a593Smuzhiyun .init = rk3328_iodomain_init,
434*4882a593Smuzhiyun };
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun static const struct rockchip_iodomain_soc_data soc_data_rk3368 = {
437*4882a593Smuzhiyun .grf_offset = 0x900,
438*4882a593Smuzhiyun .supply_names = {
439*4882a593Smuzhiyun NULL, /* reserved */
440*4882a593Smuzhiyun "dvp", /* DVPIO_VDD */
441*4882a593Smuzhiyun "flash0", /* FLASH0_VDD (emmc) */
442*4882a593Smuzhiyun "wifi", /* APIO2_VDD (sdio0) */
443*4882a593Smuzhiyun NULL,
444*4882a593Smuzhiyun "audio", /* APIO3_VDD */
445*4882a593Smuzhiyun "sdcard", /* SDMMC0_VDD (sdmmc) */
446*4882a593Smuzhiyun "gpio30", /* APIO1_VDD */
447*4882a593Smuzhiyun "gpio1830", /* APIO4_VDD (gpujtag) */
448*4882a593Smuzhiyun },
449*4882a593Smuzhiyun .init = rk3368_iodomain_init,
450*4882a593Smuzhiyun };
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun static const struct rockchip_iodomain_soc_data soc_data_rk3368_pmu = {
453*4882a593Smuzhiyun .grf_offset = 0x100,
454*4882a593Smuzhiyun .supply_names = {
455*4882a593Smuzhiyun NULL,
456*4882a593Smuzhiyun NULL,
457*4882a593Smuzhiyun NULL,
458*4882a593Smuzhiyun NULL,
459*4882a593Smuzhiyun "pmu", /*PMU IO domain*/
460*4882a593Smuzhiyun "vop", /*LCDC IO domain*/
461*4882a593Smuzhiyun },
462*4882a593Smuzhiyun };
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun static const struct rockchip_iodomain_soc_data soc_data_rk3399 = {
465*4882a593Smuzhiyun .grf_offset = 0xe640,
466*4882a593Smuzhiyun .supply_names = {
467*4882a593Smuzhiyun "bt656", /* APIO2_VDD */
468*4882a593Smuzhiyun "audio", /* APIO5_VDD */
469*4882a593Smuzhiyun "sdmmc", /* SDMMC0_VDD */
470*4882a593Smuzhiyun "gpio1830", /* APIO4_VDD */
471*4882a593Smuzhiyun },
472*4882a593Smuzhiyun };
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun static const struct rockchip_iodomain_soc_data soc_data_rk3399_pmu = {
475*4882a593Smuzhiyun .grf_offset = 0x180,
476*4882a593Smuzhiyun .supply_names = {
477*4882a593Smuzhiyun NULL,
478*4882a593Smuzhiyun NULL,
479*4882a593Smuzhiyun NULL,
480*4882a593Smuzhiyun NULL,
481*4882a593Smuzhiyun NULL,
482*4882a593Smuzhiyun NULL,
483*4882a593Smuzhiyun NULL,
484*4882a593Smuzhiyun NULL,
485*4882a593Smuzhiyun NULL,
486*4882a593Smuzhiyun "pmu1830", /* PMUIO2_VDD */
487*4882a593Smuzhiyun },
488*4882a593Smuzhiyun .init = rk3399_pmu_iodomain_init,
489*4882a593Smuzhiyun };
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun static const struct rockchip_iodomain_soc_data soc_data_rk3568_pmu = {
492*4882a593Smuzhiyun .grf_offset = 0x140,
493*4882a593Smuzhiyun .supply_names = {
494*4882a593Smuzhiyun "pmuio1",
495*4882a593Smuzhiyun "pmuio2",
496*4882a593Smuzhiyun "vccio1",
497*4882a593Smuzhiyun "vccio2",
498*4882a593Smuzhiyun "vccio3",
499*4882a593Smuzhiyun "vccio4",
500*4882a593Smuzhiyun "vccio5",
501*4882a593Smuzhiyun "vccio6",
502*4882a593Smuzhiyun "vccio7",
503*4882a593Smuzhiyun },
504*4882a593Smuzhiyun .write = rk3568_iodomain_write,
505*4882a593Smuzhiyun };
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun static const struct rockchip_iodomain_soc_data soc_data_rv1108 = {
508*4882a593Smuzhiyun .grf_offset = 0x404,
509*4882a593Smuzhiyun .supply_names = {
510*4882a593Smuzhiyun NULL,
511*4882a593Smuzhiyun NULL,
512*4882a593Smuzhiyun NULL,
513*4882a593Smuzhiyun NULL,
514*4882a593Smuzhiyun NULL,
515*4882a593Smuzhiyun NULL,
516*4882a593Smuzhiyun NULL,
517*4882a593Smuzhiyun NULL,
518*4882a593Smuzhiyun NULL,
519*4882a593Smuzhiyun NULL,
520*4882a593Smuzhiyun NULL,
521*4882a593Smuzhiyun "vccio1",
522*4882a593Smuzhiyun "vccio2",
523*4882a593Smuzhiyun "vccio3",
524*4882a593Smuzhiyun "vccio5",
525*4882a593Smuzhiyun "vccio6",
526*4882a593Smuzhiyun },
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun };
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun static const struct rockchip_iodomain_soc_data soc_data_rv1108_pmu = {
531*4882a593Smuzhiyun .grf_offset = 0x104,
532*4882a593Smuzhiyun .supply_names = {
533*4882a593Smuzhiyun "pmu",
534*4882a593Smuzhiyun },
535*4882a593Smuzhiyun };
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun static const struct rockchip_iodomain_soc_data soc_data_rv1126_pmu = {
538*4882a593Smuzhiyun .grf_offset = 0x140,
539*4882a593Smuzhiyun .supply_names = {
540*4882a593Smuzhiyun NULL,
541*4882a593Smuzhiyun "vccio1",
542*4882a593Smuzhiyun "vccio2",
543*4882a593Smuzhiyun "vccio3",
544*4882a593Smuzhiyun "vccio4",
545*4882a593Smuzhiyun "vccio5",
546*4882a593Smuzhiyun "vccio6",
547*4882a593Smuzhiyun "vccio7",
548*4882a593Smuzhiyun "pmuio0",
549*4882a593Smuzhiyun "pmuio1",
550*4882a593Smuzhiyun },
551*4882a593Smuzhiyun };
552*4882a593Smuzhiyun
553*4882a593Smuzhiyun static const struct of_device_id rockchip_iodomain_match[] = {
554*4882a593Smuzhiyun #ifdef CONFIG_CPU_PX30
555*4882a593Smuzhiyun {
556*4882a593Smuzhiyun .compatible = "rockchip,px30-io-voltage-domain",
557*4882a593Smuzhiyun .data = (void *)&soc_data_px30
558*4882a593Smuzhiyun },
559*4882a593Smuzhiyun {
560*4882a593Smuzhiyun .compatible = "rockchip,px30-pmu-io-voltage-domain",
561*4882a593Smuzhiyun .data = (void *)&soc_data_px30_pmu
562*4882a593Smuzhiyun },
563*4882a593Smuzhiyun #endif
564*4882a593Smuzhiyun #ifdef CONFIG_CPU_RK3188
565*4882a593Smuzhiyun {
566*4882a593Smuzhiyun .compatible = "rockchip,rk3188-io-voltage-domain",
567*4882a593Smuzhiyun .data = &soc_data_rk3188
568*4882a593Smuzhiyun },
569*4882a593Smuzhiyun #endif
570*4882a593Smuzhiyun #ifdef CONFIG_CPU_RK322X
571*4882a593Smuzhiyun {
572*4882a593Smuzhiyun .compatible = "rockchip,rk3228-io-voltage-domain",
573*4882a593Smuzhiyun .data = &soc_data_rk3228
574*4882a593Smuzhiyun },
575*4882a593Smuzhiyun #endif
576*4882a593Smuzhiyun #ifdef CONFIG_CPU_RK3288
577*4882a593Smuzhiyun {
578*4882a593Smuzhiyun .compatible = "rockchip,rk3288-io-voltage-domain",
579*4882a593Smuzhiyun .data = &soc_data_rk3288
580*4882a593Smuzhiyun },
581*4882a593Smuzhiyun #endif
582*4882a593Smuzhiyun #ifdef CONFIG_CPU_RK3308
583*4882a593Smuzhiyun {
584*4882a593Smuzhiyun .compatible = "rockchip,rk3308-io-voltage-domain",
585*4882a593Smuzhiyun .data = &soc_data_rk3308
586*4882a593Smuzhiyun },
587*4882a593Smuzhiyun #endif
588*4882a593Smuzhiyun #ifdef CONFIG_CPU_RK3328
589*4882a593Smuzhiyun {
590*4882a593Smuzhiyun .compatible = "rockchip,rk3328-io-voltage-domain",
591*4882a593Smuzhiyun .data = &soc_data_rk3328
592*4882a593Smuzhiyun },
593*4882a593Smuzhiyun #endif
594*4882a593Smuzhiyun #ifdef CONFIG_CPU_RK3368
595*4882a593Smuzhiyun {
596*4882a593Smuzhiyun .compatible = "rockchip,rk3368-io-voltage-domain",
597*4882a593Smuzhiyun .data = &soc_data_rk3368
598*4882a593Smuzhiyun },
599*4882a593Smuzhiyun {
600*4882a593Smuzhiyun .compatible = "rockchip,rk3368-pmu-io-voltage-domain",
601*4882a593Smuzhiyun .data = &soc_data_rk3368_pmu
602*4882a593Smuzhiyun },
603*4882a593Smuzhiyun #endif
604*4882a593Smuzhiyun #ifdef CONFIG_CPU_RK3399
605*4882a593Smuzhiyun {
606*4882a593Smuzhiyun .compatible = "rockchip,rk3399-io-voltage-domain",
607*4882a593Smuzhiyun .data = &soc_data_rk3399
608*4882a593Smuzhiyun },
609*4882a593Smuzhiyun {
610*4882a593Smuzhiyun .compatible = "rockchip,rk3399-pmu-io-voltage-domain",
611*4882a593Smuzhiyun .data = &soc_data_rk3399_pmu
612*4882a593Smuzhiyun },
613*4882a593Smuzhiyun #endif
614*4882a593Smuzhiyun #ifdef CONFIG_CPU_RK3568
615*4882a593Smuzhiyun {
616*4882a593Smuzhiyun .compatible = "rockchip,rk3568-pmu-io-voltage-domain",
617*4882a593Smuzhiyun .data = &soc_data_rk3568_pmu
618*4882a593Smuzhiyun },
619*4882a593Smuzhiyun #endif
620*4882a593Smuzhiyun #ifdef CONFIG_CPU_RV1108
621*4882a593Smuzhiyun {
622*4882a593Smuzhiyun .compatible = "rockchip,rv1108-io-voltage-domain",
623*4882a593Smuzhiyun .data = &soc_data_rv1108
624*4882a593Smuzhiyun },
625*4882a593Smuzhiyun {
626*4882a593Smuzhiyun .compatible = "rockchip,rv1108-pmu-io-voltage-domain",
627*4882a593Smuzhiyun .data = &soc_data_rv1108_pmu
628*4882a593Smuzhiyun },
629*4882a593Smuzhiyun #endif
630*4882a593Smuzhiyun #ifdef CONFIG_CPU_RV1126
631*4882a593Smuzhiyun {
632*4882a593Smuzhiyun .compatible = "rockchip,rv1126-pmu-io-voltage-domain",
633*4882a593Smuzhiyun .data = &soc_data_rv1126_pmu
634*4882a593Smuzhiyun },
635*4882a593Smuzhiyun #endif
636*4882a593Smuzhiyun { /* sentinel */ },
637*4882a593Smuzhiyun };
638*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, rockchip_iodomain_match);
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun #ifndef MODULE
rdev_get_name(struct regulator_dev * rdev)641*4882a593Smuzhiyun static const char *rdev_get_name(struct regulator_dev *rdev)
642*4882a593Smuzhiyun {
643*4882a593Smuzhiyun if (rdev->constraints && rdev->constraints->name)
644*4882a593Smuzhiyun return rdev->constraints->name;
645*4882a593Smuzhiyun else if (rdev->desc->name)
646*4882a593Smuzhiyun return rdev->desc->name;
647*4882a593Smuzhiyun else
648*4882a593Smuzhiyun return "";
649*4882a593Smuzhiyun }
650*4882a593Smuzhiyun
of_get_child_regulator(struct device_node * parent,const char * prop_name)651*4882a593Smuzhiyun static struct device_node *of_get_child_regulator(struct device_node *parent,
652*4882a593Smuzhiyun const char *prop_name)
653*4882a593Smuzhiyun {
654*4882a593Smuzhiyun struct device_node *regnode = NULL;
655*4882a593Smuzhiyun struct device_node *child = NULL;
656*4882a593Smuzhiyun
657*4882a593Smuzhiyun for_each_child_of_node(parent, child) {
658*4882a593Smuzhiyun regnode = of_parse_phandle(child, prop_name, 0);
659*4882a593Smuzhiyun
660*4882a593Smuzhiyun if (!regnode) {
661*4882a593Smuzhiyun regnode = of_get_child_regulator(child, prop_name);
662*4882a593Smuzhiyun if (regnode)
663*4882a593Smuzhiyun return regnode;
664*4882a593Smuzhiyun } else {
665*4882a593Smuzhiyun return regnode;
666*4882a593Smuzhiyun }
667*4882a593Smuzhiyun }
668*4882a593Smuzhiyun return NULL;
669*4882a593Smuzhiyun }
670*4882a593Smuzhiyun
of_get_regulator(struct device * dev,const char * supply)671*4882a593Smuzhiyun static struct device_node *of_get_regulator(struct device *dev, const char *supply)
672*4882a593Smuzhiyun {
673*4882a593Smuzhiyun struct device_node *regnode = NULL;
674*4882a593Smuzhiyun char prop_name[256];
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun dev_dbg(dev, "Looking up %s-supply from device tree\n", supply);
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun snprintf(prop_name, sizeof(prop_name), "%s-supply", supply);
679*4882a593Smuzhiyun regnode = of_parse_phandle(dev->of_node, prop_name, 0);
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun if (!regnode) {
682*4882a593Smuzhiyun regnode = of_get_child_regulator(dev->of_node, prop_name);
683*4882a593Smuzhiyun if (regnode)
684*4882a593Smuzhiyun return regnode;
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun dev_dbg(dev, "Looking up %s property in node %pOF failed\n",
687*4882a593Smuzhiyun prop_name, dev->of_node);
688*4882a593Smuzhiyun return NULL;
689*4882a593Smuzhiyun }
690*4882a593Smuzhiyun return regnode;
691*4882a593Smuzhiyun }
692*4882a593Smuzhiyun
rockchip_iodomain_dump(const struct platform_device * pdev,struct rockchip_iodomain_supply * supply)693*4882a593Smuzhiyun static void rockchip_iodomain_dump(const struct platform_device *pdev,
694*4882a593Smuzhiyun struct rockchip_iodomain_supply *supply)
695*4882a593Smuzhiyun {
696*4882a593Smuzhiyun struct rockchip_iodomain *iod = supply->iod;
697*4882a593Smuzhiyun const char *name = iod->soc_data->supply_names[supply->idx];
698*4882a593Smuzhiyun struct device *dev = iod->dev;
699*4882a593Smuzhiyun struct device_node *node;
700*4882a593Smuzhiyun struct regulator_dev *r = NULL;
701*4882a593Smuzhiyun
702*4882a593Smuzhiyun node = of_get_regulator(dev, name);
703*4882a593Smuzhiyun if (node) {
704*4882a593Smuzhiyun r = of_find_regulator_by_node(node);
705*4882a593Smuzhiyun if (!IS_ERR_OR_NULL(r))
706*4882a593Smuzhiyun dev_info(&pdev->dev, "%s(%d uV) supplied by %s\n",
707*4882a593Smuzhiyun name, regulator_get_voltage(supply->reg),
708*4882a593Smuzhiyun rdev_get_name(r));
709*4882a593Smuzhiyun }
710*4882a593Smuzhiyun }
711*4882a593Smuzhiyun #else
712*4882a593Smuzhiyun static inline void
rockchip_iodomain_dump(const struct platform_device * pdev,struct rockchip_iodomain_supply * supply)713*4882a593Smuzhiyun rockchip_iodomain_dump(const struct platform_device *pdev,
714*4882a593Smuzhiyun struct rockchip_iodomain_supply *supply)
715*4882a593Smuzhiyun {
716*4882a593Smuzhiyun }
717*4882a593Smuzhiyun #endif
718*4882a593Smuzhiyun
rv1126_iodomain_notify(struct notifier_block * nb,unsigned long event,void * data)719*4882a593Smuzhiyun static int rv1126_iodomain_notify(struct notifier_block *nb,
720*4882a593Smuzhiyun unsigned long event,
721*4882a593Smuzhiyun void *data)
722*4882a593Smuzhiyun {
723*4882a593Smuzhiyun struct rockchip_iodomain_supply *supply =
724*4882a593Smuzhiyun container_of(nb, struct rockchip_iodomain_supply, nb);
725*4882a593Smuzhiyun int uV;
726*4882a593Smuzhiyun int ret;
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun if (event & REGULATOR_EVENT_PRE_VOLTAGE_CHANGE) {
729*4882a593Smuzhiyun struct pre_voltage_change_data *pvc_data = data;
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun uV = max_t(unsigned long, pvc_data->old_uV, pvc_data->max_uV);
732*4882a593Smuzhiyun } else if (event & (REGULATOR_EVENT_VOLTAGE_CHANGE |
733*4882a593Smuzhiyun REGULATOR_EVENT_ABORT_VOLTAGE_CHANGE)) {
734*4882a593Smuzhiyun uV = (unsigned long)data;
735*4882a593Smuzhiyun } else if (event & REGULATOR_EVENT_DISABLE) {
736*4882a593Smuzhiyun uV = MAX_VOLTAGE_3_3;
737*4882a593Smuzhiyun } else if (event & REGULATOR_EVENT_ENABLE) {
738*4882a593Smuzhiyun if (!data)
739*4882a593Smuzhiyun return NOTIFY_BAD;
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun uV = (unsigned long)data;
742*4882a593Smuzhiyun } else {
743*4882a593Smuzhiyun return NOTIFY_OK;
744*4882a593Smuzhiyun }
745*4882a593Smuzhiyun
746*4882a593Smuzhiyun if (uV <= 0) {
747*4882a593Smuzhiyun dev_err(supply->iod->dev, "Voltage invalid: %d\n", uV);
748*4882a593Smuzhiyun return NOTIFY_BAD;
749*4882a593Smuzhiyun }
750*4882a593Smuzhiyun
751*4882a593Smuzhiyun dev_dbg(supply->iod->dev, "Setting to %d\n", uV);
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun if (uV > MAX_VOLTAGE_3_3) {
754*4882a593Smuzhiyun dev_err(supply->iod->dev, "Voltage too high: %d\n", uV);
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun if (event == REGULATOR_EVENT_PRE_VOLTAGE_CHANGE)
757*4882a593Smuzhiyun return NOTIFY_BAD;
758*4882a593Smuzhiyun }
759*4882a593Smuzhiyun
760*4882a593Smuzhiyun ret = supply->iod->write(supply, uV);
761*4882a593Smuzhiyun if (ret && event == REGULATOR_EVENT_PRE_VOLTAGE_CHANGE)
762*4882a593Smuzhiyun return NOTIFY_BAD;
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun dev_dbg(supply->iod->dev, "Setting to %d done\n", uV);
765*4882a593Smuzhiyun return NOTIFY_OK;
766*4882a593Smuzhiyun }
767*4882a593Smuzhiyun
rockchip_iodomain_probe(struct platform_device * pdev)768*4882a593Smuzhiyun static int rockchip_iodomain_probe(struct platform_device *pdev)
769*4882a593Smuzhiyun {
770*4882a593Smuzhiyun struct device_node *np = pdev->dev.of_node;
771*4882a593Smuzhiyun const struct of_device_id *match;
772*4882a593Smuzhiyun struct rockchip_iodomain *iod;
773*4882a593Smuzhiyun struct device *parent;
774*4882a593Smuzhiyun int i, ret = 0;
775*4882a593Smuzhiyun
776*4882a593Smuzhiyun if (!np)
777*4882a593Smuzhiyun return -ENODEV;
778*4882a593Smuzhiyun
779*4882a593Smuzhiyun iod = devm_kzalloc(&pdev->dev, sizeof(*iod), GFP_KERNEL);
780*4882a593Smuzhiyun if (!iod)
781*4882a593Smuzhiyun return -ENOMEM;
782*4882a593Smuzhiyun
783*4882a593Smuzhiyun iod->dev = &pdev->dev;
784*4882a593Smuzhiyun platform_set_drvdata(pdev, iod);
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun match = of_match_node(rockchip_iodomain_match, np);
787*4882a593Smuzhiyun iod->soc_data = match->data;
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun if (iod->soc_data->write)
790*4882a593Smuzhiyun iod->write = iod->soc_data->write;
791*4882a593Smuzhiyun else
792*4882a593Smuzhiyun iod->write = rockchip_iodomain_write;
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun parent = pdev->dev.parent;
795*4882a593Smuzhiyun if (parent && parent->of_node) {
796*4882a593Smuzhiyun iod->grf = syscon_node_to_regmap(parent->of_node);
797*4882a593Smuzhiyun } else {
798*4882a593Smuzhiyun dev_dbg(&pdev->dev, "falling back to old binding\n");
799*4882a593Smuzhiyun iod->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
800*4882a593Smuzhiyun }
801*4882a593Smuzhiyun
802*4882a593Smuzhiyun if (IS_ERR(iod->grf)) {
803*4882a593Smuzhiyun dev_err(&pdev->dev, "couldn't find grf regmap\n");
804*4882a593Smuzhiyun return PTR_ERR(iod->grf);
805*4882a593Smuzhiyun }
806*4882a593Smuzhiyun
807*4882a593Smuzhiyun for (i = 0; i < MAX_SUPPLIES; i++) {
808*4882a593Smuzhiyun const char *supply_name = iod->soc_data->supply_names[i];
809*4882a593Smuzhiyun struct rockchip_iodomain_supply *supply = &iod->supplies[i];
810*4882a593Smuzhiyun struct regulator *reg;
811*4882a593Smuzhiyun int uV;
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun if (!supply_name)
814*4882a593Smuzhiyun continue;
815*4882a593Smuzhiyun
816*4882a593Smuzhiyun /* PX30s pmuio1 not support 1v8 mode switch. */
817*4882a593Smuzhiyun if (soc_is_px30s() && (!strcmp(supply_name, "pmuio1")))
818*4882a593Smuzhiyun continue;
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun reg = devm_regulator_get_optional(iod->dev, supply_name);
821*4882a593Smuzhiyun if (IS_ERR(reg)) {
822*4882a593Smuzhiyun ret = PTR_ERR(reg);
823*4882a593Smuzhiyun
824*4882a593Smuzhiyun /* If a supply wasn't specified, that's OK */
825*4882a593Smuzhiyun if (ret == -ENODEV)
826*4882a593Smuzhiyun continue;
827*4882a593Smuzhiyun else if (ret != -EPROBE_DEFER)
828*4882a593Smuzhiyun dev_err(iod->dev, "couldn't get regulator %s\n",
829*4882a593Smuzhiyun supply_name);
830*4882a593Smuzhiyun goto unreg_notify;
831*4882a593Smuzhiyun }
832*4882a593Smuzhiyun
833*4882a593Smuzhiyun /* set initial correct value */
834*4882a593Smuzhiyun uV = regulator_get_voltage(reg);
835*4882a593Smuzhiyun
836*4882a593Smuzhiyun /* must be a regulator we can get the voltage of */
837*4882a593Smuzhiyun if (uV < 0) {
838*4882a593Smuzhiyun dev_err(iod->dev, "Can't determine voltage: %s\n",
839*4882a593Smuzhiyun supply_name);
840*4882a593Smuzhiyun ret = uV;
841*4882a593Smuzhiyun goto unreg_notify;
842*4882a593Smuzhiyun }
843*4882a593Smuzhiyun
844*4882a593Smuzhiyun if (uV > MAX_VOLTAGE_3_3) {
845*4882a593Smuzhiyun dev_crit(iod->dev,
846*4882a593Smuzhiyun "%d uV is too high. May damage SoC!\n",
847*4882a593Smuzhiyun uV);
848*4882a593Smuzhiyun ret = -EINVAL;
849*4882a593Smuzhiyun goto unreg_notify;
850*4882a593Smuzhiyun }
851*4882a593Smuzhiyun
852*4882a593Smuzhiyun /* setup our supply */
853*4882a593Smuzhiyun supply->idx = i;
854*4882a593Smuzhiyun supply->iod = iod;
855*4882a593Smuzhiyun supply->reg = reg;
856*4882a593Smuzhiyun supply->nb.notifier_call = rockchip_iodomain_notify;
857*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_CPU_RV1126))
858*4882a593Smuzhiyun supply->nb.notifier_call = rv1126_iodomain_notify;
859*4882a593Smuzhiyun
860*4882a593Smuzhiyun ret = iod->write(supply, uV);
861*4882a593Smuzhiyun if (ret) {
862*4882a593Smuzhiyun supply->reg = NULL;
863*4882a593Smuzhiyun goto unreg_notify;
864*4882a593Smuzhiyun }
865*4882a593Smuzhiyun
866*4882a593Smuzhiyun /* register regulator notifier */
867*4882a593Smuzhiyun ret = regulator_register_notifier(reg, &supply->nb);
868*4882a593Smuzhiyun if (ret) {
869*4882a593Smuzhiyun dev_err(&pdev->dev,
870*4882a593Smuzhiyun "regulator notifier request failed\n");
871*4882a593Smuzhiyun supply->reg = NULL;
872*4882a593Smuzhiyun goto unreg_notify;
873*4882a593Smuzhiyun }
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun rockchip_iodomain_dump(pdev, supply);
876*4882a593Smuzhiyun }
877*4882a593Smuzhiyun
878*4882a593Smuzhiyun if (iod->soc_data->init)
879*4882a593Smuzhiyun iod->soc_data->init(iod);
880*4882a593Smuzhiyun
881*4882a593Smuzhiyun return 0;
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun unreg_notify:
884*4882a593Smuzhiyun for (i = MAX_SUPPLIES - 1; i >= 0; i--) {
885*4882a593Smuzhiyun struct rockchip_iodomain_supply *io_supply = &iod->supplies[i];
886*4882a593Smuzhiyun
887*4882a593Smuzhiyun if (io_supply->reg)
888*4882a593Smuzhiyun regulator_unregister_notifier(io_supply->reg,
889*4882a593Smuzhiyun &io_supply->nb);
890*4882a593Smuzhiyun }
891*4882a593Smuzhiyun
892*4882a593Smuzhiyun return ret;
893*4882a593Smuzhiyun }
894*4882a593Smuzhiyun
rockchip_iodomain_remove(struct platform_device * pdev)895*4882a593Smuzhiyun static int rockchip_iodomain_remove(struct platform_device *pdev)
896*4882a593Smuzhiyun {
897*4882a593Smuzhiyun struct rockchip_iodomain *iod = platform_get_drvdata(pdev);
898*4882a593Smuzhiyun int i;
899*4882a593Smuzhiyun
900*4882a593Smuzhiyun for (i = MAX_SUPPLIES - 1; i >= 0; i--) {
901*4882a593Smuzhiyun struct rockchip_iodomain_supply *io_supply = &iod->supplies[i];
902*4882a593Smuzhiyun
903*4882a593Smuzhiyun if (io_supply->reg)
904*4882a593Smuzhiyun regulator_unregister_notifier(io_supply->reg,
905*4882a593Smuzhiyun &io_supply->nb);
906*4882a593Smuzhiyun }
907*4882a593Smuzhiyun
908*4882a593Smuzhiyun return 0;
909*4882a593Smuzhiyun }
910*4882a593Smuzhiyun
911*4882a593Smuzhiyun static struct platform_driver rockchip_iodomain_driver = {
912*4882a593Smuzhiyun .probe = rockchip_iodomain_probe,
913*4882a593Smuzhiyun .remove = rockchip_iodomain_remove,
914*4882a593Smuzhiyun .driver = {
915*4882a593Smuzhiyun .name = "rockchip-iodomain",
916*4882a593Smuzhiyun .of_match_table = rockchip_iodomain_match,
917*4882a593Smuzhiyun },
918*4882a593Smuzhiyun };
919*4882a593Smuzhiyun
rockchip_iodomain_driver_init(void)920*4882a593Smuzhiyun static int __init rockchip_iodomain_driver_init(void)
921*4882a593Smuzhiyun {
922*4882a593Smuzhiyun return platform_driver_register(&rockchip_iodomain_driver);
923*4882a593Smuzhiyun }
924*4882a593Smuzhiyun fs_initcall(rockchip_iodomain_driver_init);
925*4882a593Smuzhiyun
rockchip_iodomain_driver_exit(void)926*4882a593Smuzhiyun static void __exit rockchip_iodomain_driver_exit(void)
927*4882a593Smuzhiyun {
928*4882a593Smuzhiyun platform_driver_unregister(&rockchip_iodomain_driver);
929*4882a593Smuzhiyun }
930*4882a593Smuzhiyun module_exit(rockchip_iodomain_driver_exit);
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun MODULE_DESCRIPTION("Rockchip IO-domain driver");
933*4882a593Smuzhiyun MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
934*4882a593Smuzhiyun MODULE_AUTHOR("Doug Anderson <dianders@chromium.org>");
935*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
936