1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * R9A06G032 Second CA7 enabler.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2018 Renesas Electronics Europe Limited
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
8*4882a593Smuzhiyun * Derived from actions,s500-smp
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun #include <linux/of.h>
13*4882a593Smuzhiyun #include <linux/of_address.h>
14*4882a593Smuzhiyun #include <linux/smp.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /*
17*4882a593Smuzhiyun * The second CPU is parked in ROM at boot time. It requires waking it after
18*4882a593Smuzhiyun * writing an address into the BOOTADDR register of sysctrl.
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * So the default value of the "cpu-release-addr" corresponds to BOOTADDR...
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun * *However* the BOOTADDR register is not available when the kernel
23*4882a593Smuzhiyun * starts in NONSEC mode.
24*4882a593Smuzhiyun *
25*4882a593Smuzhiyun * So for NONSEC mode, the bootloader re-parks the second CPU into a pen
26*4882a593Smuzhiyun * in SRAM, and changes the "cpu-release-addr" of linux's DT to a SRAM address,
27*4882a593Smuzhiyun * which is not restricted.
28*4882a593Smuzhiyun */
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun static void __iomem *cpu_bootaddr;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun static DEFINE_SPINLOCK(cpu_lock);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun static int
r9a06g032_smp_boot_secondary(unsigned int cpu,struct task_struct * idle)35*4882a593Smuzhiyun r9a06g032_smp_boot_secondary(unsigned int cpu,
36*4882a593Smuzhiyun struct task_struct *idle)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun if (!cpu_bootaddr)
39*4882a593Smuzhiyun return -ENODEV;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun spin_lock(&cpu_lock);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun writel(__pa_symbol(secondary_startup), cpu_bootaddr);
44*4882a593Smuzhiyun arch_send_wakeup_ipi_mask(cpumask_of(cpu));
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun spin_unlock(&cpu_lock);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun return 0;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
r9a06g032_smp_prepare_cpus(unsigned int max_cpus)51*4882a593Smuzhiyun static void __init r9a06g032_smp_prepare_cpus(unsigned int max_cpus)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun struct device_node *dn;
54*4882a593Smuzhiyun int ret = -EINVAL, dns;
55*4882a593Smuzhiyun u32 bootaddr;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun dn = of_get_cpu_node(1, NULL);
58*4882a593Smuzhiyun if (!dn) {
59*4882a593Smuzhiyun pr_err("CPU#1: missing device tree node\n");
60*4882a593Smuzhiyun return;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun /*
63*4882a593Smuzhiyun * Determine the address from which the CPU is polling.
64*4882a593Smuzhiyun * The bootloader *does* change this property.
65*4882a593Smuzhiyun * Note: The property can be either 64 or 32 bits, so handle both cases
66*4882a593Smuzhiyun */
67*4882a593Smuzhiyun if (of_find_property(dn, "cpu-release-addr", &dns)) {
68*4882a593Smuzhiyun if (dns == sizeof(u64)) {
69*4882a593Smuzhiyun u64 temp;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun ret = of_property_read_u64(dn,
72*4882a593Smuzhiyun "cpu-release-addr", &temp);
73*4882a593Smuzhiyun bootaddr = temp;
74*4882a593Smuzhiyun } else {
75*4882a593Smuzhiyun ret = of_property_read_u32(dn,
76*4882a593Smuzhiyun "cpu-release-addr",
77*4882a593Smuzhiyun &bootaddr);
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun of_node_put(dn);
81*4882a593Smuzhiyun if (ret) {
82*4882a593Smuzhiyun pr_err("CPU#1: invalid cpu-release-addr property\n");
83*4882a593Smuzhiyun return;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun pr_info("CPU#1: cpu-release-addr %08x\n", bootaddr);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun cpu_bootaddr = ioremap(bootaddr, sizeof(bootaddr));
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun static const struct smp_operations r9a06g032_smp_ops __initconst = {
91*4882a593Smuzhiyun .smp_prepare_cpus = r9a06g032_smp_prepare_cpus,
92*4882a593Smuzhiyun .smp_boot_secondary = r9a06g032_smp_boot_secondary,
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun CPU_METHOD_OF_DECLARE(r9a06g032_smp,
96*4882a593Smuzhiyun "renesas,r9a06g032-smp", &r9a06g032_smp_ops);
97