1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Renesas R-Car V3H System Controller 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2018 Renesas Electronics Corp. 6*4882a593Smuzhiyun * Copyright (C) 2018 Cogent Embedded, Inc. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/bits.h> 10*4882a593Smuzhiyun #include <linux/kernel.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <dt-bindings/power/r8a77980-sysc.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include "rcar-sysc.h" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun static const struct rcar_sysc_area r8a77980_areas[] __initconst = { 17*4882a593Smuzhiyun { "always-on", 0, 0, R8A77980_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, 18*4882a593Smuzhiyun { "ca53-scu", 0x140, 0, R8A77980_PD_CA53_SCU, R8A77980_PD_ALWAYS_ON, 19*4882a593Smuzhiyun PD_SCU }, 20*4882a593Smuzhiyun { "ca53-cpu0", 0x200, 0, R8A77980_PD_CA53_CPU0, R8A77980_PD_CA53_SCU, 21*4882a593Smuzhiyun PD_CPU_NOCR }, 22*4882a593Smuzhiyun { "ca53-cpu1", 0x200, 1, R8A77980_PD_CA53_CPU1, R8A77980_PD_CA53_SCU, 23*4882a593Smuzhiyun PD_CPU_NOCR }, 24*4882a593Smuzhiyun { "ca53-cpu2", 0x200, 2, R8A77980_PD_CA53_CPU2, R8A77980_PD_CA53_SCU, 25*4882a593Smuzhiyun PD_CPU_NOCR }, 26*4882a593Smuzhiyun { "ca53-cpu3", 0x200, 3, R8A77980_PD_CA53_CPU3, R8A77980_PD_CA53_SCU, 27*4882a593Smuzhiyun PD_CPU_NOCR }, 28*4882a593Smuzhiyun { "cr7", 0x240, 0, R8A77980_PD_CR7, R8A77980_PD_ALWAYS_ON }, 29*4882a593Smuzhiyun { "a3ir", 0x180, 0, R8A77980_PD_A3IR, R8A77980_PD_ALWAYS_ON }, 30*4882a593Smuzhiyun { "a2ir0", 0x400, 0, R8A77980_PD_A2IR0, R8A77980_PD_A3IR }, 31*4882a593Smuzhiyun { "a2ir1", 0x400, 1, R8A77980_PD_A2IR1, R8A77980_PD_A3IR }, 32*4882a593Smuzhiyun { "a2ir2", 0x400, 2, R8A77980_PD_A2IR2, R8A77980_PD_A3IR }, 33*4882a593Smuzhiyun { "a2ir3", 0x400, 3, R8A77980_PD_A2IR3, R8A77980_PD_A3IR }, 34*4882a593Smuzhiyun { "a2ir4", 0x400, 4, R8A77980_PD_A2IR4, R8A77980_PD_A3IR }, 35*4882a593Smuzhiyun { "a2ir5", 0x400, 5, R8A77980_PD_A2IR5, R8A77980_PD_A3IR }, 36*4882a593Smuzhiyun { "a2sc0", 0x400, 6, R8A77980_PD_A2SC0, R8A77980_PD_A3IR }, 37*4882a593Smuzhiyun { "a2sc1", 0x400, 7, R8A77980_PD_A2SC1, R8A77980_PD_A3IR }, 38*4882a593Smuzhiyun { "a2sc2", 0x400, 8, R8A77980_PD_A2SC2, R8A77980_PD_A3IR }, 39*4882a593Smuzhiyun { "a2sc3", 0x400, 9, R8A77980_PD_A2SC3, R8A77980_PD_A3IR }, 40*4882a593Smuzhiyun { "a2sc4", 0x400, 10, R8A77980_PD_A2SC4, R8A77980_PD_A3IR }, 41*4882a593Smuzhiyun { "a2dp0", 0x400, 11, R8A77980_PD_A2DP0, R8A77980_PD_A3IR }, 42*4882a593Smuzhiyun { "a2dp1", 0x400, 12, R8A77980_PD_A2DP1, R8A77980_PD_A3IR }, 43*4882a593Smuzhiyun { "a2cn", 0x400, 13, R8A77980_PD_A2CN, R8A77980_PD_A3IR }, 44*4882a593Smuzhiyun { "a3vip0", 0x2c0, 0, R8A77980_PD_A3VIP0, R8A77980_PD_ALWAYS_ON }, 45*4882a593Smuzhiyun { "a3vip1", 0x300, 0, R8A77980_PD_A3VIP1, R8A77980_PD_ALWAYS_ON }, 46*4882a593Smuzhiyun { "a3vip2", 0x280, 0, R8A77980_PD_A3VIP2, R8A77980_PD_ALWAYS_ON }, 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun const struct rcar_sysc_info r8a77980_sysc_info __initconst = { 50*4882a593Smuzhiyun .areas = r8a77980_areas, 51*4882a593Smuzhiyun .num_areas = ARRAY_SIZE(r8a77980_areas), 52*4882a593Smuzhiyun .extmask_offs = 0x138, 53*4882a593Smuzhiyun .extmask_val = BIT(0), 54*4882a593Smuzhiyun }; 55