1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Renesas R-Car V3M System Controller 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2017 Cogent Embedded Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <linux/bits.h> 9*4882a593Smuzhiyun #include <linux/kernel.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <dt-bindings/power/r8a77970-sysc.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include "rcar-sysc.h" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun static const struct rcar_sysc_area r8a77970_areas[] __initconst = { 16*4882a593Smuzhiyun { "always-on", 0, 0, R8A77970_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, 17*4882a593Smuzhiyun { "ca53-scu", 0x140, 0, R8A77970_PD_CA53_SCU, R8A77970_PD_ALWAYS_ON, 18*4882a593Smuzhiyun PD_SCU }, 19*4882a593Smuzhiyun { "ca53-cpu0", 0x200, 0, R8A77970_PD_CA53_CPU0, R8A77970_PD_CA53_SCU, 20*4882a593Smuzhiyun PD_CPU_NOCR }, 21*4882a593Smuzhiyun { "ca53-cpu1", 0x200, 1, R8A77970_PD_CA53_CPU1, R8A77970_PD_CA53_SCU, 22*4882a593Smuzhiyun PD_CPU_NOCR }, 23*4882a593Smuzhiyun { "a3ir", 0x180, 0, R8A77970_PD_A3IR, R8A77970_PD_ALWAYS_ON }, 24*4882a593Smuzhiyun { "a2ir0", 0x400, 0, R8A77970_PD_A2IR0, R8A77970_PD_A3IR }, 25*4882a593Smuzhiyun { "a2ir1", 0x400, 1, R8A77970_PD_A2IR1, R8A77970_PD_A3IR }, 26*4882a593Smuzhiyun { "a2dp", 0x400, 2, R8A77970_PD_A2DP, R8A77970_PD_A3IR }, 27*4882a593Smuzhiyun { "a2cn", 0x400, 3, R8A77970_PD_A2CN, R8A77970_PD_A3IR }, 28*4882a593Smuzhiyun { "a2sc0", 0x400, 4, R8A77970_PD_A2SC0, R8A77970_PD_A3IR }, 29*4882a593Smuzhiyun { "a2sc1", 0x400, 5, R8A77970_PD_A2SC1, R8A77970_PD_A3IR }, 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun const struct rcar_sysc_info r8a77970_sysc_info __initconst = { 33*4882a593Smuzhiyun .areas = r8a77970_areas, 34*4882a593Smuzhiyun .num_areas = ARRAY_SIZE(r8a77970_areas), 35*4882a593Smuzhiyun .extmask_offs = 0x1b0, 36*4882a593Smuzhiyun .extmask_val = BIT(0), 37*4882a593Smuzhiyun }; 38