1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Renesas R-Car M3-W/W+ System Controller
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2016 Glider bvba
6*4882a593Smuzhiyun * Copyright (C) 2018-2019 Renesas Electronics Corporation
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/bits.h>
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <dt-bindings/power/r8a7796-sysc.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include "rcar-sysc.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun static struct rcar_sysc_area r8a7796_areas[] __initdata = {
17*4882a593Smuzhiyun { "always-on", 0, 0, R8A7796_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
18*4882a593Smuzhiyun { "ca57-scu", 0x1c0, 0, R8A7796_PD_CA57_SCU, R8A7796_PD_ALWAYS_ON,
19*4882a593Smuzhiyun PD_SCU },
20*4882a593Smuzhiyun { "ca57-cpu0", 0x80, 0, R8A7796_PD_CA57_CPU0, R8A7796_PD_CA57_SCU,
21*4882a593Smuzhiyun PD_CPU_NOCR },
22*4882a593Smuzhiyun { "ca57-cpu1", 0x80, 1, R8A7796_PD_CA57_CPU1, R8A7796_PD_CA57_SCU,
23*4882a593Smuzhiyun PD_CPU_NOCR },
24*4882a593Smuzhiyun { "ca53-scu", 0x140, 0, R8A7796_PD_CA53_SCU, R8A7796_PD_ALWAYS_ON,
25*4882a593Smuzhiyun PD_SCU },
26*4882a593Smuzhiyun { "ca53-cpu0", 0x200, 0, R8A7796_PD_CA53_CPU0, R8A7796_PD_CA53_SCU,
27*4882a593Smuzhiyun PD_CPU_NOCR },
28*4882a593Smuzhiyun { "ca53-cpu1", 0x200, 1, R8A7796_PD_CA53_CPU1, R8A7796_PD_CA53_SCU,
29*4882a593Smuzhiyun PD_CPU_NOCR },
30*4882a593Smuzhiyun { "ca53-cpu2", 0x200, 2, R8A7796_PD_CA53_CPU2, R8A7796_PD_CA53_SCU,
31*4882a593Smuzhiyun PD_CPU_NOCR },
32*4882a593Smuzhiyun { "ca53-cpu3", 0x200, 3, R8A7796_PD_CA53_CPU3, R8A7796_PD_CA53_SCU,
33*4882a593Smuzhiyun PD_CPU_NOCR },
34*4882a593Smuzhiyun { "cr7", 0x240, 0, R8A7796_PD_CR7, R8A7796_PD_ALWAYS_ON },
35*4882a593Smuzhiyun { "a3vc", 0x380, 0, R8A7796_PD_A3VC, R8A7796_PD_ALWAYS_ON },
36*4882a593Smuzhiyun { "a2vc0", 0x3c0, 0, R8A7796_PD_A2VC0, R8A7796_PD_A3VC },
37*4882a593Smuzhiyun { "a2vc1", 0x3c0, 1, R8A7796_PD_A2VC1, R8A7796_PD_A3VC },
38*4882a593Smuzhiyun { "3dg-a", 0x100, 0, R8A7796_PD_3DG_A, R8A7796_PD_ALWAYS_ON },
39*4882a593Smuzhiyun { "3dg-b", 0x100, 1, R8A7796_PD_3DG_B, R8A7796_PD_3DG_A },
40*4882a593Smuzhiyun { "a3ir", 0x180, 0, R8A7796_PD_A3IR, R8A7796_PD_ALWAYS_ON },
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #ifdef CONFIG_SYSC_R8A77960
45*4882a593Smuzhiyun const struct rcar_sysc_info r8a77960_sysc_info __initconst = {
46*4882a593Smuzhiyun .areas = r8a7796_areas,
47*4882a593Smuzhiyun .num_areas = ARRAY_SIZE(r8a7796_areas),
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun #endif /* CONFIG_SYSC_R8A77960 */
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun #ifdef CONFIG_SYSC_R8A77961
r8a77961_sysc_init(void)52*4882a593Smuzhiyun static int __init r8a77961_sysc_init(void)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun rcar_sysc_nullify(r8a7796_areas, ARRAY_SIZE(r8a7796_areas),
55*4882a593Smuzhiyun R8A7796_PD_A2VC0);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun return 0;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun const struct rcar_sysc_info r8a77961_sysc_info __initconst = {
61*4882a593Smuzhiyun .init = r8a77961_sysc_init,
62*4882a593Smuzhiyun .areas = r8a7796_areas,
63*4882a593Smuzhiyun .num_areas = ARRAY_SIZE(r8a7796_areas),
64*4882a593Smuzhiyun .extmask_offs = 0x2f8,
65*4882a593Smuzhiyun .extmask_val = BIT(0),
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun #endif /* CONFIG_SYSC_R8A77961 */
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