1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Renesas R-Car H3 System Controller
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2016-2017 Glider bvba
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/bits.h>
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/sys_soc.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <dt-bindings/power/r8a7795-sysc.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include "rcar-sysc.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun static struct rcar_sysc_area r8a7795_areas[] __initdata = {
17*4882a593Smuzhiyun { "always-on", 0, 0, R8A7795_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
18*4882a593Smuzhiyun { "ca57-scu", 0x1c0, 0, R8A7795_PD_CA57_SCU, R8A7795_PD_ALWAYS_ON,
19*4882a593Smuzhiyun PD_SCU },
20*4882a593Smuzhiyun { "ca57-cpu0", 0x80, 0, R8A7795_PD_CA57_CPU0, R8A7795_PD_CA57_SCU,
21*4882a593Smuzhiyun PD_CPU_NOCR },
22*4882a593Smuzhiyun { "ca57-cpu1", 0x80, 1, R8A7795_PD_CA57_CPU1, R8A7795_PD_CA57_SCU,
23*4882a593Smuzhiyun PD_CPU_NOCR },
24*4882a593Smuzhiyun { "ca57-cpu2", 0x80, 2, R8A7795_PD_CA57_CPU2, R8A7795_PD_CA57_SCU,
25*4882a593Smuzhiyun PD_CPU_NOCR },
26*4882a593Smuzhiyun { "ca57-cpu3", 0x80, 3, R8A7795_PD_CA57_CPU3, R8A7795_PD_CA57_SCU,
27*4882a593Smuzhiyun PD_CPU_NOCR },
28*4882a593Smuzhiyun { "ca53-scu", 0x140, 0, R8A7795_PD_CA53_SCU, R8A7795_PD_ALWAYS_ON,
29*4882a593Smuzhiyun PD_SCU },
30*4882a593Smuzhiyun { "ca53-cpu0", 0x200, 0, R8A7795_PD_CA53_CPU0, R8A7795_PD_CA53_SCU,
31*4882a593Smuzhiyun PD_CPU_NOCR },
32*4882a593Smuzhiyun { "ca53-cpu1", 0x200, 1, R8A7795_PD_CA53_CPU1, R8A7795_PD_CA53_SCU,
33*4882a593Smuzhiyun PD_CPU_NOCR },
34*4882a593Smuzhiyun { "ca53-cpu2", 0x200, 2, R8A7795_PD_CA53_CPU2, R8A7795_PD_CA53_SCU,
35*4882a593Smuzhiyun PD_CPU_NOCR },
36*4882a593Smuzhiyun { "ca53-cpu3", 0x200, 3, R8A7795_PD_CA53_CPU3, R8A7795_PD_CA53_SCU,
37*4882a593Smuzhiyun PD_CPU_NOCR },
38*4882a593Smuzhiyun { "a3vp", 0x340, 0, R8A7795_PD_A3VP, R8A7795_PD_ALWAYS_ON },
39*4882a593Smuzhiyun { "cr7", 0x240, 0, R8A7795_PD_CR7, R8A7795_PD_ALWAYS_ON },
40*4882a593Smuzhiyun { "a3vc", 0x380, 0, R8A7795_PD_A3VC, R8A7795_PD_ALWAYS_ON },
41*4882a593Smuzhiyun /* A2VC0 exists on ES1.x only */
42*4882a593Smuzhiyun { "a2vc0", 0x3c0, 0, R8A7795_PD_A2VC0, R8A7795_PD_A3VC },
43*4882a593Smuzhiyun { "a2vc1", 0x3c0, 1, R8A7795_PD_A2VC1, R8A7795_PD_A3VC },
44*4882a593Smuzhiyun { "3dg-a", 0x100, 0, R8A7795_PD_3DG_A, R8A7795_PD_ALWAYS_ON },
45*4882a593Smuzhiyun { "3dg-b", 0x100, 1, R8A7795_PD_3DG_B, R8A7795_PD_3DG_A },
46*4882a593Smuzhiyun { "3dg-c", 0x100, 2, R8A7795_PD_3DG_C, R8A7795_PD_3DG_B },
47*4882a593Smuzhiyun { "3dg-d", 0x100, 3, R8A7795_PD_3DG_D, R8A7795_PD_3DG_C },
48*4882a593Smuzhiyun { "3dg-e", 0x100, 4, R8A7795_PD_3DG_E, R8A7795_PD_3DG_D },
49*4882a593Smuzhiyun { "a3ir", 0x180, 0, R8A7795_PD_A3IR, R8A7795_PD_ALWAYS_ON },
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /*
54*4882a593Smuzhiyun * Fixups for R-Car H3 revisions
55*4882a593Smuzhiyun */
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #define HAS_A2VC0 BIT(0) /* Power domain A2VC0 is present */
58*4882a593Smuzhiyun #define NO_EXTMASK BIT(1) /* Missing SYSCEXTMASK register */
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun static const struct soc_device_attribute r8a7795_quirks_match[] __initconst = {
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun .soc_id = "r8a7795", .revision = "ES1.*",
63*4882a593Smuzhiyun .data = (void *)(HAS_A2VC0 | NO_EXTMASK),
64*4882a593Smuzhiyun }, {
65*4882a593Smuzhiyun .soc_id = "r8a7795", .revision = "ES2.*",
66*4882a593Smuzhiyun .data = (void *)(NO_EXTMASK),
67*4882a593Smuzhiyun },
68*4882a593Smuzhiyun { /* sentinel */ }
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
r8a7795_sysc_init(void)71*4882a593Smuzhiyun static int __init r8a7795_sysc_init(void)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun const struct soc_device_attribute *attr;
74*4882a593Smuzhiyun u32 quirks = 0;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun attr = soc_device_match(r8a7795_quirks_match);
77*4882a593Smuzhiyun if (attr)
78*4882a593Smuzhiyun quirks = (uintptr_t)attr->data;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun if (!(quirks & HAS_A2VC0))
81*4882a593Smuzhiyun rcar_sysc_nullify(r8a7795_areas, ARRAY_SIZE(r8a7795_areas),
82*4882a593Smuzhiyun R8A7795_PD_A2VC0);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun if (quirks & NO_EXTMASK)
85*4882a593Smuzhiyun r8a7795_sysc_info.extmask_val = 0;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun return 0;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun struct rcar_sysc_info r8a7795_sysc_info __initdata = {
91*4882a593Smuzhiyun .init = r8a7795_sysc_init,
92*4882a593Smuzhiyun .areas = r8a7795_areas,
93*4882a593Smuzhiyun .num_areas = ARRAY_SIZE(r8a7795_areas),
94*4882a593Smuzhiyun .extmask_offs = 0x2f8,
95*4882a593Smuzhiyun .extmask_val = BIT(0),
96*4882a593Smuzhiyun };
97