1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Renesas RZ/G2H System Controller 4*4882a593Smuzhiyun * Copyright (C) 2020 Renesas Electronics Corp. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Based on Renesas R-Car H3 System Controller 7*4882a593Smuzhiyun * Copyright (C) 2016-2017 Glider bvba 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/kernel.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <dt-bindings/power/r8a774e1-sysc.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include "rcar-sysc.h" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun static const struct rcar_sysc_area r8a774e1_areas[] __initconst = { 17*4882a593Smuzhiyun { "always-on", 0, 0, R8A774E1_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, 18*4882a593Smuzhiyun { "ca57-scu", 0x1c0, 0, R8A774E1_PD_CA57_SCU, R8A774E1_PD_ALWAYS_ON, PD_SCU }, 19*4882a593Smuzhiyun { "ca57-cpu0", 0x80, 0, R8A774E1_PD_CA57_CPU0, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR }, 20*4882a593Smuzhiyun { "ca57-cpu1", 0x80, 1, R8A774E1_PD_CA57_CPU1, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR }, 21*4882a593Smuzhiyun { "ca57-cpu2", 0x80, 2, R8A774E1_PD_CA57_CPU2, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR }, 22*4882a593Smuzhiyun { "ca57-cpu3", 0x80, 3, R8A774E1_PD_CA57_CPU3, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR }, 23*4882a593Smuzhiyun { "ca53-scu", 0x140, 0, R8A774E1_PD_CA53_SCU, R8A774E1_PD_ALWAYS_ON, PD_SCU }, 24*4882a593Smuzhiyun { "ca53-cpu0", 0x200, 0, R8A774E1_PD_CA53_CPU0, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR }, 25*4882a593Smuzhiyun { "ca53-cpu1", 0x200, 1, R8A774E1_PD_CA53_CPU1, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR }, 26*4882a593Smuzhiyun { "ca53-cpu2", 0x200, 2, R8A774E1_PD_CA53_CPU2, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR }, 27*4882a593Smuzhiyun { "ca53-cpu3", 0x200, 3, R8A774E1_PD_CA53_CPU3, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR }, 28*4882a593Smuzhiyun { "a3vp", 0x340, 0, R8A774E1_PD_A3VP, R8A774E1_PD_ALWAYS_ON }, 29*4882a593Smuzhiyun { "a3vc", 0x380, 0, R8A774E1_PD_A3VC, R8A774E1_PD_ALWAYS_ON }, 30*4882a593Smuzhiyun { "a2vc1", 0x3c0, 1, R8A774E1_PD_A2VC1, R8A774E1_PD_A3VC }, 31*4882a593Smuzhiyun { "3dg-a", 0x100, 0, R8A774E1_PD_3DG_A, R8A774E1_PD_ALWAYS_ON }, 32*4882a593Smuzhiyun { "3dg-b", 0x100, 1, R8A774E1_PD_3DG_B, R8A774E1_PD_3DG_A }, 33*4882a593Smuzhiyun { "3dg-c", 0x100, 2, R8A774E1_PD_3DG_C, R8A774E1_PD_3DG_B }, 34*4882a593Smuzhiyun { "3dg-d", 0x100, 3, R8A774E1_PD_3DG_D, R8A774E1_PD_3DG_C }, 35*4882a593Smuzhiyun { "3dg-e", 0x100, 4, R8A774E1_PD_3DG_E, R8A774E1_PD_3DG_D }, 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun const struct rcar_sysc_info r8a774e1_sysc_info __initconst = { 39*4882a593Smuzhiyun .areas = r8a774e1_areas, 40*4882a593Smuzhiyun .num_areas = ARRAY_SIZE(r8a774e1_areas), 41*4882a593Smuzhiyun .extmask_offs = 0x2f8, 42*4882a593Smuzhiyun .extmask_val = BIT(0), 43*4882a593Smuzhiyun }; 44