1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Renesas RZ/G2E System Controller
4*4882a593Smuzhiyun * Copyright (C) 2018 Renesas Electronics Corp.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Based on Renesas R-Car E3 System Controller
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/bits.h>
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/sys_soc.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <dt-bindings/power/r8a774c0-sysc.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include "rcar-sysc.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun static struct rcar_sysc_area r8a774c0_areas[] __initdata = {
18*4882a593Smuzhiyun { "always-on", 0, 0, R8A774C0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
19*4882a593Smuzhiyun { "ca53-scu", 0x140, 0, R8A774C0_PD_CA53_SCU, R8A774C0_PD_ALWAYS_ON,
20*4882a593Smuzhiyun PD_SCU },
21*4882a593Smuzhiyun { "ca53-cpu0", 0x200, 0, R8A774C0_PD_CA53_CPU0, R8A774C0_PD_CA53_SCU,
22*4882a593Smuzhiyun PD_CPU_NOCR },
23*4882a593Smuzhiyun { "ca53-cpu1", 0x200, 1, R8A774C0_PD_CA53_CPU1, R8A774C0_PD_CA53_SCU,
24*4882a593Smuzhiyun PD_CPU_NOCR },
25*4882a593Smuzhiyun { "a3vc", 0x380, 0, R8A774C0_PD_A3VC, R8A774C0_PD_ALWAYS_ON },
26*4882a593Smuzhiyun { "a2vc1", 0x3c0, 1, R8A774C0_PD_A2VC1, R8A774C0_PD_A3VC },
27*4882a593Smuzhiyun { "3dg-a", 0x100, 0, R8A774C0_PD_3DG_A, R8A774C0_PD_ALWAYS_ON },
28*4882a593Smuzhiyun { "3dg-b", 0x100, 1, R8A774C0_PD_3DG_B, R8A774C0_PD_3DG_A },
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* Fixups for RZ/G2E ES1.0 revision */
32*4882a593Smuzhiyun static const struct soc_device_attribute r8a774c0[] __initconst = {
33*4882a593Smuzhiyun { .soc_id = "r8a774c0", .revision = "ES1.0" },
34*4882a593Smuzhiyun { /* sentinel */ }
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun
r8a774c0_sysc_init(void)37*4882a593Smuzhiyun static int __init r8a774c0_sysc_init(void)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun if (soc_device_match(r8a774c0)) {
40*4882a593Smuzhiyun /* Fix incorrect 3DG hierarchy */
41*4882a593Smuzhiyun swap(r8a774c0_areas[6], r8a774c0_areas[7]);
42*4882a593Smuzhiyun r8a774c0_areas[6].parent = R8A774C0_PD_ALWAYS_ON;
43*4882a593Smuzhiyun r8a774c0_areas[7].parent = R8A774C0_PD_3DG_B;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun return 0;
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun const struct rcar_sysc_info r8a774c0_sysc_info __initconst = {
50*4882a593Smuzhiyun .init = r8a774c0_sysc_init,
51*4882a593Smuzhiyun .areas = r8a774c0_areas,
52*4882a593Smuzhiyun .num_areas = ARRAY_SIZE(r8a774c0_areas),
53*4882a593Smuzhiyun .extmask_offs = 0x2f8,
54*4882a593Smuzhiyun .extmask_val = BIT(0),
55*4882a593Smuzhiyun };
56