1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Renesas RZ/G2N System Controller 4*4882a593Smuzhiyun * Copyright (C) 2019 Renesas Electronics Corp. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Based on Renesas R-Car M3-W System Controller 7*4882a593Smuzhiyun * Copyright (C) 2016 Glider bvba 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/bits.h> 11*4882a593Smuzhiyun #include <linux/kernel.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <dt-bindings/power/r8a774b1-sysc.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include "rcar-sysc.h" 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun static const struct rcar_sysc_area r8a774b1_areas[] __initconst = { 18*4882a593Smuzhiyun { "always-on", 0, 0, R8A774B1_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, 19*4882a593Smuzhiyun { "ca57-scu", 0x1c0, 0, R8A774B1_PD_CA57_SCU, R8A774B1_PD_ALWAYS_ON, 20*4882a593Smuzhiyun PD_SCU }, 21*4882a593Smuzhiyun { "ca57-cpu0", 0x80, 0, R8A774B1_PD_CA57_CPU0, R8A774B1_PD_CA57_SCU, 22*4882a593Smuzhiyun PD_CPU_NOCR }, 23*4882a593Smuzhiyun { "ca57-cpu1", 0x80, 1, R8A774B1_PD_CA57_CPU1, R8A774B1_PD_CA57_SCU, 24*4882a593Smuzhiyun PD_CPU_NOCR }, 25*4882a593Smuzhiyun { "a3vc", 0x380, 0, R8A774B1_PD_A3VC, R8A774B1_PD_ALWAYS_ON }, 26*4882a593Smuzhiyun { "a3vp", 0x340, 0, R8A774B1_PD_A3VP, R8A774B1_PD_ALWAYS_ON }, 27*4882a593Smuzhiyun { "a2vc1", 0x3c0, 1, R8A774B1_PD_A2VC1, R8A774B1_PD_A3VC }, 28*4882a593Smuzhiyun { "3dg-a", 0x100, 0, R8A774B1_PD_3DG_A, R8A774B1_PD_ALWAYS_ON }, 29*4882a593Smuzhiyun { "3dg-b", 0x100, 1, R8A774B1_PD_3DG_B, R8A774B1_PD_3DG_A }, 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun const struct rcar_sysc_info r8a774b1_sysc_info __initconst = { 33*4882a593Smuzhiyun .areas = r8a774b1_areas, 34*4882a593Smuzhiyun .num_areas = ARRAY_SIZE(r8a774b1_areas), 35*4882a593Smuzhiyun .extmask_offs = 0x2f8, 36*4882a593Smuzhiyun .extmask_val = BIT(0), 37*4882a593Smuzhiyun }; 38